DIGITAL SYSTEMS

Logic design practice

Rudolf Tracht and A.J. Han Vinck

Logic families

• IC (Integrated circuit, 1960) – Many different components on one chip

• Logic families– Similar input, output and circuit characteristics

• TTL, 1960 (Transitor-Transitor logic based on bipolar junction transistor)

• Metal-Oxide Semiconductor field effect transitor (MOSFET, 1949)

• Complementary MOS: high speed, low power consumption

Example of TTL circuits

Combinational circuits

• Given the input: – circuit provides unique output

• Propagation delay– Each gate contributes a fixed delay for passing through

it– Delay is different for each gate type

• Memoryless: no feedback

Transition time

Transition delay: amount of time needed for a logic circuit to change its output.

tr = rise time for a 0-to-1 transition

tf = fall time for a 1-to-0 transition

tr tf

Ideal case

approximation

VhminVLmax

Slide 6

Propagation Delay

Propagation delay: amount of time it takes for a change in the input signal to produce a change in the output signal

Cases: maximum; minimum; typical; worst case

–tPLH = delay for a 0-to-1 output change

–tPHL = delay for a 1-to-0 output change

Causality

Input

Output

tr

tPHL

Slide 7

Delays from Data Book

Slide 8

Delays for Logic Families

Path Delay

• Delay along path is the sum of the delays of the gates in the path

x

y

f

Critical path

• Path length in circuits differ

• Worst-case performance determined by longest path

• Longest path designated critical path

Critical path cont’d

• Delay and area optimum may differ!Suppose Area proportional to number of inputs

– Ex:1 (AB+CD)EF– Delay: D(and2) + D(or2) + D(and3)– Number of inputs = 9

– Ex:2 ABEF + CDEF– Delay: D(and4) + D(or2) – Number of inputs = 10

Timing Hazards

• different propagation delays may lead to undesirable transient

state changes, or glitches.

• A static-1 hazard is a set of input combinations that:

– Differ only in one input variable;

– Both give a logic 1 output, such that it is possible for a momentary 0 output

to occur during a transition in the differing input variable.

X

Z

Y

F A

B

Z

A

B

F

Static-1 hazard cont‘d

Principle: minterms change value but F stays 1

Situation 1: (...) + (...) + (...) = 1 + 0 + 0 = 1

Situation 2: (...) + (...) + (...) = 0 + 1 + 0 = 1

0 0 1 1

0 1 1 0

0 0 1 1

0 1 1 0

F = XZ‘ + YZ F = XZ‘ + YZ + XY

XY 00 01 11 10

0

1

Z

XY 00 01 11 10

0

1

Z

Hazard cont‘d• REMARKS:

– Static-0 hazard may occur in a product of sums

– Sum-of-products has no static-0 hazard (convince yourself)

0 1 1 0

1 1 0 0

1 1 1 1

0 0 1 1

0 1 1 0

1 1 0 0

1 1 1 1

0 0 1 1

Example:

Timing diagramsTiming diagram:

- logical behavior of signals as a function of time

- information about: delay between transitions

GO

ENB

READY

DAT

GO

READY

DAT

delay min

max

Multi-level networks: example

• F = ABD+ABE+CD+CE F = AB(D+E)+C(D+E)

• 5 gates, 14 inputs, delay 2 4 gates, 9 inputs delay 3

Fan-in and fan-out

• Fan-in: # of inputs that go into a gate

• Fan-out: # of outputs that a gate can drive

• Maximum is specified- influences the design

- exceeding degrades

signal characteristics

and functionality

4-to-1 Multiplexer

Yi0i1i2i3

s0s1

Control inputs

Dat

a in

puts

Output

Y = s1’s0’ i0 + s1’s0 i1 + s1s0’ i2 + s1s0 i3

s0 s1 Y

0 0 i0

0 1 i1

1 0 i2

1 1 i3

Multiplex cont‘d

–Selects one of two (several) inputs based on control bit

A

BC

Out = C‘•A + C•B

Multiplexer

• Multiple inputs, control input, one output

• Selects one of the many inputs as its output value depending upon the value of the control input.

• n-to-1 multiplexor has n inputs and 1 output

• n is typically 2, 4, 8, ...

• Number of control inputs = log2n.

APPLICATION: Register 1Register 2Register 3Register 4

ALU

control

Multiplex-Demultiplex-Bus

Multiplex bus demultiplex

selectors

MUX DEMUXBUSn inputs

log2 n control inputs

Mux implementation of functions

• Example F(A,B,C) = m(0,2,3,5)

1 A B C• 0

• 1• 2• 3 F • 4• 5 • 6 • 7

ABC F

0 0 0 10 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 0

Decoders• n inputs and 2n outputs Truth table

input output

EN i1 i0 y3 y2 y1 y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

Yi0i1

EN

Control input

Output

y0

y1

y2

y3

Example of address decoding

Decoders cont’d

• Assume F(A,B,C,D) = m(0,5,12,15)

00 01 11 10

00

01

11

10

1 0 1 0

0 1 0 0

0 0 1 0

0 0 0 0

Decoder cont’d

Minterm realization (useful for sparse functions)

A 0

B 1 invertor =

C ···

D 5 F

···

12

···

15

Encoder • Inverse functionality of a decoder• Given a set of line inputs, convert it to a binary number

0 i0 i1 i2 i3 i4 i5 i6 i7 y0 y1 y2

1 1 0 0 0 0 0 0 0 0 0 0

2 y0 0 1 0 0 0 0 0 0 1 0 0

3 0 0 1 0 0 0 0 0 0 1 0

4 y1 0 0 0 1 0 0 0 0 1 1 0

5 0 0 0 0 1 0 0 0 0 0 1

6 y2 0 0 0 0 0 1 0 0 1 0 1

7 0 0 0 0 0 0 1 0 0 1 1

0 0 0 0 0 0 0 1 1 1 1

y0 = i1+i3+i5+i7; y1 = i2+i3+i6+i7; y2 = i4+i5+i6+i7

Encoder/decoder cont’d

• decoder to control 1 out of 2ª devices

• encoder used for device request of service– for multiple request : use priority encoder

ex: Computer interrupt handler

Priority encoderi0 i1 i2 i3 i4 i5 i6 i7 A0 A1 A2 IDLE1 0 0 0 0 0 0 0 0 0 0 0x 1 0 0 0 0 0 0 1 0 0 0x x 1 0 0 0 0 0 0 1 0 0x x x 1 0 0 0 0 1 1 0 0x x x x 1 0 0 0 0 0 1 0x x x x x 1 0 0 1 0 1 0x x x x x x 1 0 0 1 1 0x x x x x x x 1 1 1 1 00 0 0 0 0 0 0 0 0 0 0 1

A0 = i7 + i5i6‘i7‘ + i3i4‘i5‘i6‘i7‘ + i1i2‘i3‘i4‘i5‘i6‘i7‘

Homework: write the equations for A1, A2 and IDLE

Request for service

Priority encoder

„74x148“

idle

A0

A1

A2

Tri state gates• In bus systems, tri state logic is very useful

– States are: High, Low and Disconnected

HH

H

disable

L

enable

LL X

L

enable

Ξ

H

L

disable

variation

H = +5 V 1

L = 0 V

High impedance := Hi-Z

Circuit diagram & function table

EN A B C D Q2 Q1 OUT

L L H H L off off Hi-Z

L H H H L off off Hi-Z

H L L H H on off L

H H L L L off on H

Enable ENC

B

A D

Q1

Q2

OUT

H

L

Three-state buffer

• Acts as if it is not there (high impedance)

• Allows multiple sources to share a single „party line“ with a single active user– BUS

• Go into Hi-Z state faster than come out of– To avoid „fighting“

Sharing a three-state party line

A

B

C

selector

1-bit party line

data

“high impedance” (output disconnected)

in

oe

out

Look-ahead adder

Adding 10-ary numbers: 9 + 3 = 12 = 2 + 10 carry

2-ary numbers: 01 + 01 = 0 + 2 = 10; 00 + 01 = 01

carry

For bit position i we have the following possibilities:xi 0 0 0 1 0 1 1 1yi 0 0 1 0 1 0 1 1

carry ci 0 1 0 0 1 1 0 1

sum i 0 1 1 1 0 0 0 1

ci+1 0 0 0 0 1 1 1 1

ci+1 = xi yi + (xi + yi) ci sum i = xi yi ci

Example 4 bit addition

c1 = x0 y0 + (x0 + y0) c0

c2 = x1 y1 + (x1 + y1) c1 = x1 y1 + (x1 + y1) [x0 y0 + (x0 + y0) c0 ]

c3 = x2 y2 + (x2 + y2) c2 = x2 y2 + (x2 + y2) [ [x1 y1 + (x1 + y1) [x0 y0 + (x0 + y0) c0 ]]

c4 = x3 y3 + (x3 + y3) c3 =

To speed up, all calculations are done in parallel!

CompOrg Fall 2002 - Combinational Circuits 31

4 Bit Carry Look-ahead

adderadderadderadder

0011+ 0010

Carry Generator

1100

1100

0100

0100 0

1

adder0

1

0

0

adder1

1

1

adder0

1

0

0

adder0

0

Carry Generator

0

0

Look-ahead adder cont‘d (74x283)

C0

X0

Y0

X1

Y1

X2

Y2

X3

Y3

S0

S1

S2

S3

C4

C4

X4

Y4

X5

Y5

X6

Y6

X7

Y7

S4

S5

S6

S7

C8

Adding two 8-bit numbers