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ELEC 4200 – Digital Systems Design Victor P. Nelson
Digital System on Chip (SoC) Computer-Aided Design Flow
Nvidia Tegra 2 SoC
2/29/2012 VLSI D&T Seminar - Victor P. Nelson
Tablet Applications: • Asus Eee Pad • Motorola Xoom • Samsung Galaxy • Acer Iconia Tab
Apple “A5” SoC Used in iPad 2 and iPhone 4S Manufactured by Samsung 45nm, 12.1 x 10.1 mm
Elements (unofficial): ARM Corex-A9 MPCore CPU - 1GHz NEON SIMD accelerator
Dual core PowerVR SGX543MP2 GPU Image signal processor (ISP) Audience “EarSmart” unit for noise canceling 512 MB DDR2 RAM @ 533MHz
2/29/2012 VLSI D&T Seminar - Victor P. Nelson iPhone 4 circuit board (with A4 SoC)
T.I . smartphone reference design
2/29/2012 VLSI D&T Seminar - Victor P. Nelson
Main SoC
ASIC Design Flow Behavioral
Model VHDL/Verilog
Gate-Level Netlist
Transistor-Level Netlist
Physical Layout
Map/Place/Route
DFT/BIST & ATPG
Verify Function
Verify Function
Verify Function & Timing
Verify Timing
DRC & LVS Verification
IC Mask Data/FPGA Configuration File
Standard Cell IC & FPGA/CPLD
Synthesis
Test vectors Full-custom IC
Front-End Design
Back-End Design
Typical design flow tasks
Jouni Tomberg: “System on Chip Design Flow” http://edu.cs.tut.fi/soc-sme/TombergELKOM.pdf
ASIC CAD tools available in ECE Modeling and Simulation
Modelsim, Questa-ADMS, Eldo, ADiT (Mentor Graphics) Verilog-XL, NC_Verilog, Spectre (Cadence)
Design Synthesis (digital) Leonardo Spectrum, Precision RTL (Mentor Graphics) Design Compiler (Synopsys), RTL Compiler (Cadence)
Design for Test and Automatic Test Pattern Generation DFT Advisor, Fastscan (Mentor Graphics)
Schematic Capture & Design Integration Design Architect-IC (Mentor Graphics) Design Framework II (DFII) - Composer (Cadence)
Physical Layout IC Station (Mentor Graphics) SOC Encounter, Virtuoso (Cadence)
Design Verification Calibre (Mentor Graphics) Diva, Assura (Cadence)
FPGA Design Flow Behavioral
Design
Gate-Level Schematic
Map, Place & Route
Verify Function
Verify Function
Verify Timing
FPGA Configuration File
Aldec/Mentor Graphics Front-End Tools
(Technology-Independent)
Xilinx/Altera/Other Back-End Tools
(Technology-Specific)
Synthesis
EDIF Netlist
Xilinx/Altera FPGA/CPLD Design Tools Simulate designs in Active-HDL or Modelsim
Behavioral models (VHDL,Verilog) Synthesized netlists (VHDL, Verilog)
Requires “primitives” library for the target technology
Synthesize netlist from behavioral model Leonardo (Levels 1,2,3) has libraries for most FPGAs (ASIC-only version currently installed) Xilinx ISE has its own synthesis tool
Vendor tools for back-end design Map, place, route, configure device, timing analysis, generate timing models Xilinx Integrated Software Environment (ISE) Altera Quartus II & Max+Plus2
Higher level tools for system design & management Mentor Graphics FPGA Advantage Xilinx Platform Studio : SoC design, IP management, HW/SW codesign
Mentor Graphics Analog/Mixed-Signal IC Design Flow
ASIC Design Flow
Mentor Graphics ASIC Design Kit (ADK) Technology files & standard cell libraries
AMI: ami12, ami05 (1.2, 0.5 μm) TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm)
IC flow & DFT tool support files: Simulation
VHDL/Verilog/Mixed-Signal models (Modelsim SE/ADVance MS) Analog (SPICE) models (Eldo/Accusim) Post-layout timing (Mach TA) Digital schematic (Quicksim II, Quicksim Pro) (except tsmc025,tsmc018)
Synthesis to standard cells (LeonardoSpectrum) Design for test & ATPG (DFT Advisor, Flextest/Fastscan) Schematic capture (Design Architect-IC) IC physical design (standard cell & custom)
Floorplan, place & route (IC Station) Design rule check, layout vs schematic, parameter extraction (Calibre)
We also have ADK’s for Cadence tools for several technologies