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7/30/2019 DIGITAL SYSTEM DESIGN LAB
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Sri Venkateswara College of Engineering & TechnologyR.V.S Nagar, Chittoor
M.Tech. I SEMESTER (DECS)
DIGITAL SYSTEM DESIGN LAB
List of Experiments
1. Simulation and Verification of Logic Gates.2. Design and Simulation of
(a) Half adder (b) Full adder (c) Serial Binary adder
(d) Carry Look Ahead adder (e) Ripple Carry adder3. Simulation and Verification of
(a) Decoder (b) Mux (c) Encoder
4 Modeling of Flip-Flops
(a) SR Flip-Flops (b) D Flip-Flops(c) JK Flip-Flops (d) T Flip-Flops
5. Design and Simulation of Counters(a) Ring Counters (b) Johnson Counters
(c) Up-Down Counters (d) Ripple Counters (Asynchronous)
6. Design of a N- bit Register
(a) Serial-in Serial-out (b) Serial in Parallel out
(c) Parallel in Serial out (d) Parallel in Parallel out7. Design of Sequence detector.
8. 4-Bit Multiplier (Array)
9. Design of ALU.10. RAM (Read and Write Operations)
11. Stack and Queue Implementation.
Lab-In-charge HOD, ECE
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LOGIC GATES
Ex. No : 01
AIM :-To write a VHDL Code for realizing Gates
AND, OR, NOT, NAND, NOR, XOR, XNORAnd verify the results.
AND GATE
PROGRAM:-
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;c : out STD_LOGIC);end and2;
architecture data_flow of and2 is
begin
c
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end component;begin
A1:andx port map(a,b,c);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity andx is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);end andx;
architecture andx of andx is
beginz
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OR GATE
PROGRAM:-
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;c : out STD_LOGIC);
end or2;architecture data_flow of or2 is
begin
c
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z : out STD_LOGIC);end orx;architecture orx of orx is
begin
z
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PROGRAM:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not1;
architecture data_flow of not1 isbegin
b
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NAND GATE
PROGRAM:-
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;c : out STD_LOGIC);
end nand2;architecture data_flow of nand2 is
begin
c
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z : out STD_LOGIC);end nandx;architecture nandx of nandx is
begin
z
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z : out STD_LOGIC);end norx;architecture norx of norx is
begin
z
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XOR GATE
PROGRAM:-
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;c : out STD_LOGIC);
end xor2;architecture data_flow of xor2 is
begin
c
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z : out STD_LOGIC);end xorx;architecture xorx of xorx is
begin
z
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XNOR GATE
PROGRAM:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xnor2 is
Port ( a : in STD_LOGIC;b : in STD_LOGIC;
c : out STD_LOGIC);end xnor2;
architecture data_flow of xnor2 is
begin
c
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y : in STD_LOGIC;z : out STD_LOGIC);
end xnorx;
architecture xnorx of xnorx is
begin
z
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MODELING OF ADDERSEx. No : 02
AIM :-
To write a VHDL Code for
Half adder Full adder ripple carry adder carry look ahead adder
serial adderAnd verify the results.
HALF ADDER
PROGRAM:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum: out STD_LOGIC;carry: out STD_LOGIC);
end ha;
architecture data_flow of ha is
begin
sum
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then carry
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FULL ADDER
PROGRAM:-
library IEEE;use IEEE.std_logic_1164.all;
entity adder is
port (a : in std_logic;b : in std_logic;
cin : in std_logic;sum : out std_logic;
cout : out std_logic);
end adder;
-- description of adder using concurrent signal assignmentsarchitecture rtl of adder isbegin
sum b,
out1 => xor1_out);xor2: xorg port map(
in1 => xor1_out,in2 => cin,
out1 => sum);
and1: andg port map(in1 => a,in2 => b,
out1 => and1_out);or1: org port map(
in1 => a,in2 => b,
out1 => or1_out);
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and2: andg port map(
in1 => cin,
in2 => or1_out,out1 => and2_out);
or2: org port map(
in1 => and1_out,in2 => and2_out,out1 => cout);
end structural;
------------------------------------------------------------------------
-- N-bit adder
-- The width of the adder is determined by generic N------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;
entity adderN is
generic(N : integer := 16);port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);cin : in std_logic;sum : out std_logic_vector(N downto 1);
cout : out std_logic);
end adderN;
-- structural implementation of the N-bit adderarchitecture structural of adderN is
component adderport (a : in std_logic;
b : in std_logic;cin : in std_logic;
sum : out std_logic;
cout : out std_logic);end component;
signal carry : std_logic_vector(0 to N);begin
carry(0) b(I),
cin => carry(I - 1),
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sum => sum(I),
cout => carry(I));
end generate;end structural;
-- behavioral implementation of the N-bit adderarchitecture behavioral of adderN is
begin
p1: process(a, b, cin)variable vsum : std_logic_vector(N downto 1);variable carry : std_logic;
begin
carry := cin;for i in 1 to N loop
vsum(i) := (a(i) xor b(i)) xor carry;carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
end loop;
sum
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RIPPLE CARRY ADDERPROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity rea isPort (a: in std_logic _vector (3 downto 0);
b: in std_logic _vector (3 downto 0);
ci:in std_logic;
s: out std_logic _vector (3 downto 0);co:in out std_logic);
end rea;
architecture structural of rea issignal c:std_ logic vector(3 downto 1);
component fa is
port (a,b,cin: in std_logic;
s : out std_logic;cout: in out std_logic);
end component;
beginf1: fa port map( a(0), b(0), ci, s(0),c(1));
f2: fa port map(a(1), b(1), c(1), s(1),c(2));
f3: fa port map(a(2), b(2), c(2), s(2),c(3));f4: fa port map(1)p(a(3), b(3), c(3), s(3),c(0));
end structural;
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CARRY LOOK AHEAD ADDER
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity carry_look_ahead isPort (a: in std_logic _vector(3 downto 0);
b : in std_logic _vector(3 downto 0);
co : out std_logic;
c : inout std_logic _vector(4 downto 0);s : out std_logic _vector(3 downto 0);end carry_look_ahead;
architecture structural of carry_look_ahead issignal p,g:std_ logic _vector(3 downto 0);signal r : std_ logic_ vector(6 downto 0);
signal i : integer;
begin
processor(a,b,c,p,g,r)begin
l1 : for i in 0 to 3 loop
p(i)
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SERIAL ADDER
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity serial_adder isPort (x: in std_logic _vector(3 downto 0);
y : in std_logic _vector(3 downto 0);
clk : in std_logic;
ce:in std_logic;cout : inout std_logics : out std_logic
end serial_adder;
architecture structural of serial_adder is
signal c:std_ logic_ vector(4 downto 0);
signal i : integer;begin
processor(clk,x,y)
beginif (ceevent and ce =1)then
c(0)
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EX.No:- 03
3:8 DECODER
AIM: To write and simulate a vhdl program for a 3 to 8 decoder and verify theresults
PROGRAM:-
library ieee;
use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dc_counter isport(clk:in std_logic;
q:inout std_logic_vector(3 downto 0):="0000");
end dc_counter;
architecture behave of dc_counter is
begin
process(clk)begin
if(clk'event and clk='1')thenif(q="1001")then
q
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8x1 MULTIPLEXER
AIM:- To write and simulate aModelsim( VHDL) program for 8x1 Multiplexer.
PROGRAM:-
library ieee;use ieee.std_logic_1164.all;
entity mx is
port(i:in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto 0);y:out std_logic);
end mx;
architecture archi of mx isbegin
process(i,s)
begin
if(s="000") then y
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MODELING OF FLIP - FLOPSEx. No : 04
AIM : -
To write a VHDL Code for
SR Flip-Flop D Flip-Flop JK Flip-Flop T Flip-Flop
And verify the results.
SR- FLIP - FLOP
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity srff isPort (s : in std_logic;
r : in std_logic;
clk : in std_logic;q : in out std_logic;
qbar : in out std_logic);
end srff;
architecture Behavioral of srff is
beginProcess (s,clk,r)begin
if (clkevent and clk =1)thenif(s=0and r=0)then
q
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q
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D - FLIP - FLOP
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;Use IEEE.STD_LOGIC_UNSIGNED.All;
entity dff is
Port (d : in std_logic;
clk : in std_logic;q : in out std_logic;qbar : in out std_logic);
end dff;architecture Behavioral of dff isbegin
Process (d,clk)
Begin
if (clkevent and clk =1)thenif(d=0)then
q
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architecture structural of d_ff is
signal s1,s2,s3:std_ logic;
component nand2 is
port (a,b: in std_logic;
c : out std_logic);
end component;
component not1 is
port (a: in std_logic;
c : out std_logic);
end component;
begin
x1: not1 port map(d,s3);n1: nand2 port map(d,clk,s1);
n2: nand2 port map(s3,clk,s2);
n3: nand2 port map(s1,qbar,q);n4: nand2 port map(s2,q,qbar);
end structural;
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JK- FLIP - FLOP
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity jkff isPort (j : in std_logic;
k : in std_logic;clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end jkff;architecture Behavioral of jkff is
begin
Process (j,clk,k)
begin
if (clkevent and clk =1)then
if(j=0and k=0)then
q
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architecture data_flow of jk_ff issignal s1,s2:std_ logic;begin
s1
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T - FLIP - FLOP
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity tff is
Port (t : in std_logic;clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end tff;architecture Behavioral of tff is
begin
Process (t,clk,)
begin
if (clkevent and clk =1)then
if(t=0)then
q
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s2
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DESIGN AND SIMULATION OF COUNTERS
Ex. No : 05
AIM :-
To write a VHDL Code for
Ring Counters Johnson Counters Up-Down Counters Ripple Counters (Asynchronous)
And verify the results.
BCD COUNTER
PROGRAM:
library IEEE;
Use IEEE.STD_LOGIC_1164.All;Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity mod_n_coun is
Port (ce: in std_logic ;
clk: in std_logic;q:in out std_logic _vector (3 downto 0));end mod_n_coun ;architecture Behavioral of mod_n_coun is
begin
Process (ce,clk);
begin
if (ceevent and ce =1)thenq
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BINARY UP DOWN COUNTER
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;entity bin_up_down is
Port (up: in std_logic ;down: in std_logic;
ce: in std_logic ;clk: in std_logic;
q:in out std_logic _vector (3 downto 0));
end bin_up_down;architecture Behavioral of bin_up_down is
begin
Process (up, down, ce, clk);
begin
if (ceevent and ce =1)then
q
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ASYNCHRONOUS COUNTER
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;entity asy_count is
Port (ce: in std_logic;
clk: in std_logic;
n:in std_logic _vector (3 downto 0);q:in out std_logic _vector (3 downto 0));
end asy_count;
architecture Behavioral of asy_count isbeginProcess (ce, clk,q);
begin
if (ceevent and ce =1)then
q
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MODELING OF SHIFT REGISTERS COUNTERS
Ex. No :06
AIM :-To write VHDL Program for realizing Shift Registers
Serial-in Serial-out Serial in Parallel out Parallel in Serial out Parallel in Parallel out
And verify the results.
SHIFT REGISTERS
Serial in serial out (SISO)
PROGRAM:
library IEEE;Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
Entity siso is
Port (si: in std_logic;clk: in std_logic;
so:in out std_logic);
end siso;
architecture structural of siso iscomponent d_ff is
Port( d,clk: in std_logic;q,qbar :in out std_logic);
end component;
Signal a1, a2, a3, d1, d2, d3, d4:std_logic;
begin
11:d_ff port map (si, clk, a1, d1);
12:d_ff port map (a1, clk, a2, d2);13:d_ff port map (a2, clk, a3, d3);
14:d_ff port map (a3, clk, so, d4);
end structural;
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SIPO
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
Entity sipo isPort (si: in std_logic;
clk: in std_logic;
po:in out std_logic_vector(3 downto 0));
end sipo;architecture structural of sipo issignal d:std _logic_ vector(4 downto 0);
component d_ffPort (d,clk: in std_logic;
q,qbar :in out std_logic);
end component;
begin
a1:d_ff port map (si, clk, po(3),d(3));a2:d_ff port map( po(3), clk, po(2),d(2));
a3:d_ff port map (po(2), clk, po(1),d(1));
a4:d_ff port map (po(1), clk, po(0),d(0));end structural;
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PISO
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;entity piso isPort (pi: in std_logic _vector (3 downto 0);
c: in std_logic;
clk: in std_logic;
so:in out std_logic);
end piso;architecture structural of piso is
signal d:std_ logic vector(3 downto 0);
signal q:std _logic vector(3 downto 1);
signal a:std_ logic vector(3 downto 1);
signal r:std _logic;
component d_ff isPort (d,clk: in std_logic;
q,qbar :in out std_logic);
end component;
component aoi isPort (a,b,c,d: in std_logic;
c: out std_logic);end component;
begin
a1:aio port map (q (3),r,c,pi(2)a(3));
a2:aio port map( q (2),r,c,pi(1)a(2));
a3:aio port map (q (1),r,c,pi(0)a(1));
11:d_ff port map( pi(3), clk, q(3),d(3));12:d_ff port map(a(3), clk, q(2),d(2));
13:d_ff port map(a(2), clk, q(1),d(1));
14:d_ff port map(a(1), clk, so,d(0));
end structural;
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PIPO
PROGRAM:-
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;entity pipo isPort (pi: in std_logic _vector (3 downto 0);
clk: in std_logic;
po:in out std_logic _vector (3 downto 0));
end pipo;
architecture structural of pipo issignal d:std_ logic vector(4 downto 0);
component d_ff is
Port (d,clk: in std_logic;
q,qbar :in out std_logic);
end component;
begin11:d_ff port map( pi(3), clk, po(3),d(3));
12:d_ff port map( pi(2), clk, po(2),d(2));
13:d_ff port map( pi(1), clk, po(1),d(1));
14:d_ff port map( pi(0), clk, po(0),d(0));end structural;
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Serial in serial out (SISO)
Serial Input
Clk
Serial Out
Serial in Parallel out (SIPO)
Serial Input
Clk
Parallel Out
Q(n-2) Q(n-3) Q(0)Q(n-1)
Q(n-2) Q(n-3) Q(0)Q(n-1)
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Parallel in out Serial (PISO)
Parallel In
Clk
Serial Out
Parallel in Parallel out(PIPO)
Parallel In
Clk
Load
Parallel Out
SISO PIPO
SIN CLK SOUT
1 U
0 1
0 0
1 0
1 11 1
0 1
INPUT OUTPUT
SIN CLKQ0 Q1 Q2 Q3
1 U U U U
0 1 U U U
0 0 1 U U
1 0 0 1 U1 1 0 0 1
1 1 1 0 0
Q(n-2) Q(n-3) Q(0)Q(n-1)
Q(n-2) Q(n-3) Q(0)Q(n-1)
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PISO
PIPO
MOD-N BCD Counter
Q0
Q1
ClkQ2
Q3
INPUT OUTPUT
LOAD CLK IN0 IN1 IN1 IN1 SOUT
1 0 0 1 U
X 1 1 0 0 1
X 1 1 1 0 0
X 1 1 1 1 0
X 1 1 1 1 1
INPUT OUTPUT
LOAD CLK10 11 I2 I3 Q0 Q1 Q2 Q3
X 1 0 0 1 U U U U
X 1 0 0 1 1 0 0 1
X 1 1 0 1 1 0 0 1
0 1 0 0 1 1 0 1
X 0 1 0 0 0 1 0 0
INPUT OUTPUT
SIN CLKQ0 Q1 Q2 Q3
1 U U U U
0 1 U U U
0 0 1 U U
1 0 0 1 U
1 1 0 0 1
1 1 1 0 0
MOD-N
BCD
Counter
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BINARY UP DOWN COUNTER
Q0
UP
DN Q1
Clk Q2
Q3
ASYNCHRONOUS COUNTER
Q0
Clk
Q1Q0
Q2
Q1
Q3
Q2
CLR
BINARY
UPDOWN
COUNTER
Asynchronous
Counter
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MODELLING OF MULTIPLIERS
Ex. No :08
AIM :-To write VHDL Program for realizing multipliers like Array
Multiplier and verify the results.
PROGRAM:-
library IEEE;Use IEEE.STD_LOGIC_1164.All;Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;entity unsign_mul isPort (x: in std_logic _vector(3 downto 0);
y : in std_logic _vector(3 downto 0);
l : in std_logic;
p : inout std_logic _vector(7 downto 0);end unsign_mul;
architecture Behavioral of unsign_mul is
signal m : std_ logic_ vector(7 downto 0);signal i : integer;
begin
processor(x,y,i)begin
if (levent and l =1)then
q
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RAM
Ex. No :09
AIM :-
To write VHDL Program for RAM and verify the results.
PROGRAM:-
library ieee;
use ieee.std_logic_1164.all;entity ram is
port(din:in std_logic_vector(7 downto 0);rd,wr,clk:in std_logic;
locn:in integer range 0 to 7;
dout:out std_logic_vector(7 downto 0));
end ram;architecture behav of ram is
type mem is array(integer range 0 to 7) of std_logic_vector(7 downto 0);
signal sram:mem;
begin
process(clk,rd,wr)
begin
if((rd and wr)/='1')thenif(clk'event and clk='1')then
if(rd='1')then
dout
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STACK AND QUEUE IMPLEMENTATIONS
Ex. No :10
AIM :-To write VHDL Program for Stack and Queue Implementations
and verify the results.
PROGRAM:-
library ieee;
use ieee.std_logic_1164.all;entity stack is
port ( rd,wr,clk,clr:in std_logic;
data: inout std_logic_vector(7 downto 0);ful:out std_logic);
end stack;architecture que of stack is
type store is array(natural range )of std_logic_vector(7 downto 0);signal address: integer range 0 to 15;signal memory:store(0 to 15);begin
process (data ,rd ,wr,clr,clk)
beginif clr='1' then
memory(others=>'0'));
ful
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