Digital IP for Analog Interfaces - Stellamar · •Infinite power management •Infinite power sequencing •Redundant supplies •Powerthrottling •Simplified board layout Digital

TM

Digital IP for Analog Interfaces

10/12/2015 1Digital solutions for an analog world

Agenda

• Company introduction

• Digital ADC architecture

• Digital DAC architecture

• Digital DC-DC converter controller• Digital DC-DC converter controller

• Digital Clock Multiplier

Digital solutions for an analog world 210/12/2015

StellamarTM : Digital cell-based technology for implementing analog

functions in standard ASICs and FPGAs.

Stellamar offers fully digital synthesizable devices which use only digital

blocks available in FPGA and ASIC libraries along with a few external

passive components.

Our Business

Main IP cores:

Company Introduction


Main IP cores:

• Digital ADC

• Digital ADC with built-in digital amplifier

• Sigma-Delta DAC

• DC-DC Converter Controller

• Clock Multiplier*

Custom mixed signal design services

*Under development

Partners


In the news

5Digital solutions for an analog world 10/12/2015


Implementing Analog Functions in Rugged and Rad-Hard FPGAs


June 2012 issue

Products and Services

Semiconductor IP SolutionsAll Digital ADC Architecture: up to 14-bit resolution, up to 100 kHz bandwidth*

All Digital DAC Architecture: up to 16-bit resolution, up to 6 MHz bandwidth*

All Digital DC-DC Converter Controller: Interface with buck, boost, buck-boost and cuk to

deliver point to load DC voltage conversion

All Digital Clock Multiplier: Analog PLL replacement clocking solution with no lock time and

GHz range performance**

*Bandwidth depends on resolution requirements

**Under development


**Under development

Semiconductor Service SolutionsMixed Signal Design and Consulting

Custom ASIC Design

Custom FPGA Design

Layout and Verification

System Board Design

Signal Processing Consulting

Digital ADC IP Architecture:

• Xilinx Virtex 5 QV Space Grade

FPGA

• Actel ProASIC

• Altera Cyclone

• Lattice

Sample Work ProductSilicon Proven FPGA

Digital ADC & DAC IP Architecture:

• Digital DAC in TSMC .18

• Digital ADC in RAD Hard Honeywell

HX5000

Silicon Proven ASIC

Missions


• SEAKR Engineering: On Board

Processor Program

• Finnish Meteorological Institute: Lunar

Ions and Neutrals Analyzer

Missions

Digital DAC IP Architecture:

• Xilinx

• Actel ProASIC

• Actel Igloo

• Altera Cyclone

• Lattice

Semiconductor IP SolutionsAll digital ADC Architecture: up to 14 bit resolution, up to 100kHz bandwidth*


A 2 D without the A: Key Features • Embeddable in digital fabric

• Technology independent

• Very Low power < 6 mW

• Very small area (20k eq. NAND gates)

• Very low supply voltage < 2.5 V

• Suitable for Radiation Hard environments

• ASIC or FPGA compatible

• Extremely low offset drift

• Digital layout

• Digital testing

• No missing codes

• Oversampling

• Customizable


• Suitable for Radiation Hard environments • Customizable

Overview

The Digital ADC is a digital core which provides analog functionality with all the benefits of a digital design process: shorter design

cycles, lower risk, established design and layout tools, digital test methodology and portability across process technologies.

The design is implemented with a small number of digital gates and only an LVDS or LVPECL input cell, a digital output cell and a few

external passive components.

The Digital ADC provides up to 14 bits and up to 100kHz of bandwidth (depending on requirements) making it an ideal fit for both

low frequency sensors, high quality voice and motor control.

The benefits of the digital implementation include low voltage and low power process technologies where the Digital ADC excels in

portable applications.

14-BIT SAR ADC

_+ SAR

Logic

LPF

14-bit

DAC

Digital

OutputAnalog

Input

Typical SAR ADC

Typical Σ∆ADC

Traditional Analog ADC DesignsTraditional ADCs require complex

analog circuitry. Their design,

implementation and fabrication

are plagued by all the problems

encountered in the design and

integration of analog devices.


Analog

Input

Second Order Σ∆Modulator

LPF

_Decimator

Digital

Output

Analog Circuit Digital Circuit

1-bit

DAC

+ +

_

Typical Σ∆ADC

Analog

InputLPF1

Digital

Logic

Digital

output

ASIC/FPGA

_

+

LVDS

Input

Digital

Digital ADC


LPF2

Digital

Output


Digital ADCs need only digital cells available in ASIC & FPGA libraries

Digital ADC with Built-in Amplifier

Positive

Analog

Input

Digital

Logic

Digital

output

ASIC/FPGA

_

+

LVDS

Input

LPF


Logic_

Digital

Output

Negative

Analog

InputDigital

Output


Digital ADCs with built-in amplifier need only digital cells available in ASIC & FPGA libraries

Example of Digital ADC Performance

Characteristics

Resolution (bits) Bandwidth (kHz) Clock (MHz)

14 10 25

12 50 25


11 5 10-25

11 15 10-25

10 100 25

2-3* 50,000 100

*Under development

Example of Digital ADC Spec

SAMPLE SPECIFICATIONS

Parameter Conditions Min Typ Max Unit

General Characteristics

Technology Customer Defined

Core Area Technology Dependent mm2

Gate Equivalent1 20K Gates

Clock

Clock Frequency 10 20 50 MHz

Clock Jitter Requirement Cycle-to-cycle 150psRMS

Input Characteristics


Input Characteristics

Analog Input Range (Centered @ VddIO/2)

Single Ended 0.6VddIO Vpp

Differential 0.6VddIO Vpp

Input Impedance2 7 MΩ

Input Signal Bandwidth 0.001 100 kHz

1 Dependent on customer requirements

2 Technology dependent

Example of Digital ADC SpecParameter Conditions Min Typ Max Unit

Dynamic Performance

Dynamic Range (DR)3 72 dB

Signal-to-Noise + Distortion Ration (SNDR) 68 dB

Static Performance

Resolution1 12 14 Bits

Gain 0 dB

Gain Error2 ±0.5 LSB

Midscale Offset Error2 ±3.4 LSB

Midscale Drift2 0 LSB/°C

Delay


Delay

Startup time (latency)4 150 µs

Power Supply

I/O Voltage (Vio) 2.5 V

Core Voltage 1.2 V

I/O Current2 2.0 mA

Core Current1 0.75 mA

Operating Temperature Range

Temperature Range2 -40 125 °C


2 Technology dependent

3 DR is measured with an input at -60dB and it is equivalent to SNDR +60 dB

4 Dependent on customer filter requirements

Customizable Digital ADC Features

• Resolution: 4-14 bits

• Bandwidth: 0.5 Hz - 100 kHz (depending on resolution)

• Custom clock rate

• Number of channels


• Number of channels

• Integrated digital filter: can be customized for specific needs

• Single-ended, differential, processor interface, auto-calibration

• Gain: up to 30 dB

Semiconductor IP SolutionsAll digital Sigma-Delta DAC: up to 16-bit resolution, up to 6 MHz bandwidth*


Key Features • Embeddable in digital fabric


• Very small (~ 30k eq. NAND gates)

• Very low supply voltage < 2.5 V


• Digital layout and testing

• Custom digital filtering


Overview

The Sigma-Delta DAC is a digital converter core suitable for applications such high quality multimedia, audio, telecommunications,

and composite video.

The design is fully digital and requires only a small number of passive external components for the reconstruction filter.

The DAC provides up to 16 bits and up to 6 MHz bandwidth (depending on requirements).

Sigma-Delta DAC

Digital Digital

output

ASIC/FPGA

Analog

output


DigitalInput

LPFoutputDigital

Logic

output


Example of Stereo Sigma-Delta DAC


Stereo DAC SpecSAMPLE SPECIFICATIONS

Pin Name Description I/O

I/O Signals

reset Digital input active high to assert reset Input

in_r[19:0] Digital right input (two's complement) Input

in_l[19:0] Digital left input (two's complement) Input

cdata[31:0]Control data to configure the DAC (sampling rate, left and right volume, muting options, roll-off equalizer…)

Input

out_r Right output Output

out_l Left output Output


out_l Left output Output

Clocks

clkin Input clock (512 X audio sample rate) Input

clkoutOutput clock with the frequency of the audio sample rate used to sample the digital inputs

Output

Power Supply

VddCORE Digital supply voltage Input

VSSCORE digital logic ground Input

VddIO I/O supply voltage Input

VssIO I/O ground Input

Stereo DAC SpecSAMPLE SPECIFICATIONS

Parameter Conditions Min Typ Max Unit

General Characteristics

Technology Customer Defined

Core Area Technology Dependent mm2

Gate Equivalent1 30K Gates

Clock

Clock Frequency 24.576 MHz

Clock Jitter Requirement Cycle-to-cycle 150 ps RMS

Dynamic Performance

Dynamic Range (DR)2 100 dB

Signal-to-Noise + Distoriton Ratio (SNDR) 70 dB

Static Performance

Resolution 16 Bits


Resolution 16 Bits

Digital Filter

Passband Ripple ±0.02 dB

Stop band rejection 68 dB

Passband3 0 0.44Xfs kHz

Group Delay3 25/fs ms

Power Supply

I/O Voltage (VddIO) 2.5/3.3 V

Core Voltage 1.2 V

I/O Current2 2 mA

Core Current1 0.75 mA

Opertating Temperature Range

Temperature range1 -40 125 °C


2 DR is measured with an input at -60 dB and it is equivalent to SNDR + 60 dB

3 fs is the audio sample rate (e.g. 48 kHz)

Semiconductor IP SolutionsDigital Controller for Switch-Mode DC-DC Converters

Key Integration Advantages• Embeddable in digital fabric



• Customizable

• Smaller footprint


Key System Advantages • Infinite power management

• Infinite power sequencing

• Redundant supplies

• Power throttling

• Simplified board layout



• Synthesizable

Overview

The Controller for Switch-Mode DC-DC Converters is a completely digital IP core that interfaces with buck, boost, buck-boost and cuk

converters to provide point to load DC voltage conversion.

Digital Controller for Buck Converter


Digital Controllers need only digital cells available in ASIC & FPGA libraries

Digital Controller for Boost Converter


Digital Controllers need only digital cells available in ASIC & FPGA libraries

Semiconductor IP SolutionsDigital Clock Multiplier*

*Under development

Key Integration Advantages• Embeddable in digital fabric


• Technology independence

• Customizable

• Smaller footprint


Key System Advantages • No lock time

• Low power

• Reduce number of PLLs required

• Simplified board layout

• Ability to generate any clock



• Synthesizable

Overview

The Digital Clock Multiplier is a completely digital IP core that provides performance equivalent to existing analog PLL. We anticipate

performance into the GHz ranges.

Contact InformationStellamar LLC

Web: www.stellamar.com

Blog: stellamar.quora.com

Email: [email protected]


Documents

Digital IP for Analog Interfaces - Stellamar · •Infinite power management •Infinite power sequencing •Redundant supplies •Powerthrottling •Simplified board layout Digital