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Digital Integrated Circuits
(83-313)
Semester B, 2015-16
Lecturer: Adam Teman
TAs: Itamar Levi, Robert Giterman 1
Lecture 5:
Interconnect
21
3 4 5
What will we learn today?
2
A First Glance at
InterconnectCapacitance Resistance Interconnect
ModelingWire
Scaling
The Wire
3
transmitters receivers
schematics physical
Wire Models
4
All-inclusive modelCapacitance-only
Impact of Interconnect Parasitics
5
Interconnect parasitics affect all the metrics we care about
Reliability
Performance
Power Consumption
Cost
Classes of parasitics
Capacitive
Resistive
Inductive
Modern Interconnect
6
12
3 4 5
What will we learn today?
7
CapacitanceA First
Glance at
InterconnectResistance Interconnect
ModelingWire
Scaling
Capacitance of Wire Interconnect
8
VDDVDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CL
SimplifiedModel
Capacitance: The Parallel Plate Model
9
How can we reduce this capacitance?
Dielectric
Substrate
L
W
H
tdi
Electrical-field lines
Current flow
dipp
di
c WLt
Typical numbers:• Wire cap ~0.2 fF/um• Gate cap ~2 fF/um• Diffusion cap ~2 fF/um
Permittivity
10
Fringing Capacitance
/ 2w W H
11
W - H/2H
+
(a)
(b)
W - H/2H
+
(a)
(b)
F mm
2 2
log
di dipp fringe
di di
W HC c c
t t H
Fringing versus Parallel Plate
12
(from [Bakoglu89])
0.05fringeC fFedge m
fringe
PP
C L
C W L
A simple model for deriving wire cap
13
Wiring capacitances in 0.25μm
_ 2wire parallel plate fringeC C W L C L
Bottom Plate
Top
Pla
te
aF/µm2
aF/µm
Interwire Capacitance
14
fringing parallel
Impact of Interwire Capacitance
15
(from [Bakoglu89])
Coupling Capacitance and Delay
16
CC1
CC2CL
tot LC C
Coupling Capacitance and Delay
17
CC1
CC2CL
0
1
0
1
1 2tot L C CC C C C
Coupling Capacitance and Delay
18
CC1
CC2CL
1 22tot L C CC C C C
Example – Coupling Cap
19
A pair of wires, each with a capacitance to ground of 5pF, have a 1pF coupling capacitance between them.
A square pulse of 1.8V (relative to ground) is connected to one of the wires.
How high will the noise pulse be on the other wire?
Example – Coupling Cap
20
Draw an Equivalent Circuit:
2
2
1.8 10.3
1 5
in coupled
C
coupled
V C pV V
C C p p
Coupling Waveforms
21
Simulated coupling for Cadj=Cvictim
Aggressor
Victim (undriven): 50%
Victim (half size driver): 16%
Victim (equal size driver): 8%
Victim (double size driver): 4%
t (ps)
0 200 400 600 800 1000 1200 1400 1800 2000
0
0.3
0.6
0.9
1.2
1.5
1.8
Shielding
22
Feedthrough Cap
23
Measuring Capacitance
24
13
2 4 5
What will we learn today?
25
ResistanceA First
Glance at
Interconnect
Capacitance Interconnect
ModelingWire
Scaling
Wire Resistance
26
W
L
H
R =
H W
L
Sheet ResistanceRo
R1 R2
100m
Rsquare
Interconnect Resistance
27
,sq sq
L L LR R R
A H W W H
More LayersMetal Bulk resistivity
(*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
Sheet Resistance
28
Typical sheet resistances for 180 nm process
Layer Sheet Resistance
(/)
N-Well/P-Well 1000-1500
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02
Polycide Gate MOSFET
29
n+n+
SiO2
PolySilicon
Silicide
p
Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
Conductivity: 8-10 times better than Poly
Contact Resistance
30
Contact/Vias add extra resistanceSimilar to changing between roads on the way to a destination…
Contact resistance is generally 2-20 ohms
Make contacts biggerBUT… current “crowds” around the perimeter of a contact.
There are also problems in deposition…
Contacts/Vias have a maximum practical size.
Dealing with Resistance
31
Selective Technology ScalingDon’t scale the H
Use Better InterconnectMaterials
reduce average wire-length
e.g. copper, silicides
More Interconnect Layersreduce average wire-length
Minimize Contact ResistanceUse single layer routing
When changing layers, use lots of contacts.
90nm Process
Multiple Contacts to Diffusion?
32
14
2 3 5
What will we learn today?
33
Interconnect
Modeling
A First
Glance at
Interconnect
Capacitance Resistance Wire
Scaling
The Ideal Model
34
In schematics, a wire has no parasitics:
The wire is a single equipotential region.
No effect on circuit behavior.
Effective in first stages of design and for very short wires.
The Lumped Model
35
Vout
Driver
cwire
Vin
Clumped
RdriverVout
Ron=1kΩ-10kΩ
Rwire=1Ω
The Distributed RC-line
36
But actually, our wire is a distributed entity.
We can find its behavior by breaking it up into small RC segments.
The Distributed RC-line
3
7
2
2
rcL 0.38pdt RC
Quadratic dependence on wire length
The lumped model is
pessimistic
1 1i i i iC
V V V VI
rdx rdx
idV
cdxdt
2
2
i idV Vrc
dt x
Step-response of RC wire
38
Step-response of RC wire as a function of time and space
Elmore Delay Approximation
39
Solving the diffusion equation for a given network is complex.
Elmore proposed a reasonably accurate method to achieve an
approximation of the dominate pole.
1 1 1 2 2 1 2 3 3elmore R C R R C R R R C
Elmore Delay Approximation
40
For a complex network use the following method:
Find all the resistors on the path from in to out.
For every capacitor:
Find all the resistors on the path from the input to the capacitor.
Multiply the capacitance by the resistors that are also on the path to out.
The dominant pole is approximately the sum of all these time
constants.
Simple Elmore Delay Example
41
1 1 1 2 2 1 2elmore R C R R C R C
General Elmore Delay Example
42
1 1 1 2 1 3 3 1 3 4 1 3elmore i iR C R C R R C R R C R R R C
Generalized Ladder Chain
43
Lets apply the Elmore approximation for our original distributed wire.
Divide the wire into N equal segments of dx=L/N length with capacitance cdx and resistance rdx.
2 ..N
L L L Lc r r Nr
N N N N
2
2 ..L
rc rc NrcN
2
2
1
2
N NrcL
N
2
lim2 2
DN
rcL RC
RC-Models
44
T-ModelPie Model
Pie-2 Model
Pie-3 Model
T-2 Model
T-3 Model
Wire Delay Example
45
Inverter driving a wire and a load cap.
2 2W W
driver d inv ext inv w
C CC R C R R
A different look…
46
Again we’ll look at our driver with a distributed wire.
For the driver resistance, we can lump the as a capacitor.
For the wire resistance, we will use
the distributed time constant.
For the load capacitance, we can
lump the wire and driver resistance.
0.2
0.1
w
fFC
m
R
0.69 0.38 0.69D inv d W W W inv w LR C C R C R R C
Repeaters
47
Buffer Trees
48
15
2 3 4
What will we learn today?
49
Wire
Scaling
A First
Glance at
Interconnect
Capacitance Resistance Interconnect
Modeling
Wire Scaling
50
We could try to scale interconnect at the same rate (S) as device
dimensions.
This makes sense for local interconnect that connects smaller devices/gates.
But global interconnections, such as clock signals, buses, etc. won’t scale in
length.
Length of global interconnect is proportional to die size or system
complexity.
Die Size has increased by 6% per year (X2 @10 years)
Devices have scaled, but complexity has grown!
Nature of Interconnect
51
Local Wire Scaling
52
Looking at local interconnect:
W, H, t, L all scale at 1/S
C=LW/t1/S
R=L/WH S
RC=1
Reminder – Full Scaling of transistors:
» Ron=VDD/Ion α 1
» tpd=RonCg α 1/S
So the delay of local interconnect still increases relative to transistors!
So the delay of local interconnect
stays constant.
Local Wire Scaling – Full Scaling
53
What about fringe cap?
Local Wire Scaling - Constant Thickness
54
Thickness wasn’t scaled!
Local Wire Scaling – Interwire Capacitance
55
Without scaling height, coupling gets much worse.
Global Wire Scaling
56
Looking at global interconnect:
W, H, t scale at 1/S
L doesn’t scale!
C=LW/t1
R=L/WH S2
RC=S2 !!!
And if chip size grows, L actually increases!
Long wire delay increases
quadratically!!!
Global Wire Scaling – Constant Thickness
57
Leave thickness constant for global wires
Wire Scaling
58
So whereas device speed increases with scaling:
Local interconnect speed stays constant.
Global interconnect delays increase quadratically.
Therefore:
Interconnect delay is often the limiting factor for speed.
What can we do?
Keep the wire thickness (H) fixed.
This would provide 1/S for local wire delays
and S for constant length global wires.
But fringing capacitance increases, so this is optimistic.
Wire Scaling
59
What is done today?
Low resistance metals.
Low-K insulation.
Low metals (M1, M2) are used for local interconnect,
so they are thin and dense.
Higher metals are used for global routing, so they are
thicker, wider and spaced farther apart.
Modern Interconnect
60
Intel 90 nm Stack
[Thompson02]
Intel 45 nm Stack
[Moon08]
Further Reading
61
J. Rabaey, “Digital Integrated Circuits” 2003, Chapter 4
E. Alon, Berkeley EE-141, Lectures 15,16 (Fall 2009)http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/
B. Nicolic, Berkeley EE-241, Lecture 3 (Spring 2011) http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s11