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Digital IC Design and ArchitectureDigital IC Design and Architecture
Combinational Combinational Logic Logic d Ci itd Ci itand Circuitsand Circuits
Static CMOS Circuit
At every point in time (except during the switching y p ( p g gtransients) each gate output is connected to eitherVDD or Vss via a low-resistive path.
Th t t f th t t ll ti th lThe outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on therelies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
2
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signalg y g g
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
A
X YB Y = X if A OR B
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NMOS Transistors pass a “strong” 0 but a “weak” 1
PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
A
X YB Y = X if A OR B = ABY
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PMOS Transistors pass a “strong” 1 but a “weak” 0
Threshold DropsThreshold DropsVDD
PUNVDD
VDD
S
D S
D
0 → VDD
CL
0 → VDD ‐ VTn
CL
D SVGS
VDD → 0PDN
C
VDD → |VTp|
CSDVGS
CLVDDCL
S D
6
Digital IC Design and ArchitectureDigital IC Design and Architecture
Combinational Logic: Combinational Logic: CMOSCMOSCMOS CMOS
ImplementationImplementationImplementationImplementation
Digital IC Design and ArchitectureDigital IC Design and Architecture
Combinational Combinational Logic Logic ith R i ti L dith R i ti L dwith Resistive Loadwith Resistive Load