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DIGITAL HARDWARE NEURAL NETWORK SIMULATOR FOR SIGNAL PROCESSING BASED ON SPIKE SYNCHRONIZATION
1. THE NEURON MODEL The Oscillatory Dynamic Link Matcher (ODLM)
Oscillatory leaky integrate and fire (LIF) neurons are used as an approximation of relaxation oscillators.
The membrane potential of an uncoupled neuron follows an inverse exponential function and spikes are emitted periodically.
Spikes are instantaneously delivered to post-synaptic neurons. • Time is stopped during the processing of spikes.
The simulator alternates between two states: • Spike propagation • Computation of the time evolution of the membrane model
2. THE HARDWARE ARCHITECTURE
Design choices
Simulation
Parallel processing of the neurons • Direct mapping of the neurons to PEs
Serial processing of the synapses Serial arithmetic • Compact PEs
Tagless memory • Each stored element has a dedicated place in memory and is accessed in a predetermined order
Width of the variables • Membrane potentials (P): 16 bits • Synaptic weights (W): 11 bits
Spike propagation
A weight is sent from memory to the synapse units. If the neuron’s spiking bit is 1, the membrane unit sends the potential to the synapse unit which adds the weight.
The spiking bits are transferred from each column to its right neighbor.
Time evolution
Membrane model units compute the time evolution of the potential of all neurons in parallel.
When one or more spikes are detected the time is stopped.
The membrane units transfer the state of the neurons (firing or not) to the synapse units.
3. COMPUTING WITH SPIKES Example of an image segmentation task
Random initialization of neurons’ phase
Synchronized neurons are part of the same segment
Same principle can be applied to image matching and sound source separation
The signal processing task defines the size and topology of the network
Resource Used Available % used Dependence FFs 11594 32640 35% P, N LUTs 23821 32640 72% P, N Slices 7509 8160 92% BRAMs 104 132 78% W, N2
4. RESULTS
Function FFs LUTs BRAMs Weights memory 545 1076 104 Synapse units 1058 2116 0 Membrane units 9464 20218 0 FSM 99 227 0
SP 1
SP 2
Table 1. Impacts of the neuron model on the hardware simulator
Figure 1. Time evolution of an uncoupled oscillator LIF neuron
TE 1
TE 2
TE 3
• 529 neurons and 280000 synapses were simulated on a XC5VSX50T FPGA.
• The simulator can be readily used for a variety of signal processing tasks.
• The simulator uses a bit-slice architecture and mostly short and local connections, facilitating placement, routing and scalability.
• The performance of the simulator increases with network synchrony.
• Time multiplexing could be used to process several neurons with the same processing element, increasing network capacity.
5. CONCLUSION
6. ACKNOWLEDGEMENTS
7. REFERENCES
This work has been funded by the Natural Sciences and Engineering Research Council of Canada (NSERC). Images have been provided by MBDA
[1] Milner, P.: Psychological Review 81 (1974) [2] v. d. Malsburg, C.: Internal Report 81-2, Max-Planck Institute for Biophysical Chemistry (1981) [3] Pichevar, R.: Neurocomputing 69 (2006) [4] Pichevar, R.: Neurocomputing 71 (December 2007)
The ODLM is a spiking neural network in which computations are based on the synchronized activity of the neurons, for binding [1, 2].
It has been demonstrated to be able to accomplish image segmentation and matching and monophonic sound sources separation [3, 4].
The neuron model
Figure 2. Overview of the hardware system
Figure 6. Raster plots of the spikes of the neurons during an image segmentation task. Left. The phase of the neurons is initialized randomly. Right. After a while, the neurons corresponding to the same segment have synchronized.
Figure 3. Propagating spikes (with a network of 3 neurons) Figure 4. Computing the time evolution
Figure 5. Example of the segmentation of an image using pixel values
Feature Impact Oscillatory neurons All neurons are constantly active
Dirac delta function synapses and no propagation delay
Synapse unit is a simple adder Spikes have an instantaneous effect
LIF neuron model, no plasticity, no refractory period, no per-neuron parameter
Simple and compact processing elements (PEs)
Table 2. Resources used for the entire system Table 3. Resource used per functional block
Table 4. Theoretical performance Performance
Figure 7. Result of a simple positive matching task on the FPGA (similarity score = 0,992)
Clock cycles / period Speed at 100 MHz Best case 8,5k (P×N) 6,25M spikes/s Worst case 4,5M (P×N2) 11,8k spikes/s
Table 5. Real performance of positive matching
Pixel value differences define weights, in a 8-neighbors connected network
Figure 8. Result of a simple negative matching task on the FPGA (similarity score = 0,026)
Figure 9. Original images used for the
positive matching task
Measure Value Images size 89 × 28 pixels Simulation time 550 ms Nbr of spikes 45k spikes Nbr of periods 85 periods Processing speed 81,75k spikes/s
SP 1 SP 1 SP 2 ...