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PARITY GENERATOR & CHECKER
BY, EDWIN SHANKAR & DAMON RECKLEY
DIGITAL FUNDAMENTAL PROJECT
BY EDWIN SHANKAR & DAMON RECKLY
The parity generator is the method to check the error present while transmitting data from the transmitter node to the receiver node. Parity generator is of two types they are odd parity generator and the even parity generator. The reversible logic gates are used in the generation of the parity generator and for the parity checker. This is done using the reversible logic gates since the reversible logic gates are non- information loss gates. This parity generating technique is the most efficient technique and is one of the most widely used in the error detection techniques for the data transmission. This generation and the checking of the parity of the bits are performed by the method of the reversible logic gate makes the data transmission much easier than the conventional methods. This use of the reversible logic gates reduces the loss of information, delay and the number of gates used. Reversible logic enables the circuit to perform the retival of the information easily by using the garbage values in the reversible gates.
INTRODUCTION:
A B C D PARITY NOT Q0 0 0 00 0 0 1 1 ABC D0 0 1 0 1 ABD C0 0 1 10 1 0 0 1 ACD B0 1 0 10 1 1 00 1 1 1 1 A BCD1 0 0 0 1 BCD A1 0 0 11 0 1 01 0 1 1 1 B ACD1 1 0 01 1 0 1 1 C ABD1 1 1 0 1 ABCD1 1 1 1
TRUTH TABLE
Following is the truth table and K-map for even parity
AB ABCDCD
ABCD+ABCDAB ABCD UNCOMCD NOT
AB ABCDCD
ABCD+ABCD ABCD+ABCD+ABCD+ABCDAB ABCD ABCD+ABCD+ABCD+ABCD+CD ABCD+ABCD+ABCD+ABCD
AB ABCDCD ABCD+ABCD+ABCD+ABCD
ABCD+ABCDAB ABCDCD
AB ABCDCD
ABCD+ABCDAB ABCDCD
AND
AND
AND
AND
AND
AND
AND
AND
OR
OR
OR
OR
OR
OR
OR
PROTO BOARD
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MATERIALS
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NIGHT OUT
SET UP MODE
FINAL SETUP
WORKING CIRCUIT