DIGITAL ELECTRONICS Synchronous & Asyn Counters

Chapter 8

Sequential Circuits for Registers and Counters

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 5

Synchronous and Synchronous and Asynchronous CountersAsynchronous Counters


• Synchronous counter•• Asynchronous clear, preset and Asynchronous clear, preset and

LOAD (JAM) in a counter LOAD (JAM) in a counter •• Asynchronous clear, preset and Asynchronous clear, preset and

LOAD (JAM) in a counterLOAD (JAM) in a counter

Outline


•• Asynchronous counters have a Asynchronous counters have a characteristic that first FF at input characteristic that first FF at input stage has a propagation delay of tp stage has a propagation delay of tp and last stage has nand last stage has n×× tp delay. tp delay. Hence, counter shows next count Hence, counter shows next count correctly only after ncorrectly only after n×× tp delaytp delay

Problem with asynchronous counters


•• Synchronous counters use Synchronous counters use additonal additonal circuits such that all FFs undergoes circuits such that all FFs undergoes transition simultaneously. A transition simultaneously. A characteristic is first FF at input stage characteristic is first FF at input stage has a propagation delay of tp and last has a propagation delay of tp and last stage also has tp delay. Hence, counter stage also has tp delay. Hence, counter shows next count correctly after tp shows next count correctly after tp delaydelay

Synchronous counters


Synchronous Counting using additional circuit

• The J and K inputs connect together in each flip-flop, and are connected to a logic combinational circuit. J and K inputs are held ‘0’ so that Qs don’t change up to the final stage gets the counting input. As soon as final stage gets the input, the J and K of all FFs will simultaneously equal to ‘1’ and toggle as per the inputs (See Text for circuit)


Timing Diagram when -ve edge Synchronous counter

CLK(shift)

QA

QB

t

QC

All QA QB, QC and QD identical delay from clock edge

QD


• Synchronous counter•• Synchronous clear, preset and Synchronous clear, preset and



Outline


Clear and Preset Operations

• There may be a need to reset all Qs as 0s at the start of the counter. [For example, in a up counter.] It is called CLEAR operation.

• There may be a need to reset all Qs as 1s at the start of the counter. [For example, in a down counter.] It is called PRESET operation.


JAM (Load) Operations

• There may be a need to set certain Qs as 1s and remaining as 0s at the start of the counter It is called JAM operation.


Synchronous clear and Load• TTL 74163 or CMOS 74HC163 has

synchronous clear and synchronous load facility.

• In that case, the clear, preset or load inputs must be properly defined at a time, ts, called setup time, before a clock edge at the input is activated.


Synchronous Operation

• The effects of the CLR (clear) or PR (preset) or load inputs appear in the outputs only after a time equal to ∆TFF from the clock input transition i.e. activation (net time taken > ts+ ∆TFF). Here the ∆TFF ispropagation delay within a FF of the counter


• Synchronous counter•• Synchronous clear, preset and Synchronous clear, preset and



Outline


Asynchronous Operation

• The effects of the CLR (clear) or PR (preset) or load inputs appear in the outputs only after a time equal to m × ∆TFF from the n clock input transitions i.e. activation (net time taken > ts+ m × ∆TFF). Here the ∆TFF is propagation delay within a FF of the counter and m × ∆TFF is propagation delay between first stage and last stage FFs and combinational; circuits at a counter


Summary


We learnt• Operations in a counter are counting, clear

of all Qs to 1s, presetting of all Qs to 1s and loading the Qs.

• Two type of operations— synchronous and asynchronous


End of Lesson 5

Synchronous and Synchronous and Asynchronous CountersAsynchronous Counters


THANK YOUTHANK YOU

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DIGITAL ELECTRONICS Synchronous & Asyn Counters