Digital Communication Lab (New Scheme)_ Modified

R.V.COLLEGE OF ENGINEERING, BANGALORE 560059

DEPARTMENT OF TELECOMMUNICATION ENGINEERING

LABORATORY MANUAL

V SEMESTER TELECOMMUNICATION

TC DIGITAL COMMUNICATION LABORATORY

DEPARTMENT OF TELECOMMUNICATION, R V C E2

DO’S AND DON’TS IN THE LABORATORY

Come in proper dress code as prescribed by the college

Come well equipped to the lab. (Datasheets, Practical record book, Graph sheets, calculator etc).

Read the theory of the experiment to be performed well in advance and understand the working principle clearly before conducting the experiment.

Come prepared for viva - voce.

Follow the given procedure in the same sequence.

USE only 5V power supply for all IC.

Handle the equipment with care.

Materials present in the vicinity of the experiment should be absorbing ones. Remove reflecting objects from the work table.

After the completion of the experiment get the datasheets signed by the staff-in-charge.

Make sure to return all the components and equipments to the stores after the completion of the experiment.

Note: Lab manual should be treated as a guideline only.

2


CONTENTS

Cycle of experiments

Equipment specifications

1. Verification of sampling theorem using flat top samples.2. ASK generation and detection (binary).3. TDM and recovery of two band limited signals.4. FSK generation and detection (binary).5. PCM generation and detection using CODEC chip. 6. BPSK generation and detection (binary).7. DPSK encoder and decoder.8. QPSK modulator.9. Delta modulator and demodulator.10. Adaptive delta modulator and demodulator.11. Generation of 3bit pseudo noise binary sequence using JK flip flops.12. Realization of direct sequence spread spectrum.13. Realization of frequency hopping spread spectrum.

Data sheets.

Viva questions.

Sample question bank.

3


TC DIGITAL COMMUNICATION LAB

Hours/ week: 3 IA marks: 25Exam Hours: 3 Exam marks: 50

LAB ORIENTATION

Study of all the components of Microwave bench Usage of digital oscilloscope / Spectrum Analyzer

CYCLE – I

1. Verification of sampling theorem using flat top samples.2. ASK generation and detection (binary).3. PCM generation and detection using CODEC chip.4. TDM and recovery of two band limited signals.

CYCLE – II

1. FSK generation and detection (binary).2. PSK generation and detection (binary).3. DPSK encoder and decoder.4. QPSK modulator and demodulator.

CYCLE – III

1. Delta modulator and Demodulator.2. Adaptive delta modulator and demodulator.3. Generation of Pseudo Random Noise binary sequence using shift register.4. Generation of WALSH code and BARKER code.5. Generation of DSSS and FHSS.

Prof. and Head

4


Expt. No. 1 SAMPLING THEOREM

AIM: - (a) To verify sampling theorem using flat top sampling.(b) To observe the effect of under and over sampling.

APPARATUS REQUIRED:Op-Amp (μA 741), CD4016 IC, resistors, capacitors, signal generators, CRO, power supply, cables and accessories.

PRINCIPLESampling of a signal is a fundamental operation in digital communication. A continuous time signal is first converted to discrete time signal by sampling process. The sufficient numbers of samples have to be taken so that the original signal can be recovered from sampled values.

Statement: Let m(t) is a message signal band-limited to W Hz. If this signal is sampled at a rate of fs ≥ 2W, then we can reconstruct the information from the sampled values with less distortion. i.e. fs ≥ 2W where W = max. Message signal frequency. fs = Sampling frequency.

PROCEDURE: -

a) For flat-top sampling :-

1. Rig up the circuit as shown in fig (a).2. A sinusoidal signal is given as input message (fm) (5V and 3.4 kHz).3. A square wave of amplitude 5V, frequency fs is given at the control input

of the analog switch. fs = 2fm – Nyquist sampling 1. fs > 2fm – Over sampling 2. fs < 2fm – Under sampling

4. The sampled output is held at the output terminal using capacitor ‘C’.5. The output is observed on the CRO for different sampling frequencies.

b) For reconstruction of message signal :-

1. Rig up the circuit as shown in fig (b).2. The flat-top sampled signal from the sample & hold circuit is given as the

input to the filter.3. The cut-off frequency of the filter is chosen to be slightly greater than the

message frequency ( say 5 kHz for a message frequency of 3.4 kHz). 4. The recovered message signal at the output of the filter is displayed on

the CRO & is compared with the input message signal for different sampling frequency fs.

5. Plot the outputs obtained on a graph sheet with suitable scale.

5


OBSERVATIONS: -Part (a): - Amplitude of message signal = Volts Frequency of message signal = Hz Amplitude of sampling signal = Volts Frequency of sampling signal = Hz

Part (b): - Amplitude of recovered signal = Volts Frequency of recovered signal = Hz

DESIGN: -

1. fs : sampling frequency fm : message frequency

fs ≥ 2fm

fs = 2fm – Nyquist rate of frequency fs < 2fm – Under samplingfs > 2fm – Over sampling

Ex: If the message signal frequency = 3.4 kHz, then for proper reconstruction Fs > (2×3.4) kHz

2. Design of reconstruction filter

(i) Gain A0=1 + (RF/R1) [Hint: 2nd order Butter worth polynomial is S2+1.414S+1]

For 2nd order Butterworth filter, A0=1.586

.˙. 1 + (RF/R1) = 1.586

Let R1 = 10 KΩ, RF = 5.86 KΩ

(ii) Cut-off frequency fc = 1

Let R2=R3=R C2=C3=C Then fc = 1 / (2лRC)

Choose fc = Hz and C = F

R = 1 / (2лfcC) = Ω

CD 4016:

2л√R2C2R3C3

6

R

R


It is a CMOS quad analog switch

VDD = +15V VSS = GND S1 S2 S3 S4

Input 1 4 8 11Output 2 3 9 10Enable(control)

13 5 6 12

CIRCUIT DIAGRAM: -

Sample and hold circuit :

Reconstruction FilterResults:

7

VDD

E0

E3

Y3

Z3

Z2

Y2

1 2 3 4 5 6 7

14 13 12 11

CD4016

PIN diagram :

_

A741

+15V

-15V

_

A741

+15V

-15V

MessageInput(3.4 kHz)

1 (i/p)

13

14

VCC

2 (o/p)

7

GND 5V 0 Sampling Signal

C 0.1F

S/H Output

CD4016

Fig. (a)

Output

_

A741

+15V

-15V

RF

S/HSignal

R1

C

C

Fig. (b)


Expt. No. 2 AMPLITUDE SHIFT KEYING (ASK)

AIM: -To design and study the working of binary ASK system. To demodulate the above signal with the help of suitable circuit.

APPARATUS REQUIRED:Op-Amp (μA 741), Transistor, Diode, resistors, capacitors, signal generators, CRO, power supply, cables and accessories.

PRINCIPLEIn an ASK system , the binary symbol 1 is represented by transmitting a sinusoidal carrier wave of fixed amplitude A and fixed frequency f for a bit duration T seconds, where as the binary symbol 0 is represented by switching off the carrier k for T seconds A cos(2Лf t) symbol 1 S(t) =

0 symbol 0

To generate ASK wave, we have to apply the incoming binary data in unipolar format to a product modulator. The detection of an ASK wave is done using a coherent detector with an appropriate threshold level or using an envelope detector.

PROCEDURE: -

a) Modulation:-

1. Rig up the circuit as shown in fig(a).2. The message signal (square wave of frequency 200Hz) is applied to the

base of the transistor.3. The carrier signal (sine wave of frequency 1-2kHz) is fed to the collector

circuit of the transistor.4. The output ASK signal is taken across the emitter resistor RE.5. Observe the waveforms on the CRO and plot it.

b) Demodulation:-

1. Rig up the circuit as shown in fig (b).2. The ASK signal generated is fed at the input of envelope detector which

gives distorted square wave.3. The output of the envelope detector is compared with Vref using a

comparator to get proper square wave.4. The output of the comparator is the recovered message which is

compared with the input message.

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OBSERVATIONS: -

Amplitude of message signal = Volts Frequency of message signal = Hz Amplitude of carrier signal = Volts Frequency of carrier signal = Hz Modulated signal amplitude = VoltsDemodulated signal amplitude = VoltsDemodulated signal frequency = Hz

DESIGN: -

a) Modulator

: IC(sat) = 2 mA VCE(sat) = 0.2V hfe(min) = 30

Vbe(sat) = 0.7V

RE = VE = VC - VCEsat = 8 – 0.2 = 3.9kΩ Choose RE = 3.3kΩ Rb = Vm - Vbe(sat) = 10 – 0.7 = 139.5kΩ Choose Rb = 140kΩ

b) Demodulator

Cut-off freq fc = 1 / (2лRC)

Let message freq = 200 Hz

Choose fc = 800 Hz (passing upto 4th harmonics) Let C = 0.1F

R = 1 / (2лfcC) = 2kΩ (use pot)

Vref = AcTb / 4 Ac = 8V Tb = 1/(2x2x10-3) Vref = Volts

CIRCUIT DIAGRAM: -

IC 2x10-3IE

[2x10-

3/30][ICE(sat)/hfe(min)]

9


(i) Modulator

(ii) Demodulator

10

RE

SL100

Carrier c(t)

6V

ASKoutput

Rb

m(t)

message

Fig. (a)

OA79

C

R ASK i/p

demodulatedmessage Signal

_

+15V

741 -15V

m(t)

Vref

Fig. (b)


11


Expt. No. 3 TIME DIVISION MULTIPLEXING (TDM)

AIM: - To study the working of time division multiplexing circuit for Pulse Amplitude Modulated (PAM) signals.

APPARATUS REQUIRED:

PRINCIPLEIn Pulse Amplitude Modulated (PAM) systems, the sampled carrier pulses occupy only a portion of the time interval between samples. Thus, with TDM technique the time interval between samples is used by other independent massage sources on a time-sharing basis.The multiplexer unit multiplexes the different message signals, converts the different message signals into a set of pulses on a time division basis. At the receiving end a de-multiplexer is used to separate the sampled pulses of different messages and low pass filters do the reconstruction of the different messages.CD4051 an IC can be used as multiplexer or de-multiplexer and up to eight signals can be multiplexed.

PROCEDURE: -

c) TDM:-

1. Set up the circuit as shown in Fig a. CD4051 is used for multiplexing two signals.

2. One signal is applied at I0 and the other signal at I1 input of the multiplexer IC (pins 13 and 14).

3. VCC is connected to +5V. VEE is grounded or connected to –5V. VSS is grounded. The inhibit input (INH – pin 6) is also grounded.

4. The output is taken at pin 3. Selection lines B & C (pins 9 & 10) are grounded. The control signal is applied to A (pin 11) with a frequency greater than twice the maximum frequency of the input signals.

5. Design the demodulation (reconstruction) circuits and rig – up as shown above.

6. Observe the reconstructed output and compare with input signals.Note:- To generate PAM waves follow the procedure given below.

d) PAM:- Principle:- Pulse amplitude modulation, the simplest form of pulse modulation, is illustrated in the figure. PAM is a pulse modulation system in which the signal is sampled at regular intervals, and each sample is made proportional to the amplitude of the signal at the instant of sampling. The pulses are then sent by either wire or cable, or else used to modulate a carrier. There are two types of PAM, double-polarity PAM and single-polarity PAM. In single-polarity PAM a fixed DC level is added to the signal, to ensure that the pulses are always

12


positive. PAM is used infrequently because it does not utilize constant amplitude pulses, and when it is used, the pulses frequency-modulate the carrier.Modulation:

1. To generate PAM signal, rip up the circuit as shown in fig(c).2. Apply sinusoidal message signal at the base of the transistor(say

frequency 1kHz).3. Square wave sample pulses are applied at the collector of the transistor

(frequency is higher than message signal frequency say 10kHz)4. PAM output is observed across emitter resistor RE.

Demodulation:1. Apply PAM signal to envelope detector as shown in fig(d).2. Design RC filter to pass only message signal.3. The filter will eliminate the higher frequency components and demodulated

message is obtained at the output.4. Compare demodulated message with actual message.5. Observe the waveforms on CRO and plot it.

Block Diagram: -

Pin Diagram of CD4051: -

Function Table of CD4051: -

INPUT GATES ON CHANNELINHIBIT C B A

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

13

MUX DEMUXLPF

LPF

X1 (t)

X2 (t)

X1R (t)

X2R (t)

TDM

Control Signal

VDD

I2

I1 Inputs I0

I3

A B Selection Lines C

I4

I/O I6

OUTPUT I7

I/O I5 INHIBIT VEE

VSS

1 162 C 153 D 144 4 135 0 126 5 117 1 108 9


0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 X X X NONE

CIRCUIT DIAGRAM: -

Low Pass Filter (LPF): -

Results:

Expt. No. 4 FREQUENCY SHIFT KEYING (FSK)

TDM Signal

GND

A B CA B C

VCC

Control Signal

13 6 714 16

CD 3405 1 8

11 10 9

6 7 13 16 14

CD

3 405

8 1

11 10 9

VCC

GND

VEE VEEINHINH LPF

LPF

14

X1R(t)

X1(t) Io

X2(t) I1

X2R(t)

RCf

2

1

R

C 0.1μFI/P O/P


AIM: -To design and demonstrate the working of FSK and demodulate the signal with the help of a suitable circuit.

APPARATUS REQUIRED:NE/SE 565 PLL IC, 555 IC, Op-Amp (μA 741), Transistor, resistors, capacitors, signal generators, CRO, power supply, cables and accessories.

PRINCIPLEIn an FSK system, two sinusoidal waves of the same amplitude A, but different frequencies f1 and f2 are used to represent the binary symbols1and 0.

A cos(2Л f1 t) symbol 1 S(t) =

A cos(2Л f2 t ) symbol 0

To generate FSK wave, we may apply the incoming binary data represented in the polar format to a frequency modulator. As the modulator input changes from one voltage level to another, the transmitted frequency changes in a corresponding fashion. PROCEDURE: -

a. Modulation:-1) Rig up the circuit as shown in the figure.2) Switch on the supply and apply a LOW to the transistor so that it is OFF.3) Vary the pot RA to get an output frequency f0.4) Apply a HIGH to the transistor so that it is ON.5) Vary the pot RC to get an output frequency f1.6) Apply a square wave of given frequency and observe the FSK o/p.

b) Demodulation:-1) Rig up the circuit as shown in the figure.2) Apply the FSK signal to the i/p and observe the demodulated o/p.

DESIGN: -a. Modulator:-

f1 = 1270 Hz f2 = 1070 Hz Choose RB = 47k C = 0.01μF

For astable mode f0 = 1.44 / (RA+RB)C RA = 40k Use 47k pot + 10k resistance For monostable mode f1 = 1.44 / (RARC)+2RBC Let RB = 40k

15


C = 0.01μF RARC = 20k

Choose RA = RC = 40k Use 47k pot + 10k resistance for both RA and RC

b. Demodulator:- f1 = 1270Hz f2 = 1070Hz fout = (f1+f2)/2 = 1170Hz fout = 1.2 /4R1C1 Let C1 = 0.01μF R1 = 25k V = 5-(-5) = 10Volts fLOCK = ±8fout/V = ±936Hz fH = 1/2лR’C’ R’=10k C’=0.02μF

CIRCUIT DIAGRAM: -MODULATOR:

(ii) Demodulator

16

R1 10k


Results:

17

_

+15V

-15V

741 4

10 7 4

1234567

14 NC 13 NC 12 NC 11 NC 10 V+

9 Ext Cap for VCO8 Ext R for VCO

V-

i/p i/p VCO o/p

Phase comparator VCO i/p Ref o/p Demod o/p

NE565

C2

0.02μF 0.02μF 0.02μF 0.15μF

0.01μF

10k 10k 10k

680Ω

680Ω

27k 0.1μF

0.047μF

R2

R3

-5V

FSK i/p

5

6

8

1 9 3 2

NE/SE 565 PLL o/p


Expt. No. 5 PHASE SHIFT KEYING (PSK)

AIM: - a) To design and demonstrate the working of BPSK modulated signal.b) To demodulate the BPSK signal to recover digital data.

APPARATUS REQUIRED:Op-Amp (μA 741), Transistor, Diode, resistors, capacitors, signal generators, CRO, power supply, cables and accessories (Balanced Modulator).

PRINCIPLEIn a PSK system, a sinusoidal carrier wave of fixed amplitude A and fixed frequency f is used to represent both symbols 0 and 1, except that the carrier phase for each symbol differs by 180 degrees. The PSK may be represented as follows.

A cos(2Л f t) symbol 1 S(t) =

A cos(2Л f t + Л) symbol 0

To generate PSK wave we can apply the signal in polar format to a product modulator. The detection of the PSK wave can be done using a coherent detector by choosing an appropriate threshold level.

PROCEDURE: -

a) Modulation:-1) Rig up the circuit as shown in fig(b).2) Apply the message signal m(t), a square wave of frequency 500 Hz, at the

base of each transistor.3) A carrier signal (sine wave) of frequency 2kHz is applied as shown in the

figure.4) During the positive half cycle of the message m(t), the transistor T1 will

conduct and the output of the op-amp is in phase with the carrier, as the input is given to the non-inverting terminal.

5) During the negative half cycle of the message m(t), the transistor T2 will conduct and the output of the op-amp is 180o out of phase with the carrier, as the input is given to the inverting terminal.

6) The output of the op-amp is the BPSK signal.7) Adjust the 10k pot to get equal gain for both the cycles.8) Observe the waveform on the CRO.

18

R


b) Demodulation:-1) Rig up the circuit as shown in fig(d).2) Apply BPSK signal and reference carrier at the input of the adder as

shown in fig(d).3) The output of the adder gives the ASK signal.4) The ASK signal is applied to the envelope detector to get the demodulated

output.5) The waveform may be distorted. To get a smooth output, apply the

demodulated signal to a comparator with proper Vref.6) The output of the comparator gives a perfect square wave message.

DESIGN: -

Modulator:-

RC >> T Choose RC = 10T Let f = 500Hz T=1/f Choose C = 1μF Find R

CIRCUIT DIAGRAM: -

(i) Using IC1496 (Balanced Modulator)

19

_

+15V

3 +

- 15V

BM-I1496

Fig. (a)

MessageSignal BM-II

1496 C

0.01μF BPSK

BPSK741

DemodMessage o/p

Carrier signal

Modulator Buffer Demodulator


(i) Modulator(ii) Circuit Diagram

Alternate circuit for BPSK Modulation :

20

Fig. (b) BPSK Modulator

3 + _

mA741

+15V

-15V

10k

10k pot

10k

10k

1k

c(t)carrie

rsignal

m(t) digital data

BPSKsignal

SK100

SL100

T1

T2

Message m(t)

BPSK output

OA79

CarrierSignal c(t)

Fig. (c)


Demodulator :

Output WAVEFORMS:

Results:

21

OA79

C

R

O

O/p

3 + _

+15V

-15V

Vref

Fig. (d)

3 + _

+15V

-15V

ADDER

1k

1k

ENVELOPEDETECTOR

COMPARATOR

BPSKsigna

Reference Carrier

1k

1 0 1 1 0Binary Data

PolarRepresentation

Carrier c(t)

BPSK signal


Expt. No. 6 DIFFERENTIAL PHASE SHIFT KEYING (DPSK)

AIM: - To demonstrate the working of DPSK encoder and decoder with the help of a suitable circuit.

APPARATUS REQUIRED:

DPSK Encoder and Decoder kits, Signal Generator, CRO and accessories.

PRINCIPLE

As for PSK, it cannot be detected non-coherently because the envelope of a PSK wave is the same for both the symbols 1 and 0 and a single carrier frequency is used for the modulation process. To eliminate the need for phase synchronization of the receiver with PSK, we may incorporate differential encoding. In differential encoding, we encode the digital information content of a binary data in terms of transitions. A signaling technique that combines differential encoding with phase shift keying is known as differential phase shift keying (DPSK). The DPSK wave can be detected by multiplying the signal with a delayed version of itself and then applying it to an integrator followed by a decision device with an appropriate value of threshold. Thus the need for phase and timing synchronization is eliminated.

PROCEDURE: -

a) Transmitter:-

1. Connect the power cord to the power supply asRed : +5VBlack : GNDGreen : +12VBlue : -12V

2. Select the input bit stream by the combination of DIP switches.3. From this switch, 8-bit data is available.4. Select proper transmission rate, either 300bps or 600bps, by connecting

jumpers.5. By connecting jumper select NRZ(L) data at the output of the data

generator.6. By using EX-OR gate and 1 bit delay ckt, we can generate encoded bit

stream.ck = bk ck-1

7. The DPSK data changes the phase of the carrier whenever the selected data bit is ‘0’ and remains in the same phase when the data bit is ‘1’ (For bit ‘1’ it will select sine function whereas for bit ‘0’ it will select inverted sine function).

8. The DPSK waveform is displayed on the CRO.9. The experiment is repeated for different data patterns.

22


b) Receiver:-

1. The interface card is connected between transmitter and receiver.2. DPSK modulated signal is given to the adder ckt with or without noise.3. This signal is passed through BPF to minimize noise effect.4. The output of the BPF is applied at the input of the multiplier with reference

carrier.5. The output of the multiplier is passed through a filter to eliminate high frequency

components.6. The filter output is connected to the comparator with proper Vref to get perfect

digital data.7. This data is decoded using EX-OR and 1-bit delay ckt.8. The decoded data at EX-OR is latched at the output and observed on the CRO.

OBSERVATIONS: -

a) Modulator

Input bit stream bk 1 0 1 1 1 0 0 0Encoded bit stream ck 0 1 1 0 1 0 0 0 0

DPSK phase 0 0 Л 0 Л Л Л Л

b) Demodulator

Modulated DPSKsignal phase(RX signal)

0 0 Л 0 Л Л Л Л

Comparator outputbit stream

1 1 0 1 0 0 0 0

Decoded outputbit stream

0 1 0 1 1 1 0 0 0

23


BLOCK DIAGRAM: -

DPSK Transmitter :

DPSK Receiver :

24

DIVIDE BY 8

DATAGENERATOR

NRZ(L) Select

Ext DataParallel 8-bit

DataFrom DIP

MUX2:1

INVERTER

1 BIT

DELAY

DPSK MODULATEDOUTPUT

SINE WAVE GENERATOR

(10kHz)

600bps

300bps

NRZ(L) Selection Logic

300bps

600bps CLOCK

GENERATION

CLOCK

DIVIDER

Encoded Data

EX-OR

MULTIPLIER LPF

Reference Sine

1 BITDELAY

EX-OR

LPFADDER

Noise In

DPSK signal (from TX)

LEVELCONVERTER LATCH

DecodedData

Vref


Expt. No. 7 PCM using CODEC chip

AIM: - To study the generation of PCM wave and reconstruction of analog signal from PCM using CODEC chip.

Principle:

PCM produces a series of numbers or digits usually in binary code representing the approximately amplitude in of the signal sample at that instant. In PCM, the total amplitude range, which the signal may occupy is divided into the number of standard levels are represented by the binary code, the actual number of levels is the power 2. the essential operation of a PCM transmitter are sampling, quantization and encoding. Quantization refers to the use of finite set of amplitude levels and selection of a levels nearest to a particulars sample value of the message signals as represented for it. The quantization and coding process are performed in the same circuit known as A-D converter . the essentials of the receivers are regeneration, decoding and demodulation of the train pulses, which are performed in the same circuit called as D-A converter.the quantization process introduces some distortion known as quantization noise.Advantage of PCM:1. PCM has much better noise immunity.2. PCM doesnot suffer from gradual deterioration and degradation as in the case of analog signals.

Disadvantages:1. PCM requires very complex encoding and quantizing circuitary.2. PCM requires a large bandwidth compared to analog systems.

Application:

24 channel telephony (t1 systems), space communication, broadband network etc.

a) Clock divider circuit:

Fig-1

25


CODEC chip circuit diagram:

Procedure:

1. Rigup the clock circuit to generate 8 kHz synchronous clock and test the o/p.

2. Rigup the CODEC circuit as shown in the figure.3. Apply the clock (2 kHz) and synchronous (8 kHz) signals.4. Apply the input (analog signals) of frequency less than 3.4 kHz (with in the

voice band).5. Observe the PCM o/p at pin 15 and note down the o/p.6. Measure the frame duration (125microsec).7. Connect the PCM O/P to the PCM I/P and observe the reconstructed

signals.8. Compare the analog I/P and reconstructed input.

Observation:

26


Expt. No. 8 QUADRATURE PHASE SHIFT KEYING (QPSK)

AIM: - To generate QPSK signal by using suitable circuit and also to demodulate QPSK signal.

APPARATUS REQUIRED:

QPSK Encoder and Decoder kits, Signal Generator, CRO and accessories.

PRINCIPLE

In binary data transmission, we send only one of two possible signals during each bit of interval Tb. On the other hand, in an M-ary data transmission system we send any one of the M possible signals, during each signaling interval T. For almost all applications, the number of possible signals M=2 to the power of n. It is apparent that a binary data transmission system is a special case of M-ary data transmission system. Each of the M signals is called a symbol. The rate at which these symbols are transmitted through the communication channel is expressed in units of bauds. A baud stands for one symbol per second; for M-ary data transmission, it equals log2M bits per second.

In this section we consider quadriphase-shift keying(QPSK), which is an example of M-ary data transmission with M=4. In QPSK, one of the four possible signals is transmitted during each signaling interval, with each signal uniquely related to a dibit (pairs of bits are termed dibits).

PROCEDURE: -

a) Transmitter:-

1. Select proper clock speed either 300bps or 600bps.2. Connect the power cord to the power supply as

Red : +5VBlack : GNDGreen : +12VBlue : -12V

3. Select the input bit stream by the combination of DIP switches.4. Connect NRZ(L) line to the data select line.5. Check the working of individual MUX, each MUX has to work as a PSK

modulator.6. Output of each MUX is combined using the adder circuit. The output of the adder

ckt gives QPSK signal which is observed on the CRO.

b) Receiver:-1. The interface card is connected between the transmitter and receiver.

27


2. The reference sine & cosine carrier signals are applied to the two multipliers along with the received QPSK signal.

3. The 1st multiplier acts as in-phase detector and the 2nd multiplier acts as quadrature detector.

4. The odd and even sequences are demodulated separately.5. The output at the level converter is obtained by adjusting the pot connected to the

reference voltage.6. The recovered bit stream is observed on the CRO and compared with the inout bit

stream.OBSERVATIONS: -

Input bit stream b(t) 0 0 0 1 1 0 1 1

Odd bit stream bo(t) 0(-1)

0(-1)

1(+1)

1(+1)

Even bit stream be(t) 0 (-1)

1 (+1)

0 (-1)

1 (+1)

Phase of modulated output

Л/4 3Л/4 -3Л/4 -Л/4

BLOCK DIAGRAM: -QPSK Transmitter :

28

WORD PULSE

GENERATOR

DATAGENERATOR

BIT SPLITTER

NRZ(L) Select Data

Ext Data

DIP SWITCHDATA PATTERN

Parallel 8-bit Data

MUX2:1

INVERTER

MUX2:1

INVERTER

Ext DataOdd Bit Stream

Ext DataEven Bit Streamsin

——

sin

cos

——

cos

ADDER

QPSK

O/P

CARRIERGENERATOR

(10kHz)

90O PHASESHIFTER

600bps

300bps


QPSK Receiver :

Observation:

Results:

Expt No: 9

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MULTIPLIERLEVEL

CONVERTERLPF

Ref Sine

Vref

MULTIPLIERLEVEL

CONVERTERLPF

Ref Cos

Vref

BPFQPSKinput

BIT COMB-

INERLATCH

O/P

(ParallelTo Serial)


Aim: To realize delta modulation and demodulation using suitable circuit.Components and equipments required: Sl.No Components. Value and quantity.1. Operational Amplifier UA741 (3).2. Transistors. Q2N3904 (1).3. Resisters 1k(3), 50k(1), 10k(3),

39k(1),100k(1).4. Capacitors. 0.22u(1), 0.2n(1).5. Power supply. 0-30V.6. Signal generators 0-2MHz(2).

Theory: Delta modulation (DM or Δ-modulation) is an analog-to-digital and digital-to-analog signal conversion technique used for transmission of voice information where quality is not of primary importance. DM is the simplest form of differential pulse-code modulation (DPCM) where the difference between successive samples is encoded into n-bit data streams. In delta modulation, the transmitted data is reduced to a 1-bit data stream.

Principle of operation:

The analog signal is approximated with a series of segments

Each segment of the approximated signal is compared to the original analog wave to determine the increase or decrease in relative amplitude

The decision process for establishing the state of successive bits is determined by this comparison

Only the change of information is sent, that is, only an increase or decrease of the signal amplitude from the previous sample is sent whereas a no-change condition causes the modulated signal to remain at the same 0 or 1 state of the previous sample.

Rather than quantizing the absolute value of the input analog waveform, delta modulation quantizes the difference between the current and the previous step, as shown in the block diagram in Fig. 1.

Fig. 1 - Block diagram of a Δ-modulator/demodulator

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http://en.wikipedia.org/wiki/Digital_signal

http://en.wikipedia.org/wiki/Information

http://en.wikipedia.org/wiki/DPCM

http://en.wikipedia.org/wiki/Pulse-code_modulation

http://en.wikipedia.org/wiki/Pulse-code_modulation

http://en.wikipedia.org/wiki/Analog_signal

http://en.wikipedia.org/wiki/File:Delta1.svg


The modulator is made by a quantizer which converts the difference between the input signal and the average of the previous steps. In its simplest form, the quantizer can be realized with a comparator referenced to 0 (two levels quantizer), whose output is 1 or 0 if the input signal is positive or negative. The demodulator is simply an integrator (like the one in the feedback loop) whose output rises or falls with each 1 or 0 received. T

Circuit diagram:

V 5

TD =

TF = 1 0 0 nP W = 2 0 uP E R = 0 . 1 m

V 1 = 0

TR = 1 0 0 n

V 2 = 5

U 1

u A 7 4 1

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U 2

u A 7 4 1

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U 3

u A 7 4 1

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

R 1

5 0 k

R 2

1 k

R 3

1 k

R 4

7 k

R 5

3 9 k

R 6

1 0 0 k

C 1

0 . 2 2 u

0

V 2

F R E Q = 5 0 0V A M P L = 1 0 0 mV O F F = 0

Q 1

Q 2 N 3 9 0 4

U 4

u A 7 4 1

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

n e g

V C C

V 31 5 V d c

V 41 5 V d c

r

0

R 7

1 0 k

R 8

1 0 k

V C C

C 2

. 2 n

n e g

n e g

V C C

n e g

r

V C Ct o u t

r

n e g

V C C

0

t o u t

IN OUT

4 0 0 0 H z1 0 0 0 h z 1 d B

5 0 d B

0

V

Procedure:Part –A: Delta modulation:1. Rigup the circuit as shown in the figure above.2. Apply the voltage of the pulse to 5V and frequency to 10kHzfrom the signal generators to summer circuit.3. Apply voltage of the message signal to 5v and frequency to 500Hz from signals generators to summer circuit as shown in figure above.4. Apply the above resulting signal to quantizer and step delay circuit.6. Observe the output waveform as shown below.7. Note down the duration of the delta signal and plot the graphs.Part-B: Delta demodulation:1. Rig up the circuit for recovery of the message signal from modulation.2. Apply the modulated output to the input of the integrator fallowed by low pass filter.

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3. Observe the waveform for message signal from the demodulation circuit.

Expected waveforms:

Results:

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Expt 10: Generation of pseudo noise binary sequence using J-K flip flop.

Components required: Sl.No Components. Value and quantity.1. J-K flip flop. (3)2. 2 input XOR gate (1)

Theory: Generation of PN sequence:

Fig 1: Maximum-length sequence generator for n=3A feedback shift register is said to be Linear when the feed back logic consists of entirely mod-2-address ( Ex-or gates). In such a case, the zero state is not permitted. The period of a PN sequence produced by a linear feedback shift register with ‘n’ flip flops cannot exceed 2n-1. When the period is exactly 2n-1, the PN sequence is called a ‘maximum length sequence’ or ‘m-sequence’.

Principle of operation: Consider the linear feed back shift register as shown in fig 1. involve three flip-flops. The input so is equal to the mod-2 sum of S1 and S3. If the initialstate of the shift register is 100. Then the succession of states will be as follows.

100,110,011,011,101,010,001,100 . . . . . .

The output sequence (output S3) is therefore. 00111010 . . . . .

Which repeats itself with period 23–1 = 7 (n=3)

Maximal length codes are commonly used PN codes

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In binary shift register, the maximum length sequence is N = 2m-1 chips, where m is the number of stages of flip-flops in the shift register.

Observation:

1 0 01 1 00 1 10 1 11 0 10 1 00 0 1

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DATA SHEET:

a) CD4016:

35


b). HD44233P:

36


37


38


39


c) UA741 OPAMP:

40


41


d) CD4051B:

42


43


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e)

VIVA QUESTIONS

A. Digital Communication

1. State and explain sampling theorem.

2. What is Nyquist rate of sampling?

3. What is aliasing? How is it minimized practically?

4. What should be the minimum sampling rate for a voice signal in the range

300 – 3400 Hz?

5. Explain FDM & TDM

6. What are the advantages of digital communication?

7. What are the disadvantages of digital communication?

8. How can an analog voice signal be digitized?

9. What is quantization? How is this error minimized?

10.Explain sampling theorem for a band pass signal?

11.A message signal is band limited to a frequency range of 10 – 12 kHz, find

the minimum sampling frequency?

12.How messages signal is reconstructed from the sampled values?

13.How is bandwidth measure in the case of AM, DSBSC, SSB and Digital

Modulation?

14.For a given sinusoidal input signal write PAM, PWM and PPM signals.

15.What are the advantages of PPM signals?

16.Explain different types of digital modulation techniques.

17.For the binary data 101101 draw ASK, FSK and PSK modulated

waveforms.

18.Comment on the bandwidth requirement of the various digital modulation

techniques.

19.Explain the need for CODECS.

20.What is PCM draw the block diagram of a typical PCM system?

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21.For an 8 – bit PCM system if the voice signal is sampled at the rate of 8k

samples /sec, find the rate of transmission and bandwidth requirement.

22.What is delta modulation (DM)?

23.Explain the different types of errors in DM,

24.Compare the different types of DM techniques.

25.What are the advantages of optical communication?

26.Explain few optical sources and detectors.

27.How is the maximum bit rate supported measured in a digital link?

28.Represent the following binary data in 1.Polar, 2. Bipolar, 3. Unipolar, 4.

Manchester coded and 5. Differential coded forms.

29.Explain the need for M- ary modulation.

30.What is QPSK modulation?

31.What is signal space representation?

32.Write the signal space representation for the following signals a) ASK, b)

FSK and c) PSK.

33.Differentiate between matched filter and correlative filter.

34.What is bit error rate and probability of error in digital modulation?

35.Compare PER of ASK, FSK & PSK modulation techniques.

36.Explain non-coherent ASK & FSK demodulation.

37.What is QAM?

38.Explain a DPSK modulator and demodulator.

39.Differentiate between coherent & non-coherent demodulation techniques.

40. In a PCM system the minimum SNR required is 40dB, how many bits of

quantization is required.

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TC DIGITAL COMMUNICATION LAB

SAMPLE QUESTION BANK

b. Digital Communication

1. For a _____ Hz message signal, design and demonstrate the working of a

flat top sampling circuit. Demonstrate the effect of a) Under sampling, b)

over sampling & c) right sampling, on the demodulated signal with the help

of suitable reconstruction filter.

2. Design and demonstrate the working of TDM for PAM signals with ______

& ____ Hz message signals. With the help of suitable circuits demultiplex

the above message signals.

3. Design and demonstrate an ASK system to transmit ____bps digital date

using a suitable carrier. Demodulate the above signal with the help of a

suitable circuit and determine the minimum carrier frequency for proper

detection.

4. Design and demonstrate the working of FSK system with a suitable circuit

for ___ & ____ Hz carri9er signals. Determine the frequency deviation and

modulation index. Demodulate the above signal with the help of a suitable

circuit.

5. Design and demonstrate the working a BPSK modulation for a carrier

signal of ___Hz to transmit a digital data of ____Hz. Demodulate the

BPSK signal to recover the digital data.

6. With the help of a suitable circuit demonstrate the working of a DPSK

encoder and decoder for a given input stream and carrier frequency.

7. Rig up a DPSK system to avoid error propagation. For a suitable binary

input demonstrate the output with and without error propagation.

8. With the help of suitable circuit modules demonstrate the working of a

QPSK modulator and demodulator.

9. Measure the maximum bit rate a digital link can support by setting up a

digital fiber optic link.

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10.Conduct a suitable experiment using a fiber optic trainer kit to determine

a) Launching angle, b) attenuation loss c) bending loss, of the given

optical fiber

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Documents

Digital Communication Lab (New Scheme)_ Modified