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8/14/2019 Digital Circuit Speed
1/176.002 Fall 2000 Lecture 113
6.002 CIRCUITS ANDELECTRONICS
Digital Circuit
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8/14/2019 Digital Circuit Speed
2/17
6.002 Fall 2000 Lecture 213
C+
Cvv +
t
Cv
OV
IV
( ) RCt
IOIC eVVVv
+= 1
( ) OC Vv =0
t
V
Iv
0
Review
time constantRC
C
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8/14/2019 Digital Circuit Speed
3/17
6.002 Fall 2000 Lecture 313
Lets apply the result toan inverter.
A
B
VS VS
XCGS
t
v
V5
0
1 0 at A
A B
X
First, rising delay tr at B
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8/14/2019 Digital Circuit Speed
4/17
6.002 Fall 2000 Lecture 413
AB
VS VS
XCGS
idealt
v
V5
0
1 0 at A
First, rising delay tr at B
observedt
Bv
V5
0
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8/14/2019 Digital Circuit Speed
5/17
6.002 Fall 2000 Lecture 513
AB
VS VS
XCGS
t
v
V5
0
1 0 at AOHV
rtrising delay of X
First, rising delay tr at B
t
Bv
V5
0
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8/14/2019 Digital Circuit Speed
6/17
6.002 Fall 2000 Lecture 613
Equivalent circuit for 01 at B
+
BvSVv =
+
L
GSC
( ) GSLCRt
SSB eVVv
+= 0
1From
Now, we need to find t for whichvB = VOH .
SVv =for t 0
( ) 00 =Bv
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8/14/2019 Digital Circuit Speed
7/17
6.002 Fall 2000 Lecture 713
GSLCR
t
SSOH eVVv
=
Or
Find tr :
OHS
CR
t
S VVeVGSL
r
=
S
OHS
GSL
r
V
VV
CR
t =
ln
S
OHSGSLr
V
VVCRt
= ln
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8/14/2019 Digital Circuit Speed
8/17
6.002 Fall 2000 Lecture 813
GSLCR
t
SSOH eVVv
=
Or
Find tr :
OHS
CR
t
S VVeVGSL
r
=
S
OHS
GSL
r
V
VV
CR
t =
ln
S
OHSGSLr
V
VVCRt
= ln
e.g. KL 1=
pFCGS 1.0=
VVS 5=
VVOH 4=
5
45ln101.0101t 123r
=
ns16.0=
!1.0 nsC=
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8/14/2019 Digital Circuit Speed
9/17
6.002 Fall 2000 Lecture 913
Falling Delay tf
SV+
L
+
Bv
GS
CON
( )( )VVv SB5
0 =
Falling delay tf is
the t for which vB falls to VOL
Equivalent circuit for 1 0 at B
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8/14/2019 Digital Circuit Speed
10/17
6.002 Fall 2000 Lecture 1013
Falling Delay tfEquivalent circuit for 1 0 at B
ONLTH ||=
LON
ONSTH
RRVV
+=
Thvenin replacement
+
BvTHV
TH
GSC+
SV+
L
+
BvGSCON
( )( )VVv SB5
0 =
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8/14/2019 Digital Circuit Speed
11/17
6.002 Fall 2000 Lecture 1113
( ) GSTHCRt
THSTHB eVVVv
+=
1From
Falling decay tf isthe t for which vB falls to VOL
( )GSTH
f
CR
t
THSTHOL eVVVV
+=
orTHS
THOLGSTHf
VV
VVCRt
= ln
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8/14/2019 Digital Circuit Speed
12/17
6.002 Fall 2000 Lecture 1213
THS
THOLGSTHf
VV
VVCRt
= ln
e.g.
5
1ln101.010 12=ft
ps6.1=
!1psC=
KL 1=
pFCGS
1.0=
VVS 5=
VVOL
1=
=10ON
VVTHTH 0,10
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8/14/2019 Digital Circuit Speed
13/17
6.002 Fall 2000 Lecture 1313
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
LC
So the engineers decided to speed it upmade RL smallmade RON
small
RLRON
ideal slow!observedv:
v
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8/14/2019 Digital Circuit Speed
14/17
6.002 Fall 2000 Lecture 1413
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
LC
ideal slow!observed
but, disaster!
v:
v
expected
v:
VIL
observed
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8/14/2019 Digital Circuit Speed
15/17
6.002 Fall 2000 Lecture 1513
Why? Consider1Case 1
0
pin1
ok
Demo
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8/14/2019 Digital Circuit Speed
16/17
6.002 Fall 2000 Lecture 1613
Why? Consider
2Case1
0
pin1
2
pin2
PC
crosstalk!
Demo
model for crosstalk:
+
v
PC
+
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8/14/2019 Digital Circuit Speed
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3Case
6.002 expert saw the solution
Detailed analysis in recitation.
PC1
0
2
+
slower transitions!
