Differential Amplifiers

What is a Differential Amplifier ?

Some Definitions and Symbols

Differential-mode input voltage, vID , is the voltage difference between v1

and v2 .

Common-mode input voltage, vIC , is the average value of v1

and v2 .

Therefore vID = v1 - v2 and vIC = (v1 + v2) / 2

Differential Amplifier: A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages.

v1 v2vout

Symbol for a Differential Amplifier

The output voltage of the differential amplifier can be expressed in terms of itsdifferential-mode and common-mode input voltage as -

Vout = AVDvID + AVCvIC

= AVD (v1-v2) + AVC(v1+v2)/2

Where

AVD = differential-mode voltage gain

AVC = common-mode voltage gain

voutvIC

vID/2

vID/2

Common mode rejection ration (CMRR)

CMRR = AVD

AVC

CMRR - a measure of performanceFor ideal diff Amp – AVC is zero and hence an infinite CMRR

Input Common-mode range (ICMR)

ICMR is the range of common-mode voltages over which the differentialamplifier continues to sense and amplify the difference signal with the same gain.

Typically , ICMR is defined as common-mode voltage range over which all MOSFETs remain in the saturation region.

Offsets:

Output offset voltage (VOS(out)) : It is defined as the voltage which appears at the output of the Diff Amp when the inputs terminal are shorted.

Input offset voltage (VOS(in)) : It is equal to the output offset voltage divided by the differential voltage gain - VOS = (VOS(out) / AVD)

LARGE SIGNAL ANALYSIS

CMOS differential amplifier using NMOS transistors

Configuration of M1 and M2 is known as source coupled pair.

M3 and M4 are a typical implementation of current sink ISS.

Large signal analysis starts with the assumption that M1 and M2 are perfectly matched

iD1 iD2

ISS

Ibias

VBulk

M4

M2M1

M3

VDD

vG2vG1

vGS1 vGS2

Transconductance Characteristics of the Differential Amplifier

Defining Equations:vID = vGS1-vGS2 = (2iD1/)1/2 - (2iD2/)1/2 and ISS = iD1 + iD2

Solution of above equations:

iD1 = SS

SS

vID

2

SS

vID4

SS2

iD2 = SS

SS

vID

2

SS

vID4

SS2

and1/2

1/2Valid for vID < (2ISS/)1/2

Differentiating iD1 w r t vID and setting vID=0V gives differential transconductance of the Diff Amp as gm = (iD1)/(vID) at [VID=0] = (ISS/4)1/2 = (K’1ISSW1/4L1)1/2

iD/ISS

(vID/(ISS/)0.5)

1.0

0.8

0.6

0.4

0.2

iD1

iD2

0.0 1.4141.414

Voltage Transfer Characteristics of the Differential Amplifier

CMOS differential Amplifier using a current-mirror load

Differential-in, differential-out transconductance gmd is given as:

gmd = (iout)/(vID) at [VID=0] = (K’1ISSW1/L1)1/2 = Twice of gm

M2M1

M5

VDD

vG2vG1

vGS1 vGS2

M4M3

Vbias

iD1 iD2

iD3 iD4

ISS

iout

vout

Voltage Transfer Characteristics of the Diff Amp (cont.)

5

4

3

2

1

0-1 -0.5 0 0.5 1.0

vID(volts)

Vou

t(vol

ts)

VIC=2V

M2 saturated

M2 active

M4 saturated

M4 active

Region of operation of the transistors:M2 is saturated when,vDS2 >= vGS2-VTN vout – VS1 >= VIC- 0.5vID – VS1 – VTN vout >= VIC – VTN Where we have assumed that the region of transition for M2 is close to v ID = 0V.

Similarly M4 is saturated when, vSD4>= vSG4- !VTP! VDD- vout >= VSG4 - !VTP! vout =< VDD – VSG4 + !VTP!

Differential Amplifier Using p-channel Input MOSFETs

VDD

M1

M5

vG2vG1

Vbias

iD1 iD2

iD3iD4

IDD

iout

M3 M4

M2

Vout

Input Common Mode Range (ICMR)

ICMR is found by setting vID = 0 and varying vIC until one of the transistors leavesthe saturation region.

Highest Common Mode Voltage: There are two paths from VIC to VDD – (1) From G1 through M1 and M3 to VDD and (2) From G2 through M2 and M4 to VDD

For path (1), VIC(max) = VG1(max) =VG2(max) = VDD – VSG3 –VDS1 (sat)+ VGS1

= VDD –VSG3 +VTN1

For path (2), VIC(max)’ = VDD – VSD4(sat) – VDS2(sat) + VGS2

= VDD –VSD4(sat) +VTN2 ………………… is more than the first case.

Therefore VIC(max) = VDD –VSG3 + VTN1

Lowest Common Mode Voltage:

VIC(min) = VDS5(sat) + VGS1 = VDS5(sat) + VGS2

We have assumed that VGS1 = VGS2 during changes in the input common mode voltage.

SMALL SIGNAL ANALYSIS

Analysis of the Differential-Mode of the Differential Amplifier

Simplifies to

When both sides of the amplifier are perfectly matched then -

ac ground

G1 G2vid

vg1 vg2

1/gm3rds3

rds1

D1=G3=D3=G4

D2=D4

i3

gm1vgs1

S3

gm2vgs2

i3

rds4

iout’

S4

vout

rds2

rds5

S1= S2

Small signal model for the CMOS differential Amplifier (exact model)

Analysis of the Differential-Mode of the Differential Amplifier (cont.)

Differential Transconductance:

iout’ = {(gm1gm3rp1)/(1+gm3rp1)}vgs1- gm2vgs2 = gm1vgs1 – gm2vgs2 = gmdvid

Where gm1 = gm2 = gmd , rp1 = rds1!! rds3 and iout’ designates the output current in a short circuit.

We assume that the output is ac short.

G1 G2vid

vgs2

1/gm3rds3rds1

D1=G3=D3=G4 D2=D4

i3

gm1vgs1

S1=S2=S3=S4

gm2vgs2

i3

rds2 rds4

iout’

vgs1

Simplified equivalent model

Analysis of the Differential-Mode of the Differential Amplifier (cont.)

Therefore differential voltage gain: Av = (vout/vin) = { gmd / (gds2+gds4) }

If we assume that all transistors are in saturation and replace the small signal parametersof gm and rds in terms of their large-signal model equivalents, we achieve

Av = (vout/vin) = (K’1ISSW1/L1)1/2

(2 + )(ISS/2)=

2

(2 + )

K’1W1

ISSL1

1/2

Note that the small signal gain is inversely proportional to the square root of the bias current.

To calculate unloaded differential voltage gain:

rout = 1/(gds2+gds4) = rds2 rds4

Common–Mode Analysis for the Current Mirror Load Differential Amplifier

In an ideal case when there are no mismatches, the current-mirror load rejects anycommon-mode signal.

So the common-mode gain of the differential amplifier with a current mirror load is ideally zero.

In order to show how to analyze the small signal, common-mode gain of the differentialamplifier, we will consider a different circuit.

Let’s see …

Common–Mode Analysis for the Differential Amplifier (an illustration)

Let us consider the circuit shown below:

Differential-Mode Analysis:

vo1/vid = - (gm1/2gm3) and vo2 /vid = + (gm2 /2gm4)

M2M1

VDD

M4M3

vo1vo2

Vid/2 Vid/2

Differential-mode circuit

M2M1

M5

VDD

M4M3

Vbias

v1 v2

ISS

vo1vo2

General circuitGeneral circuit

Common–Mode Analysis for the Diff Amp (an illustration) …(cont.)

Common-mode analysis:

M2M1

M5

VDD

M4M3

Vbias

v1 v2

ISS

vo1vo2

General Circuit

M2M1

M5/2

VDD

M4M3

Vbias

ISS/2

vo1vo2

M5/2

ISS/2vic vic

Common-mode circuit

Common–Mode Analysis for the Diff Amp (an illustration) …(cont.)

Small-signal model for common-mode analysis - gm1vgs1

rds3 vo1

rds1

2rds5

vic

vgs1

1/gm3

For simplification let’s assume that rds1 is large and can be ignored.

vgs1 = vic – 2gm1rds5vgs1

The single ended output voltage, vo1 , as a function of vic is

vo1

vic

= - gm1[rds3 (1/gm3)]

1 + 2gm1rds5

= - (gm1/gm3)

1 + 2gm1rds5

= - (gds5/2gm3)

CMRR = (gm1/2gm3)

(gds5/2gm3)= gm1rds5

Frequency Response of the Differential Amplifier (differential-mode)

After some approximations we will finally get -

Vout(s)

Vin(s)=

gm1

gds2 + gds4

s + 2

First order approximation

Where 2 = [(gds2 + gds4)/ C2]C2 = Cbd2 + Cbd4 + Cgd2 + CL

M2M1

M5

VDD

vG2vG1

vGS1 vGS2

M4M3

Vbias

voutCbd2

Cgd2 CL

Cbd4

Cgd4

Cgd1

Cbd3

Cbd1

Cgs3 + Cgs4

Slew Rate: Maximum output-voltage rate (either positive or negative)

For the differential amplifier with current mirror as loads,

SR = ISS

C

Where C is the total capacitance connectedto the output node.

Note that slew rate can only occur when the differential input signal is large enough to causeISS to flow through only one of the differential input transistors.

For MOSFET differential amplifier SR can be + 2mV or more.

Slew Rate of the Differential Amplifier

Solved Example: Design of a CMOS Differential Amplifier with a Current Mirror

Load DESIGN CONSIDERATIONS:

Constraints:Power SupplyTechnologyTemperature

SpecificationsSmall-signal gainFrequency responseICMRSlew RatePower Dissipation

WHAT IS DESIGN ? The design in most CMOS circuits consists of an architecture represented by a schematic, W/L values of transistors, and dc currents.

Av = gm1Rout

-3dB = 1/RoutCL VIC(max) = VDD – VSG3 + VTN1

VIC(min) = VDS5(sat) + VGS1 = VDS5(sat) + VGS2

SR = ISS/CL

Pdiss = (VDD – VSS) times all dc currents flowing from VDD to VSS

RELATIONSHIPS:

Design: continued

STEPS:1. Choose I5 to satisfy the slew rate knowing CL or the power dissipation.2. Check to see if Rout will satisfy the frequency response, if not change ISS or modify circuit.3. Design W3/L3 (W4/L4) to satisfy the upper ICMR.4. Design W1/L1 (W2/L2) to satisfy the small signal differential gain.5. Design W5/L5 to satisfy the lower ICMR.6. Iterate where necessary.

Specs:VDD = -VSS = 2.5 V, SR > 10V/s (CL = 5pF)f-3dB > 100kHz (CL = 5pF), Av = 100V/V, -1.5V < ICMR < 2V and Pdiss < 1mW.

Given parameters:K’N = 110A/V2, K’P = 50A/V2 , VTN = 0.7 V, VTP = -0.7V, N = 0.04V-1 , P = 0.05V-1.

EXAMPLE:

Design: continuedSolution

1. Slew rate gives, ISS > 50A. Pdiss gives ISS < 200A.

2. f-3dB Rout < 318kFrom here and using Rout=[2/((N + P)ISS], we get ISS > 70A. Let’s pick ISS = 100A.

3. VIC(max) = VDD – VSG3 + VTN1 gives W3/L3 = (W4/L4) = 8

4. Av = 100V/V = gm1Rout W1/L1 = (W2/L2) = 18.4

5. VIC(min) = VSS + VDS5(sat) + VGS1 W5/L5 = 300

6. Since W5/L5 is too large, we should increase W1/L1 to reduce VGS1 and allow a smaller W5/L5. If W1/L1 = 40, then W5/L5 = 9. Note: Here Av increases to 111.1 V/V, which should be Okay.

Thank You