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Differential Amplifiers: Second Stage
Dr. Paul Hasler
Differential Transistor Pairs
MOSFET Diff-Pair BJT Diff-Pair
The bottom transistor (the one with Ibias) sets the total current
The upper two transistors compete for a fraction of this current
BJT Differential Pair Analysis
Analysis of Diff-Pair
Source of Common-Mode Gain
Differential Pair Currents
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.40
0.5
1
1.5
2
2.5
3
Differential input voltage (V)
Outp
ut
curr
ent (n
A)
Iout+Iout
-
Above VT MOSFET Large-Signal
Above VT MOSFET Large-Signal
vID vGS1 vGS2
2iD1
1/2
2iD2
1/2
ISS iD1 iD2
Start with 2 equations
Above VT MOSFET Large-Signal
vID vGS1 vGS2
2iD1
1/2
2iD2
1/2
ISS iD1 iD2
Start with 2 equations
Above VT MOSFET Large-Signal
iD1 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2
iD2 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2vID vGS1 vGS2
2iD1
1/2
2iD2
1/2
ISS iD1 iD2
Start with 2 equations
Above VT MOSFET Large-Signal
iD1 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2
iD2 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2vID vGS1 vGS2
2iD1
1/2
2iD2
1/2
ISS iD1 iD2
Start with 2 equations
gm iD1/vID(VID 0) (ISS/4)1/2
K'1ISSW1
4L1
1/2
Above VT MOSFET Large-Signal
iD1 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2
iD2 ISS2
ISS2
v2
ID
ISS
2v4ID
4I2SS
1/2vID vGS1 vGS2
2iD1
1/2
2iD2
1/2
ISS iD1 iD2
Start with 2 equations
gm iD1/vID(VID 0) (ISS/4)1/2
K'1ISSW1
4L1
1/2
Gain Changes with Bias Current
Common-Mode Input Range
Maximum: Q1 in Forward-active Minimum: Q3 in Forward-active
MOS Common-Mode Input Range
Maximum: M1 in Saturation Minimum: M3 in Saturation
vic(max) = VDD - 0.5ISSRD -vDS1(sat)+VGS1
= VDD - 0.5ISSRD + VT1
vic(min) = VSS+vDS3(sat)+VGS1
Micro-Surgery
Small Signal: BJT Diff-Pair
Common-Mode Circuit
Common-Mode Circuit
An emitter-degenerated amplifier
Gain ~ - Rc / (2 REE)
MOS Common-Mode Circuit
MOS Common-Mode Circuit
An emitter-degenerated amplifier
Gain ~ - RD / (2 Rss)
Differential-Mode Gain
Differential-Mode Gain
Gain = - gm Rc CMRR ~ - 2 gm RE
~ - 2 (IEE/ 2 UT) RE
MOS Differential Mode Circuit
MOS Differential Mode Circuit
Gain = - gm RD CMRR ~ - gm Rss
~ - (Iss/ ( Vgs - VT) ) Rss
Mismatch in Transistor Circuits
Outline
The general approach to analyzing mismatches
Input voltage and current offsets of BJT differential amplifiers
Input voltage offsets of MOS differential amplifiers
Objective
The objective of this presentation is:
1.) Illustrate the method of analyzing mismatches
2.) Analyze the input current and voltage offsets for differential amplifiers
BJT Mismatch Modeling
Mismatch Modeling in MOS
BJT Mismatch Modeling
Differential Amplifiers II
• Review of Basic Differential Pairs
• Above Threshold Differential Amplifiers
• Small-Signal Analysis: Differential and Common mode circuits
• Modeling of Mismatch
