Differential Amp with One Input

Differential Amp with One Input

• Common to implement circuit on an IC with Q1 and Q2 being matcheddevices

• Transistors are biased in the constant current region. Bias isestablished by a constant DC current source Io

• vg has no DC component such that the DC bias values vBE1 and vBE2 areexactly the same. Io is split evenly between Q1 and Q2 causing them tohave the same parameters gm and rπ

• Amplification is performed by Q1. Its emitter is incr5ementallybypassed to ground by the incremental Thevenin resistance lookinginto the emitter of Q2.

ivr

ivr

rvi

rg

bTEST

TESTTEST

THTEST

TEST m

22 2

22

2

1

11

= − = +

= =+

≅

πο

π

π

ο

β

β

( )

• If gm2 is large the value rTH2 will be small andeffectively short node E to ground

iv

r rv

r r

ivr

r r

v i Rvr

Rg R

v

Avv

g R

bIN

TH

IN

bIN

OUT b CIN

Cm C

IN

VOUT

IN

m C

11 2

12

11

2 1

11

1 1 1

2

2 2

2

=+ +

=+ + +

= =

= − = − =−

= =−

π ο π οπ

ο

ππ π

ο οπ

β β β

β β

( ) ( ) ( )

where

• The gain is half that of a single BJT inverter(−gmRC). The gain does not degrade at lowfrequencies as in the case of a shunt capacitor.

Differential Amp with Two Inputs

Differential Amp with Two Inputs

• With a simple relocation of input and output terminals Q2

can function as the inverter and Q1 as the bypass device

• In general input signals may be simultaneously applied toboth devices. Since the small signal models are linear theresponse can be analyzed using superposition

• The diff. amp amplifies the difference component of theinput signals by a large gain factor and multiplies theaverage component by a small gain factor

v v v vv v

v vv v v v v

v

v vv

v v v vv v

v vv

v vv

idm icm

icmidm

icmidm

odm o o ocmo o

o ocmodm

o ocmodm

= − =+

= + =+

+−

=

= −

= − =+

= + = −

1 21 2

11 2 1 2

1

2

1 21 2

1 2

2

2 2 2

2

2

2 2

Similarly

Differential Mode Response

v v t vv v

v v t v v v v

a icma a

a idm a a a

1

2

20

2

= =+ −

=

= − = − − =

( )( )

( ) ( )

• Solving for vo1 and vo2

v v v v i r i r

r r r

i i

ivr

vr

ivr

a a b b

b b

ba a

ba

− − = − = −

= = = == −

= = = −

( )

;

π π π π

ο ο ο π π π

π π π

β β β

1 2 1 1 2 2

1 2 1 2

2 1

1 222

For matched transistors

v i R i Rr

v R

v i R i Rr

v R

o c C b C a C

o c C b C a C

1 1 1

2 2 2

= − = − = −

= − = − =

β β

β β

οο

π

οο

π

• The differentially driven circuit is symmetric aboutits center line. Its base currents and dependentsource currents are always equal and opposite. Noincremental current flows through ro. As a result,the node E remains at incremental ground orvirtual ground.

The single ended gain seen from output 1 to groundis equal to:

Avv

v v v vdm seo

idmidm a− = = − =1

11 2 2

Av R

rv

Rr

g Rdm se

aC

a

C m C− = − = − =

−1 2 2 2

β βοπ ο

π

The differential gain is equal to:

Av v

v

v Rr v R

rg Rdm diff

o o

idm

aC

aC

m C− =−

=− −

= −1 2

2

β βοπ

οπ

Common Mode Response

v v vv v

v

v v v v v

b icm b

b idm

11 2

2 1 2

20

= =+

=

= = − =

i i i i i i

v i r i r i i i

iv

r rr r r

ro b b b b b

b b b o b b b

bb

o

= + + + = +

= + + = == =

=+ +

= =

( ) ( ) ( )

( )

( )

1 1 1 2 2 2 1

1 2

1 2

1 2

2 1

2 1

2 1

β β β

ββ β β

β

ο ο ο

π ο

ο ο ο

π οπ π π

( )

( )

v i RR

r rv v

Avv

vv

Rr r

Av v

vR R

r r

o b CC

ob o

cm seo

icm

o

b

C

o

cm diffo o

icm

C C

o

1 1 2

11 1

1 2

2 1

2 1

2 10

= − =−

+ +=

= = =−

+ +

=−

=− − −

+ +=

−

−

β ββο

ββ

β ββ

οο

π

ο

π ο

ο ο

π ο

( )

( )

• Differential amp amplifies differential signals andrejects (does not amplify) common signals. Thedegree to which common signals are rejected iscalled the Common Mode Rejection Ratio(CMRR)

CMRR =AA

dm

cm

• The CMRR is often measured in decibels

CMRR = 20 10logAA

dm

cm

• For a perfectly balanced diff amp

CMRRA

A

Rrdm diff

cm diff

C−

−

= = ∞βο

π

0

• Real diff amps have typical CMRR of 60 - 100 dB

Input and Output Resistance

• Incremental input resistance is different fordifferential and common mode signals

( )

rv v

iv v

i

ivr

iv

r

rv v

vr

r

rv v

i

v v

i

IN dm

a a

IN dma a

a

IN cm

−

−

−

=−

=−

−

= =−

=− −

=

=+

=+

1 2

1

1 2

2

1 2

1 2

1

1 2

2

2

2 2

where i and i are the signal currents into Q and Q1 2 1 2

π π

π

π

( ) ( )

i iv

r rv v v

r r r

r r R

b

ob

IN cm o

OUT se OUT se C

1 2 1 2

1 2

2 1

2 1

= =+ +

= =

= + +

= =

−

− −

π ο

π ο

β

β

( )

( )

• The differential output resistance can be computedusing the test source method

iv

R Rv

R

rvi

R

TESTTEST

C C

TEST

C

OUT diffTEST

TESTC

=+

=

= =−

2

2

Differential Amp Swing Range

• If an input signal causes any one device to reach alimit to its linear operation, the output voltage (orcurrent) will reach a swing limit

• Consider the following with differential modeexcitation. Note that RC1 and RC2 may havedifferent values. If one transistor could operateindependently VCC ≥ Vo ≥ VE + VSAT, however, Q1

and Q2 operate in tandem such that one transistormay reach cutoff before the other reachessaturation or vice versa

• For the previous circuit for the saturation of Q1

iV V V

R

V

V V

i i

i i I

iV V V

R

i I i

C SATCC E SAT

C

SAT

E BE

C E

C C o

C SATCC E SAT

C

C o C SAT

11

1 2

22

1 2

10 0 7 0133

32

01

0 7

2

10 0 7 015 6

19

01

−

−

−

=− +

=− − +

=

=≅ − = −

≅

+ = =

∴

=− +

=− − +

≅

= − =

( ) [( . ) . ].

.

.

.

( ) [( . ) . ].

.

.

kmA

Assume V

V

mA

Q will reach cutoff before Q reaches saturation

kmA

When Q reaches saturation mA

2 1

2

Ω

Ω

• When Q2 goes into cutoff iC2 = 0 and Q1 willremain in active region with iC1 = Io = 2 mA

v V i R

v V i R

OUT CC C C

OUT CC C C

2 2 2

1 1 1

10 0 10

10 2 34

= − = − =

= − = − =

V V

V mA)(3.3k V( ) .Ω

• When Q2 goes into saturation with iC2 = 1.9 mA,iC2 = 0.1 mA

v

v

OUT

OUT

2

1

10 0 6

10 01 33 9 7

= − = −

= − =

V (1.9 mA)(5.6 k V

V mA) k V

Ω

Ω

) .

( . ( . ) .

For the basic BJT diff amp of the previous page

A

CMRR dB

Diff Swing V

r

r

Power Supply V

dm SE

IN diff

OUT SE

−

−

−

=

>= ±

>

<= ±

100

60

3

1

1

10

.

k

k

Ω

Ω

Large Signal Performance

dvdv

g RAOUT

idm

m Cdm se

1 112

=−

= −

Power Amplification Stages• In many designs an amplifier is required to deliver large amounts of

power to a passive load. The power may be a large current to a smallresistance or a large voltage to a moderate resistance (impedance).

• Using a linear amplifier the power wasted in the active device iscomparable to the power delivered to the load. Devices in the outputstage must be capable of dissipating this excess power.

• Alternative configurations offer increased efficiency at the expense oftrue linear operation.

Complementary Pair (Class B) Output

• When an amplifier is required to deliver large load currents it isdesirable to bias the voltage of its output terminal near ground. Thisminimizes the bias power dissipated in both the load element and theactive devices of the output stage.

Linearly Biased (Class A) Output

Minimally Biased (Class AB) Output