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DFT Technologies for High-Quality Low-Cost Manufacturing Tests. Yuval Snir JTAG 2006. Agenda. Background – Two major fault models Problem – Exploiting a given tester memory Main goal – Two effective implementation solutions. Background. - PowerPoint PPT Presentation
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DFT Technologies for High-DFT Technologies for High-Quality Low-Cost Quality Low-Cost
Manufacturing TestsManufacturing Tests
DFT Technologies for High-DFT Technologies for High-Quality Low-Cost Quality Low-Cost
Manufacturing TestsManufacturing Tests
Yuval SnirYuval Snir
JTAG 2006JTAG 2006
Yuval SnirYuval Snir
JTAG 2006JTAG 2006
AgendaAgendaAgendaAgenda
Background – Two major fault modelsBackground – Two major fault models Problem – Exploiting a given tester Problem – Exploiting a given tester
memorymemory Main goal – Two effective implementation Main goal – Two effective implementation
solutionssolutions
BackgroundBackgroundBackgroundBackground
The Shrinkage of semiconductor The Shrinkage of semiconductor devices brought a new distribution of devices brought a new distribution of defectsdefects
Timing defects have become more Timing defects have become more significant (at least 2% of all defects)significant (at least 2% of all defects)
BackgroundBackgroundBackgroundBackground For 130 nm fabricationFor 130 nm fabrication Of yield 70%Of yield 70% No statistical faultsNo statistical faults Defect rate will be 0.7%Defect rate will be 0.7%
7000 defective devices7000 defective devices un detected per millionun detected per million (DPM)(DPM)
Fault ModelsFault ModelsFault ModelsFault Models
Stuck-at fault-Stuck-at fault-model:model:
the most popular fault the most popular fault model used in practice model used in practice
a line whose status is a line whose status is stuck at a given value stuck at a given value (normally 0 or 1). (normally 0 or 1).
aa bb cc cc cc
00 00 00 00 00
00 11 00 00 00
11 00 00 00 0->10->1
11 11 11 1->01->0 11
s@0 -b
s@1-btrue
fault Modelsfault Modelsfault Modelsfault Models
At-speed fault model:At-speed fault model: Example:Example:
Initialization Initialization
B=1B=1
Opposite valueOpposite value
Propagates from Propagates from
B to CB to C
The ProblemThe ProblemThe ProblemThe Problem Desired fast & low cost technologies Desired fast & low cost technologies
tests tests Transition pattern set is 3-5 bigger thenTransition pattern set is 3-5 bigger then
stuck-at pattern setstuck-at pattern set Sometimes there isn’t enough room on Sometimes there isn’t enough room on
the tester memory for both pattern sets.the tester memory for both pattern sets. Yields expensive tester reloads of the Yields expensive tester reloads of the
memory.memory.
1.1. Effective Merging At-Speed with Stuck-At Effective Merging At-Speed with Stuck-At
PatternsPatterns
2.2. EDT – Embedded Deterministic Test EDT – Embedded Deterministic Test
solutionssolutionssolutionssolutions
Merging At-Speed with Stuck-Merging At-Speed with Stuck-At Patterns SetsAt Patterns Sets
Merging At-Speed with Stuck-Merging At-Speed with Stuck-At Patterns SetsAt Patterns Sets
The TDF (Transition delay fault) patterns The TDF (Transition delay fault) patterns also detect a significant percentage of also detect a significant percentage of stuck-at faultsstuck-at faults
Truncate TDF patterns Truncate TDF patterns
Merging Patterns – Example Merging Patterns – Example DesignDesign
Merging Patterns – Example Merging Patterns – Example DesignDesign
Characteristic of the design
The tester can hold up to 10,000 test pattern
The highest priority – best possible coverage for stack@
One TDF pattern set for each clock domain and one
For cross clock domain.
Design demands:
Merging PatternsMerging PatternsMerging PatternsMerging Patterns
Test generation results before optimization
Due to the typically slow operation of the tester
The TDF test coverage is only 85.14%.
Merging PatternsMerging PatternsMerging PatternsMerging Patterns
Test generation results before truncation & optimization
Merging PatternsMerging PatternsMerging PatternsMerging Patterns
Flow for generating higher coverage:
Arrange TDF test patterns from most significant to least
Truncate TDF patterns ( 90% of the overall achievable)
Fault grade the truncated TDF patterns for SAF
Generate top-off SAF pattern set
Merging PatternsMerging PatternsMerging PatternsMerging Patterns
Test generation results after truncation & optimization
Merging PatternsMerging PatternsMerging PatternsMerging Patterns
Test generation methodology comparison
EDT-Embedded deterministic EDT-Embedded deterministic testtest
EDT-Embedded deterministic EDT-Embedded deterministic testtest
Two additional blocks to the traditional ATPG:
Decompressor Compactor
EDT-Embedded deterministic EDT-Embedded deterministic testtest
EDT-Embedded deterministic EDT-Embedded deterministic testtest
The blocks are in the scan chain pathThe blocks are in the scan chain path
System core isn’t affectedSystem core isn’t affected
Immunity for logic changesImmunity for logic changes
Tester see the original designTester see the original design
EDT-Embedded deterministic EDT-Embedded deterministic testtest
EDT-Embedded deterministic EDT-Embedded deterministic testtest
The decompressor:
Only 1% - 5% of scan cells get specified
EDT – compression is done prior to random fill
Shorter Chains - fewer cycles and data
Less costly tester can be used
Attributes: Extremely high encoding capacity, low silicon area And high speed of operation
EDT-Embedded deterministic EDT-Embedded deterministic testtest
EDT-Embedded deterministic EDT-Embedded deterministic testtest
The compactor:
Ability to handle any number of X values
Support for production diagnostics directly from the compressed patterns
EDT-Embedded deterministic EDT-Embedded deterministic testtest
EDT-Embedded deterministic EDT-Embedded deterministic testtest
example:
Same coverage
Effective reduction of 100X in data volume and test time
One ATPG scan pattern occupies 11292 vectors One EDT scan pattern occupies 80 vectors only!
I have to go nowI have to go now