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7/24/2019 Device Scaling
1/19
Device Scaling: CMOS
Dipankar Pal,
Dept. of EEE & EI,
BITS-Pilani, K. K. Birla Goa Camp!
7/24/2019 Device Scaling
2/19
Scaling of "#S concern! !$!tematic re%ction of
%imen!ion! !pporte% $ availale tec'nolog$.
Features:
Geometric ratio! are pre!erve%.
Proportional !caling re!lt! in a re%ction of !ilicon area.
Increa!e! overall fnctional %en!it$ of c'ip.
Total po(er %i!!ipation i! re%ce% in Constant Field !caling)
increa!e% inConstant Voltage !caling
MOSFET IN SMALL-GEOMETRY
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
3/19
Trend in Scaling of technology
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
*ear + +/ + ++ +0 + +/ +
Feature
Size !#
$.% .' .$ .( (.) (.% (.*% (.$%
A+erage d-nscaling fr a generatin t ne/t is 0y a factr S: 1 .$ t .%#2 3a44ense+ery $5* years . 6day (.() ! r )n# tec3nlgy is cn and -idely used.
Scaling of a typical MOSFET by a factor of S
7/24/2019 Device Scaling
4/19
Method of Scaling
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Constant Field Scaling (Full Scaling)
To scale by a constant factor S (> 1):
All hori!ontal and "ertical di#enion of
di"ided by S$
S%pplie caled by a#e factor &S'
The e(tent of caling &S' deter#ined by
technology and #ini#%# feat%re i!e$
7/24/2019 Device Scaling
5/19
Components after Scaling (Quantitative)
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
( ) ( )
22
'''
2
2
2'''
'
..1
.
,
.
)(.
1.
2
..
2)(
S
PVI
SVIP
Now
VIP
S
satIVV
S
kSVV
ksatI
DSDDSD
DSD
DTGS
nTGS
nD
===
=
===( )[ ]
( )[ ]S
linIVVVV
S
kS
VVVVk
linI
CSt
St
C
DDSDSTGS
n
DSDSTGSn
D
ox
ox
ox
ox
oxox
)(..2.
1.
2
.
..2.2
)(
..
2
2
2'''''
'
'
'
==
=
===
7/24/2019 Device Scaling
6/19
Method of Scaling
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Constant Voltage Scaling
To scale by a constant factor S (> 1):
All horizontal and vertical dimensions divided by S.
Extent of scaling (S) determined by technology and minimum feature size.
Sulies !et unchanged.
"oing densities increased by a factor S#
7/24/2019 Device Scaling
7/19
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Components after Scaling (Quantitative)
( )[ ]
( )[ ] )(...2.2
.
..2.2
)(
2
2''''
'
'
linISVVVVkS
VVVVk
linI
DDSDSTGS
n
DSDSTGSn
D
==
=
( ) ( )
PSVISVIP
satISVVkS
VVk
satI
DSDDSD
DTGSn
TGSn
D
....
)(..2
..
2)(
'''
22'''
'
===
===
7/24/2019 Device Scaling
8/19
Shortco#ing of Scaling - I
$radual %hannel Aroximation ($%A) no more holds.
&f channel length (') on the order of "rain Source deletion
region (xd" xdS) or deth of "rain Source*+unction(x+) thedevice is called short channel device.
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
9/19
Short )hannel Effect
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Li#itation on electron drift characteritic
Red%ction in threhold "oltage
Electron *rift )haracteritic
+$ Increaed channel electric field &Ey , +. /0c#' at%rate drift
"elocity &"d&at' , +1 c#0'$ E"en 23 "d&at' at%rate I*4
5%adratic f%nction of /GS no #ore "alid$
6$ )arrier "elocity beco#e a f%nction of nor#al &"ertical' co#ponent E($
Scattering of %rface charge lead to colliion7 %rface #obility
drop$
( ) ( )TGS
n
cGS
Siox
ox
n
x
nn
VVyVV
t
Eeff
+
+
=+
=
1)(.
.1
.1)( 000
7/24/2019 Device Scaling
10/19
Red%ction in threhold "oltage+$ Long-channel e(preion of /T no #ore "alid$
6$ *epletion region created by *rain &So%rce'-pn 8%nction 9ith b%l: to be
conidered$
;$ Shape of Gate-ind%ced channel i trape!oid ¬ rectang%lar'
Short )hannel Effect
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
11/19
Estimation of VTfor Short Channel device
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
BOQ
,here #nd term is error term due to charge
difference bet,een rectangular and traezoidal deletion region.
The traezoidal bul! deletion channel*region contains charge given by-
The +unction deletion region deths are give by and
,here +unction built*in voltage is
rom the cross*sectional vie, of the +unction deletion layer and deth of the channel
into the bul! ,e can ,rite- ,hich leads to-
and
000 )( TTT VVelshortchannV =
FASiDS
BO NqL
LLQ
+= 2....2.
21
( )DSA
SidD V
Nq
x += 0.
.
.2
0.
.
.2
A
SidS
Nq
x =
=
20
.ln.
i
AD
n
NN
q
kT
( ) ( )222 DjdmdDj Lxxxx ++=+
+ 1
21.
j
dSjS
x
xxL
+ 1
21.
j
dDjD
x
xxL
7/24/2019 Device Scaling
12/19
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Finally fro# and 9e can get the charge
difference in the trape!oidal channel 9hich lead to the
error ter# of threhold "oltage at *rain-So%rce biaia< 0TV
7/24/2019 Device Scaling
13/19
Shortco#ing of Scaling - II
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
In Narrow Channel, W is on the order of maximum depletion regionthickness !dm"# Effect: Increase in threshold voltage
7/24/2019 Device Scaling
14/19
/T IN NARRO? )hannel
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
The Gate-area o"erlap on the large FO@-area in thefringe$
An additional hallo9 depletion region for#$
For large ?7 thi i negligible$ >%t for co#parable ?&and thin to('7 /T goe %p d%e to thi depletion charge$
beco#e 9here
for an e#pirical para#eter dependent on hape of fringe gi"en by for hape of 5%arter-circ%lar arc$
W
xNq
CV dm
FASiox
T
.22.1
0
=
( )channelnarrowVT 0 00 TT VV +
2
=
7/24/2019 Device Scaling
15/19
Oth r limitations of small g om try
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
Two$dimensional electric field vector controls $ cannot %e decoupled#
Complications& e#g#, for V'S VT, potential %arrier controlled %oth %( V'S
and V)S # Increase in V)Slowers the %arrier#
This )rain Induced *arrier +owering )I*+" leads to su%$threshold I)#
I)caused %( )I*+ is expressed as&
where xc
is the sub-threshold channel depth, Dn
is the electron diffusion
coefficientLB
is the length of the barrier andris a reference potential.
( )( )
kT
VBVAq
kT
q
B
cn
D
DSGSr
eeL
nWxqDldsubthreshoI
..
0 ..
+
7/24/2019 Device Scaling
16/19
unch !hrough
or large /"S deletions region of drain extends
to,ards source.
or small geometry the t,o deletion regions mayeven merge.
This is called 0unch Through2 ,hich can damage thedevice
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
17/19
I" #O$ES and O%id &r a'(do)n
&n ractice all dimensions cannot be reduceduniformly.
&f tox e.g. is reduced by S3 for very small geometrylocalized non*uniform oxide gro,th called 0in*4oles2
develo.
Another roblem ,ith very thin tox is 05xide
6rea!do,n2
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
18/19
#ot carri r g n ration
%onstant voltage increased doing and smallgeometry combine to increase electric field.
&ncreased electric field generates electrons and holesat high !inetic energy called 04ot %arrier2.
04ot %arriers2 in+ected into gate*oxide damages oxide7
interface charge distribution.
&*/ characteristics change
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al
7/24/2019 Device Scaling
19/19
At high /*S and in #all geo#etrie the effect iober"ed$
*a#age i locali!ed on drain end$
Re%lt i red%ction of I* and general
degradation o"er a ti#e$
* piction of #ot carri r *+,+-E
Ref: "CMOS Digital Integrated Circuits:
Analysis & Design", Kang, S. et al