Detailed Routing: New Challenges

2

• Manufacturers use different wire widths Vias connecting wires of different widths

− block additional routing resources on the layer with the smaller wire pitch

Detailed Routing:New challenges

3

Detailed Routing:New challenges

130 nm 90 nm 65 nm 45 nm 32 nm

M1M2M3M4M5B1B2

M1M2M3M4B1B2B3

E1

E2

M1M2M3M4

B1B2

C1C2

B3

E1

U1

U2

M1M2M3M4

B1

B2

B3

E1

E2

M5

W1

W2

M1M2

M4M5M6

M3

Representative layer stacks for 130 nm - 32 nm technology nodes

©20

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Spr

inge

r V

erla

g

4

• Manufacturing yield: a key concern in detailed routing Redundant vias and wiring segments as backups

(via doubling and non-tree routing) Manufacturability constraints (design rules) become more

restrictive complicate detailed routing

− Example: design rules specify minimum allowed spacing between wires and vias depending on their widths and proximity to wire corners.

− Example: Recent spacing rules take into account multiple neighboring polygons.

Detailed Routing:New challenges

Via Doubling

5

6

• Detailed routers must account for manufacturing rules and the impact of manufacturing faults Via defects/performance degradation (from

misalignments):

− Via doubling during or after detailed routing − Area penalty

Interconnect defects:

− Non-tree routing: Add redundant wires to already routed nets (postprocess)

Antenna-induced defects:

Detailed Routing:New challenges

7

Antenna Effect

• Recent DFM Issue Long metal lines and vias introduce antenna violations. Conductor layers fabricated from lowest layer to

highest layer. The etch process builds up the electrical charges on

metal layers. These charges cause a high voltage spike, which may

destroy the gates connected to the metals.

8

Antenna Effect

A long line connected to gate only can cause failure Not a problem after chip is complete since every net

has at least one driver

Driver (diffusion) Load (poly)

M1

M2

But, we can have a problem during manufacturing Here is the same net after M1 is built, but not yet

M2

Driver (diffusion) Load (poly)

M1

9

Antenna Effect

Sink 1Diffusion Sink 2

Antenna violation

[©Wu]

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Antenna Rules Violations to the above antenna rules in every metal

layer have to be fixed before the chip tapeout. Each metal layer may have various upper limit rules

based on the process specifications. 0.18 (0.13) um technology: the maximum length of an

“antenna” wire ≈ 500 um (20 um).

Process-Induced Damage Rules (otherwise known as “Antenna Rules”)-

General Requirements.

http://www.mosis.org/Technical/Designrules/guidelines.html#antenna

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Antenna Avoidance1. Jumper Insertion:

Router inserts jumpers for long metals from low-level metals to upper-level layers.

− The jump cuts the long metals in the low-level layers to disconnected pieces.

− based on the fact that wire segments on top routing layers are normally fabricated at the end

Diffusion Gate

Diffusion Gate

Jumper insertion

Antenna violation

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Antenna Avoidance1. Jumper Insertion:• Disadvantage:

jumpers introduce extra vias − Degrade both manufacturing yield and circuit timing

performance

Jia Wang, Hai Zhou, “Optimal Jumper Insertion for

Antenna Avoidance under Ratio Upper-Bound,” DAC 2006.

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Antenna Avoidance3. Layer Assignment:

• Reduce antenna length by layer assignment.

Di Wu, Jiang Hu and Rabi Mahapatra, “Coupling Aware Timing

Optimization and Antenna Avoidance in Layer Assignment,” ISPD 2005.

Diffusion Gate

Diffusion Gate

Diffusion Gate

Jumper insertion

Antenna violation

Layer assignment