Design of a Current Regulator with ExtendedBandwidth for Servo Motor Drive

Anno Yoo*, Young-Doo Yoon*, Seung-Ki Sul*, Masaki Hisatune**, Shinya Morimoto**

and Kozo Ide*** School of Electrical Engineering and Computer Science, Seoul National University, Korea

* * Yaskawa Electric Corporation, Japan

Abstract-To increase the productivity of the manufacturingprocess, the high bandwidth of the current regulationshould be achieved. The bandwidth of the current regulatoris dependent on the switching frequency and digital delay.The limited switching frequency is inevitable to reduce theswitching loss due to excessive switching frequency. Also,the digital delay is inherent problem where the DigitalSignal Processor (microcontroller) and PWM are used. Thispaper proposes the novel current regulation strategy toenhance the performance of the current regulation byreducing the digital delay which is the sum of the executiontime and PWM delay and modifying the voltage reference.The proposed strategy is robust to the parameter andreference variation. Experimental results are shown toverify the effectiveness of the proposed method.

Index Terms--Digital delay, Current regulation, Voltagereference update, Bandwidth

I. INTRODUCTION

To increase the productivity of the manufacturingprocess, the bandwidth of the servo drive which is basedon that of the current regulation is getting higher. In thecurrent regulation, the fast current response which resultsin fast rising time and the accurate current regulation playa prominent role to reduce the current ripple which isdirectly related to the losses of the PWM inverter andservo machine.

There are two major limiting factors in the currentregulation, switching frequency and digital delay whichmeans the sum of algorithm execution time and PWMdelay. In the case of above a few hundreds watts of servodrive system, conventionally its switching frequency islimited up to around 10 kHz due to avoiding excessiveswitching losses. Because of the limited switchingfrequency, the bandwidth of the current regulator can notbe extended and the restricted bandwidth is directlyrelated to the current response. There have been severalpreferred approaches that enhance the current regulationaccuracy under limited switching frequency. The internalmodel controller (IMC) has low complexity [1]. Thedynamic decoupling current regulator and the complexvector current regulator are robust to the variation of theinductance of the motor [2, 3]. And the current predictionand deadbeat current regulator can provide highestbandwidth [4]. These conventional methods, however,still have a digital delay problem which is inherentproblem where the Digital Signal Processor (DSP) ormicrocontroller is utilized. Also, many researchers have

tried to reduce the digital delay to enhance theperformance of the current regulator [5, 6]. In [6], thecurrent regulator has been implemented with hardware.This method can reduce the algorithm execution timepredominantly. It is, however, quite time-consuming andhas low flexibility.

This paper presents a novel current regulation strategywhich reduces the digital execution delays up to the 0.05or 0.1 times of switching period, and it modifies thevoltage reference to extend the bandwidth of the currentregulator. It enables fast current response and accuratecurrent regulation. Moreover, its performance is robust tothe parameter and the reference variation. Theexperimental results for the Surface Mounted PermanentMagnet Synchronous Machine (SMPMSM) are shown toverify the proposed method.

II. ANALYSIS OF CONVENTIONAL CURRENT REGULATION

In this section, the timing diagrams are analyzed toclarify the time delay of the conventional design strategyof the current regulator. Fig. 1 shows the timing diagramof the conventional current regulation of PWM inverterdriven servo system in the discrete or digital domain witha PWM carrier.

To reduce the current ripple, it is prerequisite tosample the average value of the current in a samplingperiod [7-9]. If the current is sampled at peak or valley ofPWM carrier, the average value can be obtained underthe condition of symmetry PWM gating signals. Also,this kind of sampling increases the immunity of thecurrent measurement against switching noise on feedbackcurrent.

If the current sampling executes at peak or valley ofthe carrier, only one time in one switching period, thetotal delay which is the sum of the algorithm executiontime and PWM delay is 1.5 times of switchingperiod,Tsw . In Fig. 1 (a), the calculation of algorithmswhich are based on [n-I] current sampling spends the oneswitching time and the voltage reference update which isoutput of the current regulator takes 0.5 times ofswitching period on the average. Therefore, the totaldelay ofthe current regulation which is based on the [n-I]current sampling is 1.5 times of switching period. If thecurrent sampling executes at peak and valley of thecarrier, two times in one switching period, the delaywould be reduced to 0.75 times of switching period, andit is half of the previous case. In Fig. 1 (b), the algorithm

1-4244-0844-X/07/$20.00 ©2007 IEEE. 1 308

If

Fig. l(a). Current sampling at peak or valley of carrier and delay

Calculation Of,currentMb

awithlAj saimpling .

Tsw p

point [n11] poin n plgph c lcu'ton

Fig. 1(c). Current sampling at peak and valley of carrier,ancurenty

|~ ~~ Wberi",+[[

prdL;ti- n and delay

execution time is0. tie Nfsicigpro n h

vla rernhu s s t,

Cttrrent Cbasednt Ctlrrent

sampling sampling samplingpoint [n-11 point [n] point [n+11

Fig.ae(d). Current sampling at peak and valley of carrier, canu ensavedcanedelaymy b

eeuintmis05tmsofswitching period.naign1c)thetoadeyisnlreae otevoltage reference updatesed .2Inthies caste,however,n therlineait ofthe referaenc variation and theacedcurteooprmther idffentifiatidon teshouldedguaraenteedfornedttheexatturent prseditin Otherwxcuise, thmerespnsbeofated curreth reglatomayb revueal unacptablhe r5ippes.

Figat2 show thevlaequivalenticuitdofthe.IthsMPMsM.

Thoweve,q-axissaritovoltaeoefeSMPMS inr synchron

rotuatin farametarewittentiiasinsol egaate

wherg frearewrit a

vr ~ f/=Rs=r+ Arq_wee d, +qsfd 4q

Fig. 2. Equivalent circuit of SMPMSM

The flux linkage induced by the permanent magnet andstator currents are expressed as

Ld, 7FLs +Lmd 1ds +FLm if (2).0Iqsj L 0 L +Lmq jr JL0j

From the equation (1) and (2), d, q-axis voltageequation can be rewritten as follows

d r

Vdqs = R dqs + Ls dqsjPr~~Rjr dt rq (3)

where Ls = LIS +Lmd =L,S+ Lmq and I is constant.

Fig.3 describes the timing diagram of the proposedcurrent regulation strategy which reduces the digitalexecution time and PWM delay as short as possible. Inthis point of view, the proposed current regulator can beapproximated closely to their analog counterpart.

In the proposed strategy, the current sampling pointlocates at peak and valley of PWM carrier. An analogLow Pass Filter (LPF) is essential to eliminate theswitching noise on the sampled current, and the delaytime due to the analog filter cannot be reduced below acertain value. The execution time for current regulationalgorithm is the calculation time to generate the voltagereference from synchronous frame Proportional andIntegral (PI) current regulator which is robust to theparameter variation.

In Fig.3, the proposed current regulator can reduce thetotal digital execution delay down to 0.05 or 0.1 times ofswitching period. When 2nd current regulation does notrun, the execution delay is 0.05 times of switching periodand when the 2nd current regulation runs, the executiondelay is 0.1 times of switching period. Although theexecution delay increases when 2nd current regulationruns, the voltage references which are the results of the2nd current regulation are more accurate, because the 2ndcurrent regulation updates the information of the currentreference once more. Also, it seems that the proposedcurrent regulator doesn't utilize the DC-link voltagemaximally because of the analog filter delay and thealgorithm execution delay in every rising / falling carrier.The servo motor driven by PWM inverter, however, hassmall back-EMF especially at low speed.

1309

LPFdelay

2nd currentregulatio

IF

1 st currentregulation0. 15Tsw

Tsw

PWM by 1st current regulation

PWM by 2ndi currefit regulationFig. 3. Timing diagram of proposed current regulation

Hence, the voltage references locate near the center of thecarrier, and the execution time delays in the proposedcurrent regulators doesn't influence seriously on currentregulation performance in the sense of limited outputvoltage. In this point, the execution time delay doesn'tmatter wherever the effective voltage vector can locatewithin the rest oftime after algorithm.

In this paper, the time delay due to the analog LPF isset as 0.05Tsw and the execution time for each currentregulation is 0.05Tsw . The voltage references are updatedimmediately after the each current regulation. It meansthat the total delay time of the proposed current strategyis 0.25 TSw which represents the sum of the analog filterdelay, digital execution time and PWM delay on theaverage, whether 2nd current regulation runs or not. The0.25 TSW delay is the minimum delay time in the PWMinverter driven servo system, because it come from thePWM itself. The digital delay of the proposed strategy isequal to the conventional current regulator using theprediction method which is mentioned at the previouschapter. The proposed strategy, however, does not rely onthe prediction, and it is robust to the parameter andreference variations.

Fig.4 shows the block diagram of the proposed currentregulation. In the equation (3) and Fig.4, the last term ofthe right side (jrCOiqs ) which is defined as the back-EMF can be cancelled by the cross coupling decouplingstrategy as follows when the inductance is knownexactly.

V4r f =Jfo)rs dqs (4)

where 'dqs : estimated d, q-axis flux

The cross coupling decoupling strategy is done perfectly,

SMPMSM is equal to R-L load.The proposed current regulator executes the current

regulation algorithm twice in one sampling period. InFig.4, the I't current regulation runs at the rising instantof the pulse generator from the digital controller and the2nd current regulation is generated at the falling instant.The pulse generator whose frequency is equal to thecurrent sampling rate is synchronized with the PWMcarrier. In the I't current regulation, the sampled realcurrents and the sampled current reference are used as itsfeedback signal and reference signals respectively. In the2nd current regulation, the voltage references for PWMblock are updated again to enhance the current regulationperformance. That is, the difference between the I'tcurrent reference and the 2nd sampled current referencesare used as PI regulators' two input signals, and then theresults are multiplied by the specific gain k. Finally, theyare added to the output voltages of the 1St currentregulators. The overall procedure to derive the voltagereference for PWM block is shown in (5).

vr +p K,J(. r* riq7

( ( K)~ (r* .*Vdqs =vs+k(K + ) \dqs s (5)

=rP+ K1,[Q -i5)+ k(i ~i5)= (Kp + )[(dqs-ds ) (dqs idqs)]

Kp + K,I(kir** (k I)i'* irq)

whereVdrqs Voltage reference after It current regulation.

r** Voltage reference after 2nd current regulation.

idrqs Sampled current reference in 1st current regulation.

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mi-I

I< ''d-Ift

SMPMSM

pulse

Fig. 4. Block diagram of proposed current regulator

rdq : Sampled current reference in 2nd current regulation.r Sampled real current.

In (5), the specific gain k is 8 when the currentreference changes linearly. And it is 4 or 6 in case ofsinusoidal reference.

If the 2nd current regulation doesn't run, the currentreference is 1r* . Otherwise, the current reference should

dqs

be changed by the difference of the current reference. In(5), k 152* - (k - 1)i5` is the modified current referencewhich is generated by the 2nd current regulation.

In the proposed method, Space Vector PWM(SVPWM) using the offset voltage is implemented for thePWM strategy. The SVPWM using the offset voltage hasadvantage which can move the effective voltage vector atthe center of PWM carrier. In the proposed method, thevoltage references can shift between the end of thealgorithm and the next current sampling. The 2nd currentregulation does not run at the following condition.

Vmax-Vmln 23 VDC (6)5

he Vmax=max (vjs,IbXC)T,in = min V,s X VbsXVC)inV'

V : Output of the 1 st current regulationIf the above condition is satisfied, the 2nd voltage

references Vdq* are ignored. In this case, the effective

voltage vector cannot be located on the center of carrier,

due to the large voltage reference.The gain of PI regulator can be set from the following

equation (7) - (9). Suppose that current regulation is welldone when the current reference is ij* and at the next

instant, the current error, A 15qS is generated by the changeof the current reference, the equation (7) should besatisfied for the current regulation.

KP AIi",+ KIfAIi" dt=

s (i- +A idqs ) Ldqs At

(7)

whereA

KP =LS Proportional gain of current regulator.A

KI = RSc Integral gain of current regulator.A

LS Estimated stator inductance.A

RS Estimated stator resistance.

6cc : Bandwidth of current regulator.In the equation (7), At is the time between the end of

the 1 st current regulation and the following currentsampling time.

In the proposed strategy, if the equation (7) is satisfied,the current regulator has similar dynamics with thedeadbeat regulator in which the current regulation is doneat next instant. However, the proposed method which hasthe synchronous frame PI regulator is more robust to the

1311

*r*dqs

[A]2 1/ ........................ .; ;. ;;::. .; ;.; .; ;; .; ;; .; ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0n DF...... 2(ms]'1

Fig. 5(a). Current regulation of the proposed current regulator(Frequency: 1 kHz, 60% offset and 10% amplitude ofrated current )

0.5

0

M: -0.5a)

-1=cc> -1.5

-2.5Frequency[Hz]

[A]2 X

<1--

0 lI[ms]

Fig. 5(b). Current regulation of the proposed current regulator(Frequency: 3 kHz, 60% offset and 10% amplitude ofrated current )

)000

to

¢

Frequency[Hz]Fig. 6. Bode plot of the proposed current regulator(60% offset and 10% amplitude ofrated current )

parameter variation than the deadbeat regulator is.In the transient, the proportional gain at the left term of

equation (7) which is the output of the synchronous framePI current regulator is dominant. And at the right sideterm which is the electrical model of the SMPMSM, thevoltage drop across the resistance can be ignored. Hence,equation (8) can be obtained.

KP Aj5qs + KI |fI5qS dt PKP Aidqs

LASdqs +RS (i- +Ai-)LA-LS (8)

From the equation (7) and (8), the equation (9) can beacquired.

A Ai"LS C Air = L dqsscdcsp At

0cc LS 1

A Ats

In (9), when the estimated inductance matches with thereal value, acc is 25000 [rad / s].

IV. EXPERIMENTAL RESULTS

In conventional servo drive, the position and speedcontrol loops are executed in lower sampling ratecompared to the sampling rate of current control loop.Hence, the output of speed control loop, that is currentreference, is updated in sampling rate of the speed controlloop. But in some case, the current reference can bedirectly transferred to servo drive in analog form from a

host controller, where position and speed control iscarried out. In this study to show the performance of thecurrent regulator clearly, the latter case has beenconsidered. Hence it is assumed that the reference of thecurrent control loop is given in analog form.

In this paper, Bode plot is used for evaluating theperformance of the current regulation. Generally, thecurrent regulation loop is considered as the ISt LPF,therefore, the margin of the regulation is -3 [dB] in themagnitude and -45 [deg] in the phase. Bode plot isdescribed by FFT analyzer.

The machine parameters are shown in Table 1. Fig.5(a) shows experimental results which depict the q-axiscurrent reference and real q-axis current. The q-axiscurrent reference is the 1 kHz sinusoidal wave that has60% offset and 10% amplitude of the rated current. InFig.5 (b), the frequency of the reference current ischanged to 3 kHz. Fig.6 shows Bode plot of the proposedcurrent regulator under the same condition as the Fig.5.At 3160 Hz, the magnitude is -0.52[dB] and the phasedelay is equal to -45[deg].

Fig.7 shows the experimental results which has 10%offset and 10% amplitude of the rated current. In Fig.7 (a),the frequency of the reference current is 1 kHz and inFig.7 (b), it is 3 kHz. Fig.8 shows the Bode plot of theproposed current regulator under the same condition asthe Fig. 7. At 3630 Hz, the magnitude is -0.77[dB] andthe phase delay is -45[deg].

Fig.9 shows the step response, the q-axis currentreference is 20% of the rated current. Fig.9 (a) depicts theq-axis current reference and q-axis real current. Fig.9 (b)

1312

LN++N++N

irr .i

[A]I [A]2

axis rel urrent

Fig. 7(a). Current regulation of the proposed current regulator(Frequency I1kHz, 10% offset and 10% amplitude of rated current)

0 Ims]

q7Axis real 7urientl

Fig. 7(b). Current regulation of the proposed current regulator(Frequency: 3kHz, 10% offset and 10% amplitude of rated current)

00

- -O-e

0 -1

-,1

-45bD

-Cd2 -90bD

-135

-180Frequency[Hz] Frequency[lIz]

Fig. 8. Bode plot of the proposed current regulator(10% offset and 10% amplitude ofrated current )

[Al0.8

0.4 L 0.4

0.25 I0.5 [ms]

Fig. 9(a). Current regulation ofthe proposed current regulator( Step input: 20% ofrated current, real current )

[A]4

2

0

0

200

o0.

0.32; . m'I"'~~~~~[Ms0

sampl4d is olt;ge reference

Fig. 9(b). Current regulation of the proposed current regulator( Step input: 20% ofrated current, sampled current )

[A]4

2

0

......I.............................

0 5

rr"ntre e

Fig. 10(a). Current regulation of the proposed current regulator( Step input: rated current, real current )

IV]

i.0

--------- 1MME-

D

0

0.25 .5 [Ms]0

sa] un ed 9-axis oltage. reference

Fig. 10(b). Current regulation of the proposed current regulator

(Step input: rated current, sampled current)

1313

[Al0.8

IV]~400

0 -- -.,L L.- -L - -1

W77 77-.T7

demonstrates the sampled q-axis current reference andsampled q-axis feedback current. Only within 2 steps, q-axis real current settles down.

Fig. 10 shows the step response of the rated current.Fig. 10 (a) shows the q-axis current reference and q-axisreal current. Fig. 10 (b) depicts the sampled q-axis currentreference and the sampled q-axis current. Due to the lackof the voltage margin, the current settles down within 4steps.

Drives," IEEE TranslIndustry Application, vol. 34,No.5,Sep 1998.

[8] S.H.Song, J.W.Choi, and S.K.Sul, "Current Measurementof Digital Field Oriented Control," inConfRec. of IAS'96,pp. 334-338, 1996.

[9] Y.C.Son, S.H.Song, and S.K.Sul, "Analysis andCompensation of Current Sampling Error in AC Drivewith Discontinuous PWM," IEEE-APEC, vol. 2, No.5, pp.795-799, Mar 1999.

TABLE ISMPMSM PARAMETERS

Quantity Value [Unit]

Rated output 200 [W]

Rated torque 0.637 [N/m]

Rated current 2.69 [A]

Rated speed 3000 [r/min]

Stator resistance 3.54 [Q]Stator inductance 8.46[mH]

V. CONCLUSIONS

The proposed current regulation reduces the digitaldelays and uses the voltage reference update method. Ithas two current regulation loops in the one switchingperiod, and at each regulation loop PI regulator runstwice to regulate the sampled current and to update thecurrent reference variation. The bandwidth of theproposed current regulator can be extended almost twotimes of that of the conventional regulator. Experimentalresults show the performance of the proposed strategy.And it can be easily applied to the modem servo drivesystem.

REFERENCES

[1] L.Harnefors, and H.P.Nee, "Model-Based Current Controlof AC Machines Using the Internal Model ControlMethod," IEEE TranslIndustry Application, vol. 34, No.1,pp. 529-551, Jan/Feb 1998.

[2] F.Briz, M.W.Degner, and R.D.Lorenz, "Analysis andDesign of Current Regulators Using Complex Vectors,"IEEE TranslIndustry Application, vol. 36, pp. 817-825,May/June 2000.

[3] J.Jung, and K.Nam, "A Dynamic Decoupling ControlScheme for High-Speed Operation of Induction Motors,"IEEE Transl.Industrial Electronics, vol. 46, No.1, Feb1999.

[4] L.Springob, and J.Holtz, "High-Bandwidth CurrentControl for Torque-Ripple Compensation in PMSynchronous Machines," IEEE TranslIndustrialElectronics, vol. 45, No.5, Oct 1998.

[5] A.Fratta, G.Griffero, and S.Nieddu, "ComparativeAnalysis among DSP and FPGA-based Control Capailitiesin PWM Power Converters," IEEE-IECON '04,Busan ,Korea, vol. 1, pp. 257-262,2-6, Nov2004.

[6] M.W.Naouar, E.Monmasson and I.Slama-Belkhodja,"FPGA-Based Torque Controller of a SynchronousMachine," IEEE-ICIT, vol. 1, pp. 9-14, 8- 10, Dec 2004.

[7] V.Blasko, V.Kaura, and W.Niewiadomski, "Sampling ofDiscontinuous Voltage and Current Signals in Electrical

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