Designing the WRAMP

Dean ArmstrongThe University of Waikato

Aims and Objectives Provide a suitable hardware platform

for teaching Computer Systems Commercial processors generally

not suitable for teaching Designed for high performance/low cost Often have quirks that complicate

teaching Need to design a custom processor

Implementing a Processor Could use full custom design, but…

Extremely expensive Long design cycle Inflexible

Another alternative is to use ‘Reconfigurable Logic’ General purpose chip which can be

configured to act in a certain way

Reconfigurable Logic Comparatively inexpensive

Particularly in small quantities Short design cycle Extremely flexible

FPGA’s Field Programmable Gate Arrays

(FPGA’s) are a kind of Reconfigurable Logic

Static RAM based An ‘FPGA Image’ is loaded to specify how

the chip is to act When the power is off the image is lost

An FPGA is used for the WRAMP processor on the REX board

Creating an FPGA Image Can use VHDL

VHDL = VHSIC Hardware Description Language

VHSIC = Very High Speed Integrated Circuit

VHDL is like a programming language

It allows hardware to be described

VHDL example code VHDL code is

synthesised to create an FPGA image

Code can also be simulated to test its correctness

a_bus <= pc when pc_out = ‘1’

else (other => ‘Z’);

...

process (reset, clk)

begin

if reset = ‘1’ then

pc <= (others => ‘0’);

elsif rising_edge(clk) then

if pc_in = ‘1’ then

pc <= c_bus;

end if;

end if;

end process;

Processor Design Choices Need to consider style of

architecture RISC/CISC Memory and I/O models Number of registers Choice of instructions Exception mechanism

WRAMP RISC style processor Load/store architecture 16 general purpose registers Consistent and predictable

instruction set Simple exception mechanism

Processor Design Firstly construct a datapath which will

allow execution of all the instructions This is a matter of drawing block

diagrams Decide on instruction encodings Design control logic to perform the

operations Draw state machines

Datapath Design We use building blocks such as

Registers Sometimes combined as a Register File

ALU Buses Memory Interface

When combining these we need to… Ensure that we can execute all the

instructions Keep the datapath as simple as possible

The WRAMP Datapath

Instruction Encodings

I-Type instruction 4 bits 4 bits 4 bits 4 bits 16 bits

OPcode Rd Rs Func Immediate

R-Type instruction 4 bits 4 bits 4 bits 4 bits 12 bits 4 bits

OPcode Rd Rs Func 0000 0000 0000 Rt

J -Type instruction 4 bits 4 bits 4 bits 20 bits

OPcode Rd Rs Address/Offset

Example Control

Insn Fetch PC Incr

OPcode = “0000”

OPcode = “0100”

OPcode = “0110”

Do Jump

Save $ra

ALU op

Control Signals We need to decide which control signals

should be set in each state. Eg. Insn Fetch

pc_out, ir_in, mem_read PC Incr

pc_out, alu_out, alu_func = inc, pc_in Save $ra

pc_out, b_out, sel_b = $0, alu_out, alu_func = add, c_in, sel_c = $ra

Do jump imm_20_out, a_out, sel_a = $0, alu_out, alu_func =

add, pc_in

Processor Implementation With the datapath and control

decided we can begin implementation in VHDL

We can run the code on a simulator to ensure that it works correctly

Supporting Tools To allow use of the WRAMP, certain

tools were created Assembler (wasm) Linker (wlink) C Compiler (wcc)

We also needed a mini operating system to run on the boards (WRAMPmon)

Schematic Design

PCB Layout