Research ArticleDesign and Analysis of Nanoscaled Recessed-SD SOIMOSFET-Based Pseudo-NMOS Inverter forLow-Power Electronics

Anjali Priya Nilesh Anand Srivastava and Ram Awadh Mishra

Department of Electronics and Communication Engineering Motilal Nehru National Institute of Technology AllahabadPrayagraj-211004 India

Correspondence should be addressed to Anjali Priya rel1454mnnitacin

Received 24 August 2018 Revised 3 January 2019 Accepted 24 February 2019 Published 28 March 2019

Academic Editor Andrey E Miroshnichenko

Copyright copy 2019 Anjali Priya et al +is is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

In this paper a comparative analysis of nanoscaled triple metal gate (TMG) recessed-sourcedrain (Re-SD) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime Forthis firstly an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity ofthe studied device and also verified against simulation results In this structure the novel concept of backchannel inversion hasbeen utilized for the study of device performance+e threshold voltage has been analyzed by varying the parameters of the devicelike the ratio of metal gate length and the recessed-sourcedrain thickness for TMG Re-SD SOI MOSFET Drain-induced barrierlowering (DIBL) has also been explored in terms of recessed-sourcedrain thickness and the metal gate length ratio to examineshort channel effects (SCEs) For the exact estimation of results the comparison of the existing multimetal gate structures withTMG Re-SD SOI MOSFET has also been taken under study in terms of electrostatic performance ie threshold voltagesubthreshold slope and on-off current ratio +ese structures are investigated with the TCAD numerical simulator from SilvacoATLAS Furthermore for the first time TMG Re-SD FD SOI MOSFET-based pseudo-NMOS inverter has been designed toobserve the device performance at circuit levels It has been found that the device offers high noise immunity with optimumswitching characteristics and the propagation delay of the studied circuit is recorded as 043 ps

1 Introduction

Incorporation of new technologies is going to be morecrucial in the coming era of CMOS devices [1 2] Shortchannel effect has become the major problem in perfor-mance improvement at the nanotechnology node [3]Various technologies have been reported recently regardingthe improvement in the device performance at nanometrenodes such as FinFET FD SOI recessed-source and drainand gate engineering [4ndash20] In last few years FinFET de-vices have gained popularity due to better short channelimmunity [4] However the fin structure was found to bemore complex as compared to FD SOI MOSFETs +eleakage and power consumption are drastically reduced bythe use of the FD SOI structure [5ndash7] Dielectric isolation inSOI MOSFET reduces parasitic capacitances and substrate

leakage current which tempted the device for analog anddigital applications [8] Since FD SOI MOSFET is associatedwith the problem of higher sourcedrain series resistancethe structure of single-metal gate (SMG) recessed-sourcedrain MOSFET was introduced [9 10] In Re-SD-baseddevice the depth of source and drain is expanded in theburied insulated layer It reduces capacitances and givesbetter drive current [11]

To increase the drive current capability multimaterialgate [12ndash14] is associated with recessed-sourcedrainMOSFET To reduce DIBL hot carrier effect [15] andgate transport efficiency the dual-metal gate (DMG)structure was acquainted in the papers [16] In [17] TMGRe-SD SOI MOSFET was proposed in which work func-tions are in the descending order from the source end todrain end Due to distinct work function of gate metal

HindawiJournal of NanotechnologyVolume 2019 Article ID 4935073 12 pageshttpsdoiorg10115520194935073

contacts there is a spike identified in the channel electricfield So the carrier transport efficiency is improved and sothe driving capability of the device is also improved [18]+ere is suppressed hot carrier effect (HCE) due to highwork function of the control gate than the screen gates

+e three metals in the gate structures give two steppotential profile It reduces DIBL and improves the currenttransit speed [19] So it enhances current-driving capabilitywhich ensures SCEs reduction It can be the same thresholdvoltage with reduced doping due to gate engineering [20] Itassures immunity against mobility degradation and im-proved transconductance

Moreover use of portable devices in the integration ofVLSI circuits requires low power and high speed At the levelof circuit design the power reduction shifts towards theconsideration of a different logic style CMOS logic offers allrequirement of lower and high speed but in CMOS the sizeof the PMOS transistor is larger than the NMOS transistor tobalance the rise and fall time Sometimes in the logic cir-cuits it requires to reduce the area for some applications Itcan be fulfilled by the use of pseudo-NMOS logic It uses then+ 1 transistor as compared to CMOS which uses 2ntransistors in the logic circuit [21] Here TMG Re-SD FDSOI MOSFET has been utilized for the performance analysisof aforesaid pseudo-NMOS inverter for low-power digitalapplications

In this work threshold voltage of triple-metal gate Re-SD SOI MOSFET is analyzed for the first time which is theextension of previous work [17] because surface potential isrequired to model the threshold voltage of the deviceHowever to describe the overall electrostatic performanceof the device the threshold voltage model is necessaryHere analytical threshold voltage model for the deviceunder consideration has been proposed by assuming cer-tain parabolic approximations and verified against two-dimensional mathematical simulations It is analyzed byvarying device parameters like Re-SD thickness oxidethickness and body thickness Effect of DIBL for a differentRe-SD thickness has also been discussed +resholdvoltage subthreshold slope and onoff current ratio havebeen compared for SMG DMG and TMG It is also in-vestigated by 2D TCAD simulator Silvaco ATLAS [22]Furthermore the studied device has been analyzed for thedesign of the pseudo-NMOS inverter for the estimation ofits switching behaviour

Section 2 discusses the materials and methods of devicedesign and the specifications +e analytical modeling hasbeen presented in Section 3 and corresponding results arediscussed in Section 4 Furthermore the design and analysisof the pseudo-NMOS inverter is shown in Section 5 and theoverall contribution is mentioned in Section 6

2 Materials and Methods

+e cross-sectional view of the TMG Re-SD SOI MOSFETis shown in Figure 1 where L tsi tox trsd tbox and dboxrepresent the channel length silicon body thickness oxidethickness Re-SD thickness buried oxide (BOX) layerthickness and SD overlap over the BOX layer respectively

+e x-axis is taken along the front oxide-channel interfaceand y-axis is taken along the source-channel interface +ethree metals of the gate are M1(control gate) M2(screengate first) and M3(screen gate second) in which Au Moand Ti are the metal materials +e length of these threemetals are termed as L1 L2 and L3 where L1 + L2 + L3 LNa Nd and Nsub are concentration levels of the channelregion sourcedrain region and substrate region Alsounder the zero bias condition it is assumed that channel isfully depleted+e structures of single-metal double-metaland triple-metal gate are described in Table 1 for 90 nmchannel length

3 Analytical Modeling

+e device under consideration is shown in Figure 1 forwhich under parabolic approximations 2D Poissonrsquosequation for the potential at the surface of the channel ispresented as follows

z2emptyi(x y)

zx2 +z2emptyi(x y)

zy2 qNa

εsi (1)

where i 1 2 and 3 for region 1(0lexle L1) 2(L1 le xleL1 + L2) and 3(L1 + L2 le xleL) εsi is the silicon permit-tivity +e solution of (1) is defined as follows

emptyi(x y) emptysi(x) + Ci1(x)y + Ci2(x)y2 (2)

whereemptysi(x) is the surface potential at the SiO2Si interface+e coefficient Ci1(x) and Ci2(x) can be determined fromthe following boundary condition

At the boundary line of region 1 and 2zempty1(x y)

zx

1113868111386811138681113868111386811138681113868xL1

zempty2(x y)

zx

1113868111386811138681113868111386811138681113868xL1

zempty2(x y)

zx

1113868111386811138681113868111386811138681113868xL1+L2

zempty3(x y)

zx

1113868111386811138681113868111386811138681113868xL1+L2

(3)

At boundary line between SiO2 and Si

Substrate

Box

Oxide

Channel

VS VD

VG

L

xy

tbox

trsd

tsi

Vsub

tox

Source Drain

M1 M2 M3

dbox

Figure 1 Cross-sectional view of TMG recessed-SD UTB SOIMOSFET

2 Journal of Nanotechnology

εsi middotzempty1(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox1 middot

emptys1(x)minus VGS minusVFB1( 1113857

L1

εsi middotzempty2(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox2 middot

emptys2(x)minus VGS minusVFB2( 1113857

L2

εsi middotzempty3(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox3 middot

emptys3(x)minus VGS minusVFB3( 1113857

L3

(4)

Oxide capacitances Cox1 Cox2 and Cox3 and flat bandvoltage VFB1 VFB2 and VFB3 are defined in [17] At theboundary line between the Si and BOX layer

εsi middotzempty1(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd1 middotVs minusVFB4 minusemptyb1(x)

L1

+ Crsd2 middotVD minusVFB4 minusemptyb1(x)

L1

+ Cbox1 middotVsub minusVFB5 minusemptyb1(x)

L1

εsi middotzempty2(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd3 middotVs minusVFB4 minusemptyb2(x)

L2

+ Crsd4 middotVD minusVFB4 minusemptyb2(x)

L2

+ Cbox2 middotVsub minusVFB5 minusemptyb2(x)

L2

εsi middotzempty3(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd5 middotVs minusVFB4 minusemptyb3(x)

L3

+ Crsd6 middotVD minusVFB4 minusemptyb3(x)

L3

+ Cbox3 middotVsub minusVFB5 minusemptyb3(x)

L3

(5)

Re-SD capacitances Crsd1 Crsd2 Crsd3 Crsd4 Crsd5 andCrsd6 and flat band voltage VFB4 and VFB5 are defined in [17]emptybi is the surface potential of the backchannel

at source side empty1(0 y) Vbi

at drain side empty3(L y) Vbi + VDS(6)

where Vbi and VDS are the barrier potential and drain-to-source bias +reshold voltage is described as the gatevoltage in which the minimum surface potential is equal totwice the Fermi potential In the TMG structure there arethree metal gates with different work functions +e mini-mum surface potential is defined under the region of highestwork function (control gate)

In the recessed-sourcedrain structure backchannelinversion is also significant as compared to front channelinversion due to certain length of recessed-sourcedrain+erefore threshold voltage for the front and backchannel isanalyzed in this modeling +reshold voltage is describedwith a larger minimum surface potential

31 Front reshold Voltage Surface potential at SiO2Si iscalculated as follows [17]

d2emptysi(x)

dx2 minusGsiemptysi(x) Hsi i 1 2 3 (7)

where Gsi and Hsi are defined in paper [17] Now thethreshold voltage can be evaluated by following expression

emptys1min1113868111386811138681113868VGSVth

emptys1 xmin( 11138571113868111386811138681113868VGSVth

2emptyFsi (8)

where emptys1min is the minimum surface potential at the frontchannel and xmin presents the position of minimum surfacepotential from the source side It can be obtained as

demptys1dx

1113868111386811138681113868111386811138681113868xxmin

0 (9)

where emptyFsi is the Fermi potential in the channel region andis defined as

emptyFsi kT

qln

Na

ni1113888 1113889 (10)

where ni is the intrinsic carrier concentration Solvingequation (1) gives the following expression of thresholdvoltage

Vth minusbs +

b2s minus 4ascs

1113969

2as (11)

+e derived formulas of coefficients as bs and cs areshown in Appendix A

32 Back reshold Voltage Surface potential at the SiO2BOX interface is calculated as follows [17]

d2emptybi(x)

dx2 minusGbiemptybi(x) Hbi i 1 2 3 (12)

where Gbi and Hbi are defined in [17] Similarly thresholdvoltage for the backchannel can be obtained by evaluatingthe following expression

emptyb1min1113868111386811138681113868VGSVth

emptyb1 xmin( 11138571113868111386811138681113868VGSVth

2emptyFsi (13)

where emptyb1min is the minimum surface potential in thebackchannel and xmin presents the position of the mini-mum surface potential from the source side It can beobtained as

demptyb1dx

1113868111386811138681113868111386811138681113868xxmin

0 (14)

Solving this equation gives the following expression ofthreshold voltage

Table 1 Device structure of SMG DMG and TMG Re-SD SOIMOSFET

Device L1 L2 L3 emptyM1emptyM2

emptyM3

SMG Re-SD 90 mdash mdash 48 eV (Au) mdash mdashDMG Re-SD 45 45 mdash 48 eV (Au) 46 eV (Mo) mdashTMG Re-SD 30 30 30 48 eV (Au) 46 eV (Mo) 44 eV (Ti)

Journal of Nanotechnology 3

Vth minusbb +

b2b minus 4abcb

1113969

2ab (15)

+e derived formulas of coefficients ab bb and cb areshown in Appendix B

In the next section the corresponding results has beendiscussed and verified against simulation results

4 Results and Discussion

Analytical model of the threshold voltage for the studiedstructure has also been compared with TCAD ATLASSimulator [21] In the ATLAS simulation different types ofthe physical model have been used like field-dependentmobility mode (FLDMOB) concentration-dependent mo-bility mode (CVT) and Fermi-Dirac statistical model +edoping profile is uniform +e device parameters have beenchosen as per the ITRS roadmap +e device channel length(L) is 90 nm and it has been varied from 20 nm to 300 nm inorder to evidence the scaling challenges +e front oxidethickness (tox) is considered as 2 nm buried oxide thickness(tbox) as 200 nm silicon channel thickness (tsi) of 10 nm andRe-SD thickness (trsd) of 30 nm +e studied MOSFET ischaracterized with uniform sourcedrain concentration (Nd)of 1020 cmminus3 and low bulk doping (Nsub) of 1015 cmminus3

41 reshold Voltage +e comparative study of thresholdvoltage for SMG DMG and TMG Re-SD SOI MOSFET isshown in Figure 2 One can find that TMG offers smallestroll off in threshold till 40 nm as compared to DMG and canbe further optimized with the metal gate length ratio Alsothere is 14-15 improvement in the TMG Re-SD SOIMOSFET in threshold voltage and 05ndash1 error in be-tween simulation and model Figure 3 shows the graph forthe threshold voltage by varying length ratio of screen andcontrol gates keeping the overall gate length constant Rolloff in threshold voltage is decreased by choosing a shorterscreen gate length but the effect of drain potential variationbecomes considerable which indicates poor immunity toDIBL So the ratio (L1 L2) can be optimized to reduce rolloff in threshold voltage

Figure 4 presents the graph of Vth with channel lengthwhile recessed-sourcedrain thickness is a variable param-eter For a larger recessed-sourcedrain thickness roll off ishigher at a shorter channel length which shows the re-duction of gate controllability over the channel and so theSCEs In the Re-SD MOSFET inversion in the backchanneloccurs before inversion in the front channel At zerorecessed thickness device behaves like conventional SOIMOSFET in which the front gate controls the channel Sorecessed-sourcedrain thickness should be optimized fortrade-off between the SCEs and the backchannel controlFigure 5 shows the graph of Vth versus channel length byvarying work function values of three materials of gate+reshold voltage is observed to be increased for highervalues of work function and also have less roll off When thedifference between the work function is reduced the channelwill be more prone to drain voltage variation which shows

more HCEs So work function should be maintained tooptimize between SCEs and HCEs

Figure 6 shows the graph of DIBL versus channel lengthfor varying the length ratio of control gate and screen gateswhile the overall channel length is constant+e graph showsthe reduction of DIBL at a shorter length of the control gateIt demonstrates that the structure will be less susceptible toDIBL when control gate length is kept lower Figure 7 showsthe graph of drain-induced barrier lowering (DIBL) plottedagainst channel length by varying the thickness of therecessed-sourcedrain region Here DIBL is the difference

Thre

shol

d vo

ltage

(V)

05

04

03

02

01

00

0 50 100 150Channel length (nm)

200

Lines modelSymbols Atlas

250 300

SMGDMGTMG

Figure 2 Comparison of threshold voltage for SMG DMG andTMG Re-SD SOI MOSFET

Thre

shol

d vo

ltage

(V)

04

03

02

01

00

Lines modelSymbols Atlas

0 50 100 150Channel length (nm)

200 250 300

L1L2L3 = 1 2 3L1L2L3 = 1 1 1L1L2L3 = 3 2 1

Figure 3 +reshold voltage for different ratios of control gate andscreen gates of TMG Re-SD SOI MOSFET

4 Journal of Nanotechnology

between the threshold voltage at drain to the source voltagevalue of 01 V and 005V It has been observed that DIBL isminimized by increasing the thickness of recessed-sourcedrain thickness

42 Electrostatic Performance +e graph of drain currentversus gate voltage for single double and TMG Re-SD SOIMOSFET is shown in Figure 8 +is graph reveals that thedrain current is better in the case of TMG+is high currentis due to high electric field which results from three gatemetals +e increment in the electric field at the edge of

metals accelerates the carriers which automatically en-hances the transport efficiency of the carriers+ere is 3ndash17enhancement in the drain current for TMG recessed-SDMOSFET However this signifies a lesser change as com-pared to SMG and DMGMoreover it is well known that theon-current behaviour of all the three devices depends uponrecessed-SD structure +is is the reason that all the threedevices have almost the same on current behaviour due torecessed-SD and due to the TMG structure electrostaticcharacteristics such as off-state leakage threshold voltageand DIBL will be improved Figure 9 represents the onoffcurrent ratio with respect to channel length It shows that the

Thre

shol

d vo

ltage

(V)

04

03

02

01

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 4+reshold voltage for different values of recessed-sourcedrain thickness

Thre

shol

d vo

ltage

(V)

04

03

02

01

ΦM1= 477eV ΦM2

= 44eV ΦM3= 41eV

ΦM1= 48eV ΦM2

= 46eV ΦM3= 44eV

ΦM1= 485eV ΦM2

= 47eV ΦM3= 454eV

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 5 +reshold voltage for different sets of values of workfunctions for TMG Re-SD SOI MOSFET

010

008

006

004DIB

L (V

V)

002

000

0 20 40 60 80Channel length (nm)

100 120 140 160

L1L2L3 = 12 3L1L2L3 = 11 1L1L2L3 = 32 1

Lines modelSymbols Atlas

Figure 6 DIBL for the different ratios of control gate and screengates of the TMG device

DIB

L (V

V)

012

008

010

006

004

002

000

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 7 DIBL for the different values of recessed-sourcedrainthickness

Journal of Nanotechnology 5

switching (IonIoff) current ratio is higher for TMG thanDMG and SMG +e peaks in the electric field are increaseddue to the two interface of metal gate So the currenttransport efficiency becomes better in comparison to dualand single-metal gate Onoff current ratio is increased bythe increasing gate length As compared to studied DMGRe-SD there is 3ndash17 improvement in the onoff current ratioin TMG Figure 10 is the graph of the onoff current ratio at adifferent value of oxide thickness As shown in the graph onoff current ratio is larger for a small value of oxide thicknessWhen the thickness is increased onoff current ratio isdecreased It is due to the enhancement of on current ascompared to off current It presents the better currenttransport at a small oxide region thickness IonIoff current

ratio for the TMG Re-SD device is better as compared toDMG and SMG due to the better current transport

Onoff current ratio with the variation of the thickness ofthe Re-SD region is shown in Figure 11 It shows the higheronoff current ration at zero Re-SD thickness and lower at100 nm thickness Since at 0 nm thickness the resistance valueof the MOSFET is increased So the thickness is slightly in-creased to optimize between resistance and current It alsoshows the 2ndash10 better onoff current ratio for the TMGRe-SD structure Figure 12 represents the graph of subthresholdslope at different values of channel length As shown in thegraph the subthreshold value is decreased towards higherchannel length +e value of subthreshold slope is approxi-mately 70mVdec at a higher channel length It increases at alower value due to high leakage It also shows the lower valuefor TMG as compared to DMG and SMG Re-SD SOIMOSFET +ere is 05-6 decrease in the subthreshold slopefor TMG as compared to DMG Re-SD Figure 13 presentsthe subthreshold slope with the variation of oxide thicknessat 90 nm channel length As shown in the graph the sub-threshold value is decreased by decreasing oxide thickness+e subthreshold value is between 60 and 73mVdecwhich is approximately close to the ideal value of70mVdec Subthreshold slope for TMG is lower than thatfor DMG and SMG Re-SD structures which show thatTMG is better immune to SCEs than DMG and SMG It isobserved that 07ndash15 reduction in the subthreshold slopefor TMG Re-SD SOI MOSFET Subthreshold slope withthe variation of Re-SD thickness is represented in Fig-ure 14 As shown in the graph the subthreshold value islower for 0 nm Re-SD thickness but it increases the seriesresistance of the MOSFET +e subthreshold value for100 nm thickness is higher So Re-SD thickness is kept inbetween to optimize between resistance and SCEs ie at30 nm It also shows the 001ndash03 better results for theTMG Re-SD device as compared to others

30 times 10ndash4

25 times 10ndash4

20 times 10ndash4

15 times 10ndash4

10 times 10ndash4

Dra

in cu

rren

t (A

μm

)

50 times 10ndash5

00

00 02

SMGDMGTMG

04Gate voltage (V)

06 08 10

Figure 8 Drain current versus gate voltage for SMG DMG andTMG Re-SD SOI MOSFET

I onI o

ff

40 times 108

35 times 108

30 times 108

25 times 108

20 times 108

15 times 108

10 times 108

50 times 107

00

SMGDMGTMG

Channel length (nm)40 50 60 70 80 90 100

Figure 9 IonIoff at various channel lengths for SMG DMG andTMG Re-SD SOI MOSFET

16 times 109

14 times 109

12 times 109

10 times 109

80 times 108

I onI o

ff

60 times 108

40 times 108

20 times 108

00

SMGDMGTMG

10 15 20Oxide thickness (nm)

25 30

Figure 10 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus oxide thickness

6 Journal of Nanotechnology

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

εsi middotzempty1(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox1 middot

emptys1(x)minus VGS minusVFB1( 1113857

L1

εsi middotzempty2(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox2 middot

emptys2(x)minus VGS minusVFB2( 1113857

L2

εsi middotzempty3(x y)

zy

11138681113868111386811138681113868111386811138681113868y0 Cox3 middot

emptys3(x)minus VGS minusVFB3( 1113857

L3

(4)

Oxide capacitances Cox1 Cox2 and Cox3 and flat bandvoltage VFB1 VFB2 and VFB3 are defined in [17] At theboundary line between the Si and BOX layer

εsi middotzempty1(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd1 middotVs minusVFB4 minusemptyb1(x)

L1

+ Crsd2 middotVD minusVFB4 minusemptyb1(x)

L1

+ Cbox1 middotVsub minusVFB5 minusemptyb1(x)

L1

εsi middotzempty2(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd3 middotVs minusVFB4 minusemptyb2(x)

L2

+ Crsd4 middotVD minusVFB4 minusemptyb2(x)

L2

+ Cbox2 middotVsub minusVFB5 minusemptyb2(x)

L2

εsi middotzempty3(x y)

zy

11138681113868111386811138681113868111386811138681113868ytsi

Crsd5 middotVs minusVFB4 minusemptyb3(x)

L3

+ Crsd6 middotVD minusVFB4 minusemptyb3(x)

L3

+ Cbox3 middotVsub minusVFB5 minusemptyb3(x)

L3

(5)

Re-SD capacitances Crsd1 Crsd2 Crsd3 Crsd4 Crsd5 andCrsd6 and flat band voltage VFB4 and VFB5 are defined in [17]emptybi is the surface potential of the backchannel

at source side empty1(0 y) Vbi

at drain side empty3(L y) Vbi + VDS(6)

where Vbi and VDS are the barrier potential and drain-to-source bias +reshold voltage is described as the gatevoltage in which the minimum surface potential is equal totwice the Fermi potential In the TMG structure there arethree metal gates with different work functions +e mini-mum surface potential is defined under the region of highestwork function (control gate)

In the recessed-sourcedrain structure backchannelinversion is also significant as compared to front channelinversion due to certain length of recessed-sourcedrain+erefore threshold voltage for the front and backchannel isanalyzed in this modeling +reshold voltage is describedwith a larger minimum surface potential

31 Front reshold Voltage Surface potential at SiO2Si iscalculated as follows [17]

d2emptysi(x)

dx2 minusGsiemptysi(x) Hsi i 1 2 3 (7)

where Gsi and Hsi are defined in paper [17] Now thethreshold voltage can be evaluated by following expression

emptys1min1113868111386811138681113868VGSVth

emptys1 xmin( 11138571113868111386811138681113868VGSVth

2emptyFsi (8)

where emptys1min is the minimum surface potential at the frontchannel and xmin presents the position of minimum surfacepotential from the source side It can be obtained as

demptys1dx

1113868111386811138681113868111386811138681113868xxmin

0 (9)

where emptyFsi is the Fermi potential in the channel region andis defined as

emptyFsi kT

qln

Na

ni1113888 1113889 (10)

where ni is the intrinsic carrier concentration Solvingequation (1) gives the following expression of thresholdvoltage

Vth minusbs +

b2s minus 4ascs

1113969

2as (11)

+e derived formulas of coefficients as bs and cs areshown in Appendix A

32 Back reshold Voltage Surface potential at the SiO2BOX interface is calculated as follows [17]

d2emptybi(x)

dx2 minusGbiemptybi(x) Hbi i 1 2 3 (12)

where Gbi and Hbi are defined in [17] Similarly thresholdvoltage for the backchannel can be obtained by evaluatingthe following expression

emptyb1min1113868111386811138681113868VGSVth

emptyb1 xmin( 11138571113868111386811138681113868VGSVth

2emptyFsi (13)

where emptyb1min is the minimum surface potential in thebackchannel and xmin presents the position of the mini-mum surface potential from the source side It can beobtained as

demptyb1dx

1113868111386811138681113868111386811138681113868xxmin

0 (14)

Solving this equation gives the following expression ofthreshold voltage

Table 1 Device structure of SMG DMG and TMG Re-SD SOIMOSFET

Device L1 L2 L3 emptyM1emptyM2

emptyM3

SMG Re-SD 90 mdash mdash 48 eV (Au) mdash mdashDMG Re-SD 45 45 mdash 48 eV (Au) 46 eV (Mo) mdashTMG Re-SD 30 30 30 48 eV (Au) 46 eV (Mo) 44 eV (Ti)

Journal of Nanotechnology 3

Vth minusbb +

b2b minus 4abcb

1113969

2ab (15)

+e derived formulas of coefficients ab bb and cb areshown in Appendix B

In the next section the corresponding results has beendiscussed and verified against simulation results

4 Results and Discussion

Analytical model of the threshold voltage for the studiedstructure has also been compared with TCAD ATLASSimulator [21] In the ATLAS simulation different types ofthe physical model have been used like field-dependentmobility mode (FLDMOB) concentration-dependent mo-bility mode (CVT) and Fermi-Dirac statistical model +edoping profile is uniform +e device parameters have beenchosen as per the ITRS roadmap +e device channel length(L) is 90 nm and it has been varied from 20 nm to 300 nm inorder to evidence the scaling challenges +e front oxidethickness (tox) is considered as 2 nm buried oxide thickness(tbox) as 200 nm silicon channel thickness (tsi) of 10 nm andRe-SD thickness (trsd) of 30 nm +e studied MOSFET ischaracterized with uniform sourcedrain concentration (Nd)of 1020 cmminus3 and low bulk doping (Nsub) of 1015 cmminus3

41 reshold Voltage +e comparative study of thresholdvoltage for SMG DMG and TMG Re-SD SOI MOSFET isshown in Figure 2 One can find that TMG offers smallestroll off in threshold till 40 nm as compared to DMG and canbe further optimized with the metal gate length ratio Alsothere is 14-15 improvement in the TMG Re-SD SOIMOSFET in threshold voltage and 05ndash1 error in be-tween simulation and model Figure 3 shows the graph forthe threshold voltage by varying length ratio of screen andcontrol gates keeping the overall gate length constant Rolloff in threshold voltage is decreased by choosing a shorterscreen gate length but the effect of drain potential variationbecomes considerable which indicates poor immunity toDIBL So the ratio (L1 L2) can be optimized to reduce rolloff in threshold voltage

Figure 4 presents the graph of Vth with channel lengthwhile recessed-sourcedrain thickness is a variable param-eter For a larger recessed-sourcedrain thickness roll off ishigher at a shorter channel length which shows the re-duction of gate controllability over the channel and so theSCEs In the Re-SD MOSFET inversion in the backchanneloccurs before inversion in the front channel At zerorecessed thickness device behaves like conventional SOIMOSFET in which the front gate controls the channel Sorecessed-sourcedrain thickness should be optimized fortrade-off between the SCEs and the backchannel controlFigure 5 shows the graph of Vth versus channel length byvarying work function values of three materials of gate+reshold voltage is observed to be increased for highervalues of work function and also have less roll off When thedifference between the work function is reduced the channelwill be more prone to drain voltage variation which shows

more HCEs So work function should be maintained tooptimize between SCEs and HCEs

Figure 6 shows the graph of DIBL versus channel lengthfor varying the length ratio of control gate and screen gateswhile the overall channel length is constant+e graph showsthe reduction of DIBL at a shorter length of the control gateIt demonstrates that the structure will be less susceptible toDIBL when control gate length is kept lower Figure 7 showsthe graph of drain-induced barrier lowering (DIBL) plottedagainst channel length by varying the thickness of therecessed-sourcedrain region Here DIBL is the difference

Thre

shol

d vo

ltage

(V)

05

04

03

02

01

00

0 50 100 150Channel length (nm)

200

Lines modelSymbols Atlas

250 300

SMGDMGTMG

Figure 2 Comparison of threshold voltage for SMG DMG andTMG Re-SD SOI MOSFET

Thre

shol

d vo

ltage

(V)

04

03

02

01

00

Lines modelSymbols Atlas

0 50 100 150Channel length (nm)

200 250 300

L1L2L3 = 1 2 3L1L2L3 = 1 1 1L1L2L3 = 3 2 1

Figure 3 +reshold voltage for different ratios of control gate andscreen gates of TMG Re-SD SOI MOSFET

4 Journal of Nanotechnology

between the threshold voltage at drain to the source voltagevalue of 01 V and 005V It has been observed that DIBL isminimized by increasing the thickness of recessed-sourcedrain thickness

42 Electrostatic Performance +e graph of drain currentversus gate voltage for single double and TMG Re-SD SOIMOSFET is shown in Figure 8 +is graph reveals that thedrain current is better in the case of TMG+is high currentis due to high electric field which results from three gatemetals +e increment in the electric field at the edge of

metals accelerates the carriers which automatically en-hances the transport efficiency of the carriers+ere is 3ndash17enhancement in the drain current for TMG recessed-SDMOSFET However this signifies a lesser change as com-pared to SMG and DMGMoreover it is well known that theon-current behaviour of all the three devices depends uponrecessed-SD structure +is is the reason that all the threedevices have almost the same on current behaviour due torecessed-SD and due to the TMG structure electrostaticcharacteristics such as off-state leakage threshold voltageand DIBL will be improved Figure 9 represents the onoffcurrent ratio with respect to channel length It shows that the

Thre

shol

d vo

ltage

(V)

04

03

02

01

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 4+reshold voltage for different values of recessed-sourcedrain thickness

Thre

shol

d vo

ltage

(V)

04

03

02

01

ΦM1= 477eV ΦM2

= 44eV ΦM3= 41eV

ΦM1= 48eV ΦM2

= 46eV ΦM3= 44eV

ΦM1= 485eV ΦM2

= 47eV ΦM3= 454eV

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 5 +reshold voltage for different sets of values of workfunctions for TMG Re-SD SOI MOSFET

010

008

006

004DIB

L (V

V)

002

000

0 20 40 60 80Channel length (nm)

100 120 140 160

L1L2L3 = 12 3L1L2L3 = 11 1L1L2L3 = 32 1

Lines modelSymbols Atlas

Figure 6 DIBL for the different ratios of control gate and screengates of the TMG device

DIB

L (V

V)

012

008

010

006

004

002

000

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 7 DIBL for the different values of recessed-sourcedrainthickness

Journal of Nanotechnology 5

switching (IonIoff) current ratio is higher for TMG thanDMG and SMG +e peaks in the electric field are increaseddue to the two interface of metal gate So the currenttransport efficiency becomes better in comparison to dualand single-metal gate Onoff current ratio is increased bythe increasing gate length As compared to studied DMGRe-SD there is 3ndash17 improvement in the onoff current ratioin TMG Figure 10 is the graph of the onoff current ratio at adifferent value of oxide thickness As shown in the graph onoff current ratio is larger for a small value of oxide thicknessWhen the thickness is increased onoff current ratio isdecreased It is due to the enhancement of on current ascompared to off current It presents the better currenttransport at a small oxide region thickness IonIoff current

ratio for the TMG Re-SD device is better as compared toDMG and SMG due to the better current transport

Onoff current ratio with the variation of the thickness ofthe Re-SD region is shown in Figure 11 It shows the higheronoff current ration at zero Re-SD thickness and lower at100 nm thickness Since at 0 nm thickness the resistance valueof the MOSFET is increased So the thickness is slightly in-creased to optimize between resistance and current It alsoshows the 2ndash10 better onoff current ratio for the TMGRe-SD structure Figure 12 represents the graph of subthresholdslope at different values of channel length As shown in thegraph the subthreshold value is decreased towards higherchannel length +e value of subthreshold slope is approxi-mately 70mVdec at a higher channel length It increases at alower value due to high leakage It also shows the lower valuefor TMG as compared to DMG and SMG Re-SD SOIMOSFET +ere is 05-6 decrease in the subthreshold slopefor TMG as compared to DMG Re-SD Figure 13 presentsthe subthreshold slope with the variation of oxide thicknessat 90 nm channel length As shown in the graph the sub-threshold value is decreased by decreasing oxide thickness+e subthreshold value is between 60 and 73mVdecwhich is approximately close to the ideal value of70mVdec Subthreshold slope for TMG is lower than thatfor DMG and SMG Re-SD structures which show thatTMG is better immune to SCEs than DMG and SMG It isobserved that 07ndash15 reduction in the subthreshold slopefor TMG Re-SD SOI MOSFET Subthreshold slope withthe variation of Re-SD thickness is represented in Fig-ure 14 As shown in the graph the subthreshold value islower for 0 nm Re-SD thickness but it increases the seriesresistance of the MOSFET +e subthreshold value for100 nm thickness is higher So Re-SD thickness is kept inbetween to optimize between resistance and SCEs ie at30 nm It also shows the 001ndash03 better results for theTMG Re-SD device as compared to others

30 times 10ndash4

25 times 10ndash4

20 times 10ndash4

15 times 10ndash4

10 times 10ndash4

Dra

in cu

rren

t (A

μm

)

50 times 10ndash5

00

00 02

SMGDMGTMG

04Gate voltage (V)

06 08 10

Figure 8 Drain current versus gate voltage for SMG DMG andTMG Re-SD SOI MOSFET

I onI o

ff

40 times 108

35 times 108

30 times 108

25 times 108

20 times 108

15 times 108

10 times 108

50 times 107

00

SMGDMGTMG

Channel length (nm)40 50 60 70 80 90 100

Figure 9 IonIoff at various channel lengths for SMG DMG andTMG Re-SD SOI MOSFET

16 times 109

14 times 109

12 times 109

10 times 109

80 times 108

I onI o

ff

60 times 108

40 times 108

20 times 108

00

SMGDMGTMG

10 15 20Oxide thickness (nm)

25 30

Figure 10 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus oxide thickness

6 Journal of Nanotechnology

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

Vth minusbb +

b2b minus 4abcb

1113969

2ab (15)

+e derived formulas of coefficients ab bb and cb areshown in Appendix B

In the next section the corresponding results has beendiscussed and verified against simulation results

4 Results and Discussion

Analytical model of the threshold voltage for the studiedstructure has also been compared with TCAD ATLASSimulator [21] In the ATLAS simulation different types ofthe physical model have been used like field-dependentmobility mode (FLDMOB) concentration-dependent mo-bility mode (CVT) and Fermi-Dirac statistical model +edoping profile is uniform +e device parameters have beenchosen as per the ITRS roadmap +e device channel length(L) is 90 nm and it has been varied from 20 nm to 300 nm inorder to evidence the scaling challenges +e front oxidethickness (tox) is considered as 2 nm buried oxide thickness(tbox) as 200 nm silicon channel thickness (tsi) of 10 nm andRe-SD thickness (trsd) of 30 nm +e studied MOSFET ischaracterized with uniform sourcedrain concentration (Nd)of 1020 cmminus3 and low bulk doping (Nsub) of 1015 cmminus3

41 reshold Voltage +e comparative study of thresholdvoltage for SMG DMG and TMG Re-SD SOI MOSFET isshown in Figure 2 One can find that TMG offers smallestroll off in threshold till 40 nm as compared to DMG and canbe further optimized with the metal gate length ratio Alsothere is 14-15 improvement in the TMG Re-SD SOIMOSFET in threshold voltage and 05ndash1 error in be-tween simulation and model Figure 3 shows the graph forthe threshold voltage by varying length ratio of screen andcontrol gates keeping the overall gate length constant Rolloff in threshold voltage is decreased by choosing a shorterscreen gate length but the effect of drain potential variationbecomes considerable which indicates poor immunity toDIBL So the ratio (L1 L2) can be optimized to reduce rolloff in threshold voltage

Figure 4 presents the graph of Vth with channel lengthwhile recessed-sourcedrain thickness is a variable param-eter For a larger recessed-sourcedrain thickness roll off ishigher at a shorter channel length which shows the re-duction of gate controllability over the channel and so theSCEs In the Re-SD MOSFET inversion in the backchanneloccurs before inversion in the front channel At zerorecessed thickness device behaves like conventional SOIMOSFET in which the front gate controls the channel Sorecessed-sourcedrain thickness should be optimized fortrade-off between the SCEs and the backchannel controlFigure 5 shows the graph of Vth versus channel length byvarying work function values of three materials of gate+reshold voltage is observed to be increased for highervalues of work function and also have less roll off When thedifference between the work function is reduced the channelwill be more prone to drain voltage variation which shows

more HCEs So work function should be maintained tooptimize between SCEs and HCEs

Figure 6 shows the graph of DIBL versus channel lengthfor varying the length ratio of control gate and screen gateswhile the overall channel length is constant+e graph showsthe reduction of DIBL at a shorter length of the control gateIt demonstrates that the structure will be less susceptible toDIBL when control gate length is kept lower Figure 7 showsthe graph of drain-induced barrier lowering (DIBL) plottedagainst channel length by varying the thickness of therecessed-sourcedrain region Here DIBL is the difference

Thre

shol

d vo

ltage

(V)

05

04

03

02

01

00

0 50 100 150Channel length (nm)

200

Lines modelSymbols Atlas

250 300

SMGDMGTMG

Figure 2 Comparison of threshold voltage for SMG DMG andTMG Re-SD SOI MOSFET

Thre

shol

d vo

ltage

(V)

04

03

02

01

00

Lines modelSymbols Atlas

0 50 100 150Channel length (nm)

200 250 300

L1L2L3 = 1 2 3L1L2L3 = 1 1 1L1L2L3 = 3 2 1

Figure 3 +reshold voltage for different ratios of control gate andscreen gates of TMG Re-SD SOI MOSFET

4 Journal of Nanotechnology

between the threshold voltage at drain to the source voltagevalue of 01 V and 005V It has been observed that DIBL isminimized by increasing the thickness of recessed-sourcedrain thickness

42 Electrostatic Performance +e graph of drain currentversus gate voltage for single double and TMG Re-SD SOIMOSFET is shown in Figure 8 +is graph reveals that thedrain current is better in the case of TMG+is high currentis due to high electric field which results from three gatemetals +e increment in the electric field at the edge of

metals accelerates the carriers which automatically en-hances the transport efficiency of the carriers+ere is 3ndash17enhancement in the drain current for TMG recessed-SDMOSFET However this signifies a lesser change as com-pared to SMG and DMGMoreover it is well known that theon-current behaviour of all the three devices depends uponrecessed-SD structure +is is the reason that all the threedevices have almost the same on current behaviour due torecessed-SD and due to the TMG structure electrostaticcharacteristics such as off-state leakage threshold voltageand DIBL will be improved Figure 9 represents the onoffcurrent ratio with respect to channel length It shows that the

Thre

shol

d vo

ltage

(V)

04

03

02

01

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 4+reshold voltage for different values of recessed-sourcedrain thickness

Thre

shol

d vo

ltage

(V)

04

03

02

01

ΦM1= 477eV ΦM2

= 44eV ΦM3= 41eV

ΦM1= 48eV ΦM2

= 46eV ΦM3= 44eV

ΦM1= 485eV ΦM2

= 47eV ΦM3= 454eV

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 5 +reshold voltage for different sets of values of workfunctions for TMG Re-SD SOI MOSFET

010

008

006

004DIB

L (V

V)

002

000

0 20 40 60 80Channel length (nm)

100 120 140 160

L1L2L3 = 12 3L1L2L3 = 11 1L1L2L3 = 32 1

Lines modelSymbols Atlas

Figure 6 DIBL for the different ratios of control gate and screengates of the TMG device

DIB

L (V

V)

012

008

010

006

004

002

000

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 7 DIBL for the different values of recessed-sourcedrainthickness

Journal of Nanotechnology 5

switching (IonIoff) current ratio is higher for TMG thanDMG and SMG +e peaks in the electric field are increaseddue to the two interface of metal gate So the currenttransport efficiency becomes better in comparison to dualand single-metal gate Onoff current ratio is increased bythe increasing gate length As compared to studied DMGRe-SD there is 3ndash17 improvement in the onoff current ratioin TMG Figure 10 is the graph of the onoff current ratio at adifferent value of oxide thickness As shown in the graph onoff current ratio is larger for a small value of oxide thicknessWhen the thickness is increased onoff current ratio isdecreased It is due to the enhancement of on current ascompared to off current It presents the better currenttransport at a small oxide region thickness IonIoff current

ratio for the TMG Re-SD device is better as compared toDMG and SMG due to the better current transport

Onoff current ratio with the variation of the thickness ofthe Re-SD region is shown in Figure 11 It shows the higheronoff current ration at zero Re-SD thickness and lower at100 nm thickness Since at 0 nm thickness the resistance valueof the MOSFET is increased So the thickness is slightly in-creased to optimize between resistance and current It alsoshows the 2ndash10 better onoff current ratio for the TMGRe-SD structure Figure 12 represents the graph of subthresholdslope at different values of channel length As shown in thegraph the subthreshold value is decreased towards higherchannel length +e value of subthreshold slope is approxi-mately 70mVdec at a higher channel length It increases at alower value due to high leakage It also shows the lower valuefor TMG as compared to DMG and SMG Re-SD SOIMOSFET +ere is 05-6 decrease in the subthreshold slopefor TMG as compared to DMG Re-SD Figure 13 presentsthe subthreshold slope with the variation of oxide thicknessat 90 nm channel length As shown in the graph the sub-threshold value is decreased by decreasing oxide thickness+e subthreshold value is between 60 and 73mVdecwhich is approximately close to the ideal value of70mVdec Subthreshold slope for TMG is lower than thatfor DMG and SMG Re-SD structures which show thatTMG is better immune to SCEs than DMG and SMG It isobserved that 07ndash15 reduction in the subthreshold slopefor TMG Re-SD SOI MOSFET Subthreshold slope withthe variation of Re-SD thickness is represented in Fig-ure 14 As shown in the graph the subthreshold value islower for 0 nm Re-SD thickness but it increases the seriesresistance of the MOSFET +e subthreshold value for100 nm thickness is higher So Re-SD thickness is kept inbetween to optimize between resistance and SCEs ie at30 nm It also shows the 001ndash03 better results for theTMG Re-SD device as compared to others

30 times 10ndash4

25 times 10ndash4

20 times 10ndash4

15 times 10ndash4

10 times 10ndash4

Dra

in cu

rren

t (A

μm

)

50 times 10ndash5

00

00 02

SMGDMGTMG

04Gate voltage (V)

06 08 10

Figure 8 Drain current versus gate voltage for SMG DMG andTMG Re-SD SOI MOSFET

I onI o

ff

40 times 108

35 times 108

30 times 108

25 times 108

20 times 108

15 times 108

10 times 108

50 times 107

00

SMGDMGTMG

Channel length (nm)40 50 60 70 80 90 100

Figure 9 IonIoff at various channel lengths for SMG DMG andTMG Re-SD SOI MOSFET

16 times 109

14 times 109

12 times 109

10 times 109

80 times 108

I onI o

ff

60 times 108

40 times 108

20 times 108

00

SMGDMGTMG

10 15 20Oxide thickness (nm)

25 30

Figure 10 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus oxide thickness

6 Journal of Nanotechnology

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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Hindawiwwwhindawicom Volume 2018

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ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

between the threshold voltage at drain to the source voltagevalue of 01 V and 005V It has been observed that DIBL isminimized by increasing the thickness of recessed-sourcedrain thickness

42 Electrostatic Performance +e graph of drain currentversus gate voltage for single double and TMG Re-SD SOIMOSFET is shown in Figure 8 +is graph reveals that thedrain current is better in the case of TMG+is high currentis due to high electric field which results from three gatemetals +e increment in the electric field at the edge of

metals accelerates the carriers which automatically en-hances the transport efficiency of the carriers+ere is 3ndash17enhancement in the drain current for TMG recessed-SDMOSFET However this signifies a lesser change as com-pared to SMG and DMGMoreover it is well known that theon-current behaviour of all the three devices depends uponrecessed-SD structure +is is the reason that all the threedevices have almost the same on current behaviour due torecessed-SD and due to the TMG structure electrostaticcharacteristics such as off-state leakage threshold voltageand DIBL will be improved Figure 9 represents the onoffcurrent ratio with respect to channel length It shows that the

Thre

shol

d vo

ltage

(V)

04

03

02

01

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 4+reshold voltage for different values of recessed-sourcedrain thickness

Thre

shol

d vo

ltage

(V)

04

03

02

01

ΦM1= 477eV ΦM2

= 44eV ΦM3= 41eV

ΦM1= 48eV ΦM2

= 46eV ΦM3= 44eV

ΦM1= 485eV ΦM2

= 47eV ΦM3= 454eV

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 5 +reshold voltage for different sets of values of workfunctions for TMG Re-SD SOI MOSFET

010

008

006

004DIB

L (V

V)

002

000

0 20 40 60 80Channel length (nm)

100 120 140 160

L1L2L3 = 12 3L1L2L3 = 11 1L1L2L3 = 32 1

Lines modelSymbols Atlas

Figure 6 DIBL for the different ratios of control gate and screengates of the TMG device

DIB

L (V

V)

012

008

010

006

004

002

000

trsd = 0nmtrsd = 30nmtrsd = 100nm

Symbols AtlasLines model

0 50 100 150Channel length (nm)

200 250 300

Figure 7 DIBL for the different values of recessed-sourcedrainthickness

Journal of Nanotechnology 5

switching (IonIoff) current ratio is higher for TMG thanDMG and SMG +e peaks in the electric field are increaseddue to the two interface of metal gate So the currenttransport efficiency becomes better in comparison to dualand single-metal gate Onoff current ratio is increased bythe increasing gate length As compared to studied DMGRe-SD there is 3ndash17 improvement in the onoff current ratioin TMG Figure 10 is the graph of the onoff current ratio at adifferent value of oxide thickness As shown in the graph onoff current ratio is larger for a small value of oxide thicknessWhen the thickness is increased onoff current ratio isdecreased It is due to the enhancement of on current ascompared to off current It presents the better currenttransport at a small oxide region thickness IonIoff current

ratio for the TMG Re-SD device is better as compared toDMG and SMG due to the better current transport

Onoff current ratio with the variation of the thickness ofthe Re-SD region is shown in Figure 11 It shows the higheronoff current ration at zero Re-SD thickness and lower at100 nm thickness Since at 0 nm thickness the resistance valueof the MOSFET is increased So the thickness is slightly in-creased to optimize between resistance and current It alsoshows the 2ndash10 better onoff current ratio for the TMGRe-SD structure Figure 12 represents the graph of subthresholdslope at different values of channel length As shown in thegraph the subthreshold value is decreased towards higherchannel length +e value of subthreshold slope is approxi-mately 70mVdec at a higher channel length It increases at alower value due to high leakage It also shows the lower valuefor TMG as compared to DMG and SMG Re-SD SOIMOSFET +ere is 05-6 decrease in the subthreshold slopefor TMG as compared to DMG Re-SD Figure 13 presentsthe subthreshold slope with the variation of oxide thicknessat 90 nm channel length As shown in the graph the sub-threshold value is decreased by decreasing oxide thickness+e subthreshold value is between 60 and 73mVdecwhich is approximately close to the ideal value of70mVdec Subthreshold slope for TMG is lower than thatfor DMG and SMG Re-SD structures which show thatTMG is better immune to SCEs than DMG and SMG It isobserved that 07ndash15 reduction in the subthreshold slopefor TMG Re-SD SOI MOSFET Subthreshold slope withthe variation of Re-SD thickness is represented in Fig-ure 14 As shown in the graph the subthreshold value islower for 0 nm Re-SD thickness but it increases the seriesresistance of the MOSFET +e subthreshold value for100 nm thickness is higher So Re-SD thickness is kept inbetween to optimize between resistance and SCEs ie at30 nm It also shows the 001ndash03 better results for theTMG Re-SD device as compared to others

30 times 10ndash4

25 times 10ndash4

20 times 10ndash4

15 times 10ndash4

10 times 10ndash4

Dra

in cu

rren

t (A

μm

)

50 times 10ndash5

00

00 02

SMGDMGTMG

04Gate voltage (V)

06 08 10

Figure 8 Drain current versus gate voltage for SMG DMG andTMG Re-SD SOI MOSFET

I onI o

ff

40 times 108

35 times 108

30 times 108

25 times 108

20 times 108

15 times 108

10 times 108

50 times 107

00

SMGDMGTMG

Channel length (nm)40 50 60 70 80 90 100

Figure 9 IonIoff at various channel lengths for SMG DMG andTMG Re-SD SOI MOSFET

16 times 109

14 times 109

12 times 109

10 times 109

80 times 108

I onI o

ff

60 times 108

40 times 108

20 times 108

00

SMGDMGTMG

10 15 20Oxide thickness (nm)

25 30

Figure 10 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus oxide thickness

6 Journal of Nanotechnology

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

switching (IonIoff) current ratio is higher for TMG thanDMG and SMG +e peaks in the electric field are increaseddue to the two interface of metal gate So the currenttransport efficiency becomes better in comparison to dualand single-metal gate Onoff current ratio is increased bythe increasing gate length As compared to studied DMGRe-SD there is 3ndash17 improvement in the onoff current ratioin TMG Figure 10 is the graph of the onoff current ratio at adifferent value of oxide thickness As shown in the graph onoff current ratio is larger for a small value of oxide thicknessWhen the thickness is increased onoff current ratio isdecreased It is due to the enhancement of on current ascompared to off current It presents the better currenttransport at a small oxide region thickness IonIoff current

ratio for the TMG Re-SD device is better as compared toDMG and SMG due to the better current transport

Onoff current ratio with the variation of the thickness ofthe Re-SD region is shown in Figure 11 It shows the higheronoff current ration at zero Re-SD thickness and lower at100 nm thickness Since at 0 nm thickness the resistance valueof the MOSFET is increased So the thickness is slightly in-creased to optimize between resistance and current It alsoshows the 2ndash10 better onoff current ratio for the TMGRe-SD structure Figure 12 represents the graph of subthresholdslope at different values of channel length As shown in thegraph the subthreshold value is decreased towards higherchannel length +e value of subthreshold slope is approxi-mately 70mVdec at a higher channel length It increases at alower value due to high leakage It also shows the lower valuefor TMG as compared to DMG and SMG Re-SD SOIMOSFET +ere is 05-6 decrease in the subthreshold slopefor TMG as compared to DMG Re-SD Figure 13 presentsthe subthreshold slope with the variation of oxide thicknessat 90 nm channel length As shown in the graph the sub-threshold value is decreased by decreasing oxide thickness+e subthreshold value is between 60 and 73mVdecwhich is approximately close to the ideal value of70mVdec Subthreshold slope for TMG is lower than thatfor DMG and SMG Re-SD structures which show thatTMG is better immune to SCEs than DMG and SMG It isobserved that 07ndash15 reduction in the subthreshold slopefor TMG Re-SD SOI MOSFET Subthreshold slope withthe variation of Re-SD thickness is represented in Fig-ure 14 As shown in the graph the subthreshold value islower for 0 nm Re-SD thickness but it increases the seriesresistance of the MOSFET +e subthreshold value for100 nm thickness is higher So Re-SD thickness is kept inbetween to optimize between resistance and SCEs ie at30 nm It also shows the 001ndash03 better results for theTMG Re-SD device as compared to others

30 times 10ndash4

25 times 10ndash4

20 times 10ndash4

15 times 10ndash4

10 times 10ndash4

Dra

in cu

rren

t (A

μm

)

50 times 10ndash5

00

00 02

SMGDMGTMG

04Gate voltage (V)

06 08 10

Figure 8 Drain current versus gate voltage for SMG DMG andTMG Re-SD SOI MOSFET

I onI o

ff

40 times 108

35 times 108

30 times 108

25 times 108

20 times 108

15 times 108

10 times 108

50 times 107

00

SMGDMGTMG

Channel length (nm)40 50 60 70 80 90 100

Figure 9 IonIoff at various channel lengths for SMG DMG andTMG Re-SD SOI MOSFET

16 times 109

14 times 109

12 times 109

10 times 109

80 times 108

I onI o

ff

60 times 108

40 times 108

20 times 108

00

SMGDMGTMG

10 15 20Oxide thickness (nm)

25 30

Figure 10 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus oxide thickness

6 Journal of Nanotechnology

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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Submit your manuscripts atwwwhindawicom

+e performances of the parameters are compared inTable 2 Table 2 is shown for 90 nm channel length in whichthreshold voltage has been approximately 14 improved forthe TMG structure+ere is 04ndash08 improvement in DIBLand subthreshold slope for TMG Re-SD as compared toothers which shows better immunity to SCEs For TMG Re-SD MOSFET it is observed to approximate 6 improve-ment in onoff current ratio and approximate 3 en-hancement in transconductance It shows that TMG Re-SDMOSFET has superior current driving ability as comparedto others

Also it is necessary to examine charge distribution at theinterfaces of the three metal gates As in the channel uniformcharge density has been assumed for the modeling of the

SMGDMGTMG

40

120

110

100

90

80

Subt

hres

hold

slop

e (m

VD

ec)

70

6050 60 8070

Channel length (nm)90 100

Figure 12 Subthreshold slope at a different channel length forSMG DMG and TMG Re-SD SOI MOSFET

SMGDMGTMG

72

70

68

Subt

hres

hold

slop

e (m

VD

ec)

66

64

10 15 20Oxide thickness (nm)

25 30

Figure 13 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus oxide thickness at 90 nm channel length

SMGDMGTMG

Recessed sourcedrain thickness (nm)

68

67

66

Subt

hres

hold

slop

e (m

VD

ec)

65

64200 806040 100

Figure 14 Subthreshold slope for SMG DMG and TMG Re-SDSOI MOSFET versus Re-SD thickness

Table 2 Performance comparison of SMG DMG and TMG Re-SD SOI MOSFET

Parameters SMGRe-SD

DMGRe-SD

TMGRe-SD

+reshold voltage (V) 0284 0379 0432DIBL (mVV) 248 246 245Subthreshold slope(mVdec) 681 675 669

IonIoff 2052times108 3316times108 3537times108

Transconductance(Smicrom) 5559times10minus4 5903times10minus4 6041times 10minus4

I onI o

ff

8 times 108

7 times 108

6 times 108

5 times 108

4 times 108

3 times 108

2 times 108

SMGDMGTMG

Recessed sourcedrain thickness (nm)0 20 40 60 80 100

Figure 11 IonIoff for SMG DMG and TMGRe-SD SOIMOSFETversus Re-SD thickness

Journal of Nanotechnology 7

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

proposed device+e plot of carrier concentration vs positionalong the channel is shown in Figure 15 It is clear from theplot that the device offers almost uniform charge density inthe channel and even all the metal interfaces have equalcharge distribution+e uniform charge density of 1925 cmminus3and 1940 cmminus3 is observed at the first and second metalinterfaces respectively +ese performance features of TMGRe-SD FD SOI MOSFET have made it a suitable candidatefor the analysis and design of todayrsquos low-power integratedcircuits (ICs) In the next section an attempt has beenmade toanalyze the studied device performance in digital circuitry

5 Design and Analysis of Pseudo-NMOS Inverter

Recently pseudo-NMOS inverter has been accepted as thefaster design as compared to the conventional inverter [23]Here TMG Re-SD FD SOI MOSFET-based pseudo-NMOSinverter is designed by using PMOS and NMOS pairs asshown in Figure 16 PMOS transistor is connected as pull-upload in which its gate is connected permanently to groundSince it is not driven by any signals it is always in the ONcondition NMOS is used as pull-down or driver circuit Itsgate is connected with input signals It is equivalent to theoperation of NMOS technology in the depletion mode So itis called pseudo-NMOS In this circuit PMOS works in thelinear region so it has low resistance and hence low timeconstant However NMOS works in the subthreshold regiondue to which it is fastest among other CMOS logic It has theadvantage of less area and high speed but also it has thedisadvantage of significant static power consumption

+e voltage transfer characteristics (VTC) of pseudo-NMOS inverter for TMG DMG and SMG recessed-SD FDSOI MOSFETare shown in Figure 17 One can observe fromthe plot that the switching distance of TMG Re-SDMOSFET is less as compared to DMG and SMG Re-SDMOSFET +e TMG offers better characteristics due to thehigher threshold and lesser threshold voltage variability ascompared to DMG and SMG Re-SD FD SOI MOSFETs+is will directly affect the noise immunity levels of SMGand DMG as compared to the TMG structure So theperformance of TMG Re-SD-based pseudo-NMOS is betteras it responds rapidly Furthermore in order to analyze thescaling constraints versus switching characteristics of theTMG Re-SD FD SOI MOSFET this has been scaled downto 45 nm

+e VTC curve of the pseudo-NMOS inverter for TMGRe-SD MOSFET at various channel lengths is shown inFigure 18 In short channel devices barrier for electroninjection from source to channel reduces due to overlappingof source and drain depletion regions It leads to reducedthreshold voltage At the lower threshold voltage NMOStransistor turns on earlier than the one with higher thresholdvoltage Similarly the PMOS transistor takes time to turn offSo the switching distance is increased So threshold voltagevaries with channel length It reduces by reducing thechannel length of the device+erefore switching distance islarge for a smaller channel length It is clear from the plotthat the device resembles the inverter characteristics even if

it is scaled down to 45 nmMoreover the performance of theinverter at 90 nm channel length of TMG Re-SD MOSFETis found to be better as its characteristics tend towards theideal value and switching is faster So we have analyzed thedevice further at 90 nm channel length for its transientbehaviour

+e transient analysis of pseudo-NMOS inverter forTMG Re-SD FD SOI MOSFET is presented in Figure 19 at90 nm channel length In the transient analysis input voltagehas been given in pulse waveform with 0 to 1V amplitudeand 10 ps of cycle As the supply voltage given in the inverteris 1V output voltage waveform switches between 0 and 1V+e graph itself shows the inversion characteristics for inputand output voltage and the propagation delay between inputand output switching is observed When the output goes lowto high value the delay ie τplh is observed as 059 ps andwhen the output goes high to low output the delay ie τphlis observed as 027 ps As the total propagation delay of the

000 002 004Position along channel length (nm)

006 008

Log

of ca

rrie

r con

cent

ratio

n (c

mndash3

)

202

200

198

196

194

192

190

ФM1= 48eV ФM2

= 46eV ФM3= 44eV

L = 90nm tsi = 10nm tox = 2nm trsd = 30nmtbox = 200nm dbox = 3nm L1L2L3 = 1 1 1

Figure 15 Carrier concentration along the position of channellength for TMG Re-SD FD SOI MOSFET

VDD

Vout

Vin

PMOS

NMOS

C

Figure 16 Pseudo-NMOS inverter

8 Journal of Nanotechnology

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

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ria

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Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

pseudo-NMOS is the average of τphl and τplh the total delaycomes as 043 ps +e comparison with the previous liter-ature is shown in Table 3+is is very less for the circuit to beoperated faster and hence the studied device could beoptimized for high-speed applications

6 Conclusion

In this contribution design and analysis of recessed-SD SOI MOSFET-based pseudo-NMOS inverter hasbeen presented for low-power and high-speed applica-tions First a comparison of threshold voltage and

electrostatic performance has been discussed for single-metal double-metal and triple-metal gate recessed-sourcedrain (Re-SD) SOI MOSFET +e model for thresholdvoltage helps to optimize the SCEs for short channel devices+e gate of three materials which are laterally joined showsbetter immunity to SCEs and DIBL which is the majorconcern of SOI MOSFET +e accuracy of the analyticalmodel has been verified with the result of the two-dimensional TCAD simulator of Silvaco ATLAS and itshows good agreement with 05ndash1 error in results +ecomparison of threshold voltage indicates that the TMG-based device offers better immunity to SCEs than other Re-SD SOI MOSFETs as less roll off seen in case of TMG +eTMG device provides significant reduction in the DIBL effecteven if there are parameter variations +e enhancement inthe drain current reveals that the TMG is better than theDMG and SMG Re-SD SOI MOSFET in terms of current-driving capability+ese advanced features of the TMGdevicemade it a suitable candidate to further analyze it for highspeed switching applications For this a pseudo-NMOSinverter has been designed and simulated using TMGRe-SD FD SOI MOSFET It is found that the invertershows the excellent characteristics in case of TMG ascompared to others as the TMG device resembles almostideal VTC at Vdd 1 V +e transient analysis shows thatthe studied circuit allows very less propagation delay of043 ps So the device could be suggested for high-speedand low-power IC applications Moreover channel

00 02 04Input voltage (V)

06 08 10

00

02

04

06

08

10

Out

put v

olta

ge (V

)

L = 45nmL = 60nmL = 90nm

Figure 18 VTC curve of pseudo-NMOS for TMG Re-SD FD SOIMOSFET at different channel lengths

00 50 times 10ndash12 10 times 10ndash11

Time (s)15 times 10ndash11

00

02

04

06

VinVout

08

10

Volta

ge (V

)

Figure 19 Transient analysis of pseudo-NMOS for TMG Re-SDFD SOI MOSFET at 90 nm channel length

Table 3 Comparison of delay of inverters at 90 nm channel length

References Inverter delaySamanta et al [24] 031 nsSing et al [25] 943 psRodoni et al [26] 47 psProposed pseudo-NMOS 043 ps

00

00

02

04

06

08

10

02 04Input voltage (V)

Out

put v

olta

ge (V

)

06 08 10

SMG Re-SD MOSFETDMG Re-SD MOSFETTMG Re-SD MOSFET

Figure 17 Voltage transfer characteristic curve of pseudo-NMOSfor TMG DMG and SMG Re-SD FD SOI MOSFET

Journal of Nanotechnology 9

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

CorrosionInternational Journal of

Hindawiwwwhindawicom Volume 2018

Advances in

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Analytical ChemistryInternational Journal of

Hindawiwwwhindawicom Volume 2018

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Hindawiwwwhindawicom Volume 2018

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Advances in Condensed Matter Physics

Hindawiwwwhindawicom Volume 2018

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Hindawiwwwhindawicom Volume 2018

High Energy PhysicsAdvances in

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

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BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

engineering and the analysis of analog and high-frequencyperformances can be the future work of this device

Appendix

A Derived Coefficients of FrontThreshold Voltage

as Q2

s1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Qs1

Gs1

Qs2

Gs2

2re

ns+

Qs1

Gs1

Qs3

Gs3

2rf

ns

(A1)

bs 2Ps1Qs1

G2s1

2r +2rd

nsminus 51113888 1113889 +

Ps1Qs2 + Ps2Qs1

Gs1Gs2

2re

ns

+Ps1Qs3 + Ps3Qs1

Gs1Gs3

2rf

ns+

Qs2

Gs2

2reVbi

ns+

Qs3

Gs3

2rfVbi

ns

+Qs1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889

(A2)

cs P2s1

G2s1

2r +2rd

nsminus 51113888 1113889

+Ps1

Gs1

2rg

ns+2rdVbi

nsminus 8Vbi minus 4emptyFsi1113888 1113889 +

Ps1

Gs1

Ps2

Gs2

2re

ns

+Ps1

Gs1

Ps3

Gs3

2rf

ns+

Ps2

Gs2

2reVbi

ns+

Ps3

Gs3

2rfVbi

ns+2rgVbi

ns

minus 4 V2bi +empty2Fsi1113872 1113873

(A3)

Ps1 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd2C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox1C1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

+VFB1 middot 2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1( 1113857

t2si 1 + 2Csi1C1( 1113857( 1113857

(A4)

Qs1 minus2 Csi1 + C1( 1113857Cox1( 1113857C1 middot Csi1

t2si 1 + 2Csi1C1( 1113857( 1113857 (A5)

Ps2 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd3C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd4C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox2C2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

+VFB2 middot 2 Csi2 + C2( 1113857Cox2C2 middot Csi2( 1113857

t2si 1 + 2Csi2C2( 1113857( 1113857

(A6)

Qs2 minus2 Csi2 + C2( 1113857Cox2( 1113857C2 middot Csi2

t2si 1 + 2Csi2C2( 1113857( 1113857 (A7)

Ps3 qNa

εsiminus

VS minusVFB4( 1113857 middot 2Crsd5C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVD minusVFB4( 1113857 middot 2Crsd6C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

minusVsub minusVFB5( 1113857 middot 2Cbox3C3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

+VFB3 middot 2 Csi3 + C3( 1113857Cox3C3 middot Csi3( 1113857

t2si 1 + 2Csi3C3( 1113857( 1113857

(A8)

Qs3 minus2 Csi3 + C3( 1113857Cox3( 1113857C3 middot Csi3

t2si 1 + 2Csi3C3( 1113857( 1113857 (A9)

d g

Vbiminus λf1λf2coth λf1L1( 1113857coth λf2L2( 1113857

minus λf1λf3coth λf1L1( 1113857coth λf3L3( 1113857

(A10)

e λf2λf3cosech λf2L2( 1113857coth λf3L3( 1113857

minus λf2λf3coth λf2L2( 1113857coth λf3L3( 1113857minus λ2f2(A11)

f minusλf2λf3cosech (A12)

g Vbi( λf1λf2cosech λf1L1( 1113857coth λf2L2( 1113857

+ λf1λf3cosech λf1L1( 1113857coth λf3L3( 1113857

+ λf2λf3cosech λf2L2( 1113857cosech λf3L3( 11138571113857

(A13)

r coth λf1L1( 1113857cosech λf1L1( 1113857 + cosech2 λf1L1( 1113857 (A14)

+e values of Gs1 Gs2 Gs3 ns λf1 λf2 and λf3 are takenfrom [17]

B Derived Coefficients of BackThreshold Voltage

ab Q2

b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Qb1

Gb1

Qb2

Gb2

2rprimeeprimens

+Qb1

Gb1

Qb3

Gb3

2rprimefprimenb

(B1)

bb 2Pb1Qb1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889 +

Pb1Qb2 + Pb2Qb1

Gb1Gb2

2rprimeeprimenb

+Pb1Qb3 + Pb3Qb1

Gb1Gb3

2rprimefprimenb

+Qb1

Gb1

⎛⎝2rprimegprime

nb+2rprimedprimeVbi

nb

minus 8Vbi minus 4emptyFsi⎞⎠ +

Qb2

Gb2

2rprimeeprimeVbi

nb+

Qb3

Gb3

2rprimefprimeVbi

nb

(B2)

10 Journal of Nanotechnology

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

CorrosionInternational Journal of

Hindawiwwwhindawicom Volume 2018

Advances in

Materials Science and EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Journal of

Chemistry

Analytical ChemistryInternational Journal of

Hindawiwwwhindawicom Volume 2018

ScienticaHindawiwwwhindawicom Volume 2018

Polymer ScienceInternational Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Advances in Condensed Matter Physics

Hindawiwwwhindawicom Volume 2018

International Journal of

BiomaterialsHindawiwwwhindawicom

Journal ofEngineeringVolume 2018

Applied ChemistryJournal of

Hindawiwwwhindawicom Volume 2018

NanotechnologyHindawiwwwhindawicom Volume 2018

Journal of

Hindawiwwwhindawicom Volume 2018

High Energy PhysicsAdvances in

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

TribologyAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

ChemistryAdvances in

Hindawiwwwhindawicom Volume 2018

Advances inPhysical Chemistry

Hindawiwwwhindawicom Volume 2018

BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

cb P2b1

G2b1

2rprime +2rprimedprime

nbminus 51113888 1113889

+Pb1

Gb1

2rprimegprimenb

+2rprimedprime

Vbi

nbminus 8Vbi minus 4emptyFsi

⎛⎝ ⎞⎠

+Pb1

Gb1

Pb2

Gb2

2rprimeeprimenb

+Pb1

Gb1

Pb3

Gb3

2rprimefprimenb

+Pb2

Gb2

2rprimeeprimeVbi

nb

+Pb3

Gb3

2rprimefprimeVbi

nb+2rprimegprime

Vbi

nbminus 4 V

2bi +empty2Fsi1113872 1113873

(B3)

Pb1 qNa

εsiminus 2( minusVFB1( 1113857 + VS minusVFB4( 11138571113858 Crsd1Cox1( 1113857

+ Crsd1Csi1( 11138571113859 + VD minusVFB4( 11138571113858 Crsd2Cox1( 1113857

+ Crsd2Csi1( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox1Cox1( 1113857

+ Cbox1Csi1( 111385711138591113857 times t2si 1 + 2Csi1Cox1( 1113857( 11138571113872 1113873

minus1

(B4)

Qb1 minus2

t2si 1 + 2Csi1Cox1( 1113857( 1113857 (B5)

Pb2 qNa

εsiminus 2( minusVFB2( 1113857 + VS minusVFB4( 11138571113858 Crsd3Cox2( 1113857

+ Crsd3Csi2( 11138571113859 + VD minusVFB4( 11138571113858 Crsd4Cox2( 1113857

+ Crsd4Csi2( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox2Cox2( 1113857

+ Cbox2Csi2( 111385711138591113857 times t2si 1 + 2Csi2Cox2( 1113857( 11138571113872 1113873

minus1

(B6)

Qb2 minus2

t2si 1 + 2Csi2Cox2( 1113857( 1113857 (B7)

Pb3 qNa

εsiminus 2( minusVFB3( 1113857 + VS minusVFB4( 11138571113858 Crsd5Cox3( 1113857

+ Crsd5Csi3( 11138571113859 + VD minusVFB4( 11138571113858 Crsd6Cox3( 1113857

+ Crsd6Csi3( 11138571113859 + Vsub minusVFB5( 11138571113858 Cbox3Cox3( 1113857

+ Cbox3Csi3( 111385711138591113857 times t2si 1 + 2Csi3Cox3( 1113857( 11138571113872 1113873

minus1

(B8)

Qb3 minus2

t2si 1 + 2Csi3Cox3( 1113857( 1113857 (B9)

dprime gprimeVbiminus λb1λb2coth λb1L1( 1113857coth λb2L2( 1113857

minus λb1λb3coth λb1L1( 1113857coth λb3L3( 1113857

(B10)

eprime λb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857

minus λb2λb3coth λb2L2( 1113857coth λb3L3( 1113857minus λ2b2(B11)

fprime minusλb2λb3cosech λb2L2( 1113857coth λb3L3( 1113857 (B12)

gprime Vbi( λb1λb2cosech λb1L1( 1113857coth λb2L2( 1113857

+ λb1λb3cosech λb1L1( 1113857coth λb3L3( 1113857

+ λb2λb3cosech λb2L2( 1113857cosech λb3L3( 11138571113857

(B13)

rprime coth λb1L1( 1113857cosech λb1L1( 1113857 + cosech2 λb1L1( 1113857 (B14)

+e values of Gb1 Gb2 Gb3 nb λb1 λb2 and λb3 are takenfrom [17]

Data Availability

+e data used to support the findings of this study are in-cluded within the article

Conflicts of Interest

+e authors declare that there are no conflicts of interestregarding the publication of this paper

Acknowledgments

+is work was supported with the resources of VLSI Lab-oratory of MNNIT Allahabad under Special ManpowerDevelopment Programme Chip to System Design (SMDP-C2SD) project funded by MeitY Govt of India

References

[1] R D Isaac ldquo+e future of CMOS technologyrdquo IBM Journalof Research and Development vol 44 no 3 pp 369ndash3782000

[2] E J Novak ldquoMaintaining the benefits of CMOS scaling whenscaling bogs downrdquo IBM Journal of Research and Develop-ment vol 46 no 2-3 pp 169ndash180 2002

[3] W H Krautscheider A Kohlhase and H Terlezki ldquoScalingand reliability problems of gigabit CMOS circuitsrdquo Micro-electronics Reliability vol 37 no 1 pp 19ndash37 1997

[4] V Narendar and R A Mishra ldquoAnalytical modeling andsimulation of multigate FinFET devices and the impact ofhigh-k dielectrics on short channel effects (SCEs)rdquo Super-lattices and Microstructures vol 85 pp 357ndash369 2015

[5] P Agarwal G Saraswat and M J Kumar ldquoCompact surfacepotential model for FD SOI MOSFET considering substratedepletion regionrdquo IEEE Transactions on Electron Devicesvol 55 no 3 pp 789ndash795 2008

[6] J P Colinge ldquo+e new Generation of SOI MOSFETsrdquo Ro-manian Journal of Information Science and Technologyvol 11 no 1 pp 3ndash15 2008

[7] H Shang and M H White ldquoAn ultra-thin midgap gateFDSOI MOSFETrdquo Solid-State Electronics vol 44 pp 1621ndash1625 2008

[8] D Flandre J P Colinge J Chen D D CeusterJ P Eggermont and L Ferreira ldquoFully depleted SOI CMOStechnology for low-voltage low-power mixed digitalanalogmicrowave circuitsrdquo AAnalog Integrated Circuits and SignalProcessing vol 21 pp 213ndash228 1999

Journal of Nanotechnology 11

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

CorrosionInternational Journal of

Hindawiwwwhindawicom Volume 2018

Advances in

Materials Science and EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Journal of

Chemistry

Analytical ChemistryInternational Journal of

Hindawiwwwhindawicom Volume 2018

ScienticaHindawiwwwhindawicom Volume 2018

Polymer ScienceInternational Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Advances in Condensed Matter Physics

Hindawiwwwhindawicom Volume 2018

International Journal of

BiomaterialsHindawiwwwhindawicom

Journal ofEngineeringVolume 2018

Applied ChemistryJournal of

Hindawiwwwhindawicom Volume 2018

NanotechnologyHindawiwwwhindawicom Volume 2018

Journal of

Hindawiwwwhindawicom Volume 2018

High Energy PhysicsAdvances in

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

TribologyAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

ChemistryAdvances in

Hindawiwwwhindawicom Volume 2018

Advances inPhysical Chemistry

Hindawiwwwhindawicom Volume 2018

BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

[9] Z Zhang S Zhang and M Chan ldquoSelf-align recesed sourcedrain Ultrthin body SOI MOSFETrdquo IEEE Electron DeviceLetters vol 25 no 11 2004

[10] C G AhnW J Cho K Im J H Yang and I B Baek ldquo30-nmRecessed SD SOI MOSFETwith an ultrathin body and a lowSDE resistancerdquo IEEE Electron Device Letters vol 26 no 7pp 486ndash488 2005

[11] B Sivilicic V Jovanovic and T Suligoj ldquoAnalytical models offront and back-gate potential distribution and threshold-voltage for recessed sourcedrain UTB SOI MOSFETsrdquoSolid State Electron vol 53 no 5 pp 540ndash547 2009

[12] M Saxena S Haldar M Gupta and R S Gupta ldquoPhysics-based analytical modeling of potential and electrical fielddistribution in dual material gate (DMG)-MOSFET for im-proved hot electron effect and carrier transport efficiencyrdquoIEEE Transactions on Electron Devices vol 49 no 11pp 1928ndash1938 2002

[13] N Vadthiya S Rai S Tiwari and R A Mishra ldquoA two-dimensional (2D) analytical subthreshold swing and trans-conductance model of underlap dual-material double-gate(DMDG) MOSFET for analogRF applicationsrdquo Super-lattices and Microstructures vol 100 pp 274ndash289 2016

[14] D B Chandar N Vadthiya A Kumar and R A MishraldquoSuppression of short channel effects (SCEs) by dual materialgate vertical surrounding gate (DMGVSG) MOSFET 3-DTCAD simulationrdquo Procedia Engineering vol 64 pp 125ndash132 2013

[15] E Takeda C Y-W Yang and A M Hamada Hot-CarrierEffects in MOS Devices Academic Press Cambridge MAUSA 1995

[16] G K Saramekala A Santra S Dubey S Jit and P K TiwarildquoAn analytical threshold voltage model for a short-channeldual-metal-gate (DMG) recessed-sourcedrain (Re-SD) SOIMOSFETrdquo Superlattices and Microstructures vol 60pp 580ndash595 2013

[17] A Priya and R A Mishra ldquoA two dimensional analyticalmodeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-SourceDrain (Re-SD) SOI MOSFETrdquoSuperlattices and Microstructures vol 92 pp 316ndash329 2016

[18] K Goel M Saxena M Gupta and R S Gupta ldquoModelingand simulation of a nanoscale three-region tri-material gatestack (TRIMGAS) MOSFET for improved carrier transportefficiency and reduced hot-electron effectsrdquo IEEE Trans-actions on Electron Devices vol 53 no 7 pp 1623ndash16332006

[19] P Ghosh S Haldar R S Gupta andM Gupta ldquoAn analyticaldrain current model for dual material engineered cylindricalsurrounded gate MOSFETrdquo Microelectronics Journal vol 43no 1 pp 17ndash24 2012

[20] M A Mahmud and S Subrina ldquoA two dimensional analyticalmodel of drain to source current and subthreshold slope of atriple material double gate MOSFETrdquo in Proceedings of In-ternational Conference on Electrical and Computer Engi-neering pp 92ndash95 IEEE Dhaka Bangladesh December 2014

[21] R Kumar and V K Pandey ldquoLow power combinationalcircuit based on psuedo NMOS logicrdquo International Journal ofEnhanced Research in Science Technology and Engineeringvol 3 no 3 pp 452ndash457 2014

[22] Atlas Userrsquos Manual Silvaco International Santa Clara CAUSA 2014

[23] N Subba A Salman S Mitra D E Loannou and C TretzldquoPseudo-nMOS revisited Impact of SOI on low power highspeed circuit designrdquo in Proceedings of IEEE International SOIConference Procee pp 26-27 Wakefield MA USA 2000

[24] J Samanta B P De B Bag and R K Maity ldquoComparativestudy for delay and power dissipation of CMOS Inverter inUDSM rangerdquo International Journal of Soft Computing andEngineering vol 1 no 6 pp 162ndash167 2012

[25] A K Singh J Samanta and J Bhaumik ldquoModified IndashVmodelfor delay analysis of UDSM CMOS circuitsrdquo in Proceedings ofInternational Conference on Communications Devices andIntelligent Systems pp 357ndash360 IEEE Kolkata India De-cember 2012

[26] L C Rodoni F Ellinger and H Jackel ldquoUltrafast CMOSinverter with 47 ps gate delay facbricated on 90 nm SOItechnologyrdquo Electronics Letter vol 40 no 20 2004

12 Journal of Nanotechnology

CorrosionInternational Journal of

Hindawiwwwhindawicom Volume 2018

Advances in

Materials Science and EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Journal of

Chemistry

Analytical ChemistryInternational Journal of

Hindawiwwwhindawicom Volume 2018

ScienticaHindawiwwwhindawicom Volume 2018

Polymer ScienceInternational Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Advances in Condensed Matter Physics

Hindawiwwwhindawicom Volume 2018

International Journal of

BiomaterialsHindawiwwwhindawicom

Journal ofEngineeringVolume 2018

Applied ChemistryJournal of

Hindawiwwwhindawicom Volume 2018

NanotechnologyHindawiwwwhindawicom Volume 2018

Journal of

Hindawiwwwhindawicom Volume 2018

High Energy PhysicsAdvances in

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

TribologyAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

ChemistryAdvances in

Hindawiwwwhindawicom Volume 2018

Advances inPhysical Chemistry

Hindawiwwwhindawicom Volume 2018

BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom

CorrosionInternational Journal of

Hindawiwwwhindawicom Volume 2018

Advances in

Materials Science and EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Journal of

Chemistry

Analytical ChemistryInternational Journal of

Hindawiwwwhindawicom Volume 2018

ScienticaHindawiwwwhindawicom Volume 2018

Polymer ScienceInternational Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Advances in Condensed Matter Physics

Hindawiwwwhindawicom Volume 2018

International Journal of

BiomaterialsHindawiwwwhindawicom

Journal ofEngineeringVolume 2018

Applied ChemistryJournal of

Hindawiwwwhindawicom Volume 2018

NanotechnologyHindawiwwwhindawicom Volume 2018

Journal of

Hindawiwwwhindawicom Volume 2018

High Energy PhysicsAdvances in

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

TribologyAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

ChemistryAdvances in

Hindawiwwwhindawicom Volume 2018

Advances inPhysical Chemistry

Hindawiwwwhindawicom Volume 2018

BioMed Research InternationalMaterials

Journal of

Hindawiwwwhindawicom Volume 2018

Na

nom

ate

ria

ls

Hindawiwwwhindawicom Volume 2018

Journal ofNanomaterials

Submit your manuscripts atwwwhindawicom