Design Optimization of System-On-Chip Platforms 2

7/31/2019 Design Optimization of System-On-Chip Platforms 2

1/15

Authored by Amirhosein Mosavi ,

Supervised by Professor Oniga Istvn,

University of Debrecen, 2011

Design Optimization of System-on-Chip PlatformsAuthored by Amirhosein Mosavi ,Supervised by Professor Oniga Istvn,Reports in Computer Science, University of Debrecen, Faculty of Informatics, 2011.


2/15

1. A brief Introduction to my thesis

2. Introduction to System-on-Chip(SoC)

3. Multiobjective Optimization design problem of SoC


3/15

1. The process of optimization in the engineering design is considered as avery important and in the same time complicated task for engineers to dealwith.

2. The problems of this type are mostly nonconvex, nonlinear andcomputationally expensive, including several conflicting objectives. Solvingmentioned design optimization problems, which mostly referred to black-

box optimization problems, is not a simple task.3. Black-box optimization problems with multiple objectives can be solved in

several different ways. And there have been more than hundredsalgorithms developed

4. However most of these algorithms, due to some difficulties related to theusage, havent been applicable

5. we introduced the challenges and suggested the solutions , in particular inshape optimization

6. we introduced the effective methods and evaluate them via real-lifestudycases


4/15

1. Number of variables2. Number of objectives

3. Visualizations for more than 3 objectives

4. RSM, an approximation to the actual problem

5. Efficient algorithms

6. Decision supports

7. Hybrid and parallel methods

Response to the challenge:

1. MOO packages2. Data mining


5/15


6/15


7/15

SoC is the integration of all components of a electronic

system into a single integrated circuit (chip).

It may contains digital, analog, mixed-signal, radio-frequency functions


8/15

According to the study case of STMicroelectronics, MULTICUBE Project

Typical Objectives:

1. Performance

2. Power

3. Area

It is a discrete, nonliner optimization problem with more than 1,500,000possible design points to evaluate


9/15

As engineers would prefer to pick up and utilize the simplest

technique.

1.They do it by try and error (STMicroelectronics FP7 project end

June 2010) after performing an statistical approach

2. Recently focused on multiobjective optimization, Design SpaceExploration utilizing Design of Experience(DoE); I would call it anoptimization assisted try and error method


10/15

1. Utilizing statistical method of Design Space Exploration(DSE) by a tool calledM3Explorer , just 5000 points are selected and evaluated by the ST computer

farm simulator faculties and a Pareto optimal solutions including 10,000 pointsare suggested( it took 3days)

2. Utilizing the Design of Experience (DoE) algorithms, From the abovesimulations results evaluated the design space is reduced from 10,000 to 500

utilizing ( DoE)


11/15


12/15


13/15


14/15


15/15

1. DoE algorithms for optimization reduced the complexity of the problemand reduced the design space for some levels

2. Utilizing further multiobjective optimization such as Response Surfacemodeling, EMO and the advanced visualization methods are beneficial andcould speed up the process of product to market

Documents

Design Optimization of System-On-Chip Platforms 2