Systems and Computers in Japan, Vol. 24, No, 5, 1993 Translated from Denshi Joho Tsushin Gakkai Ronbunshi, Vol. J75-D-11, No. 5, May 1992, pp. 305-313

Design of Testing Circuit and Test Generation for Built-in Current Testing

Yukiya Miura, Member

Faculty of Engineering, Osaka University, Suita-shi, 565 Japan

Yasushi Wada, Nonmember, and Kozo Kinoshita, Member

Faculty of Engineering, Osaka University, Suita, 565 Japan

SUMMARY

Recently current testing is beginning to be noticed as a testing method for CMOS circuits. However, since CMOS circuits cause the dynamic current due to switching, it has been pointed out that testing at a fast clock rate by current testing is difficult. To cope with this problem a built-in current testing circuit is proposed in this paper. It is a circuit which measures the value of the dynamic current integratedover a unit time. Next a test sequence generation method for the proposed circuit is presented. In this method test sequences are generated so that the numbers of changes in the gate output values for two consecutive test vectors are almost equal. As a result the dynamic current does not change much between consecutive vectors. Finally the results of test generation for ISCAS’85 benchmark circuits are shown.

Keywords: current testing, stuck-on faults, CMOS circuits, test generation.

1. Introduction

As the CMOS technology becomes the main stream of semiconductor integrated circuit technology, a number of faults which cannot be explained by the conventional stuck-at fault model have started appear- ing. Some of the examples of such faults are transistor

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stuck-open faults, stuck-on faults, and gate oxide short faults [l - 61. Many of those faults can often not be detected by the tests for the conventional stuck-at faults.

In a fault-free CMOS IC circuit very little current (called static current) flows when it is in a steady state. But when there is a fault of the type mentioned above including a stuck-at fault in the circuit, a very large static often flows. Thus by measuring the static current at the voltage source a CMOS circuit can be tested [2 - 81. This kind of test is called current testing or IDDQ

test. In general when a current is measured by an ex- ternal tester, it is difficult to measure the current at the inherent clock rate of the IC, because the load of the tester itself is larger than that of the IC and the output driver of the IC carries a relatively large current 19, 101. This problem is due to the difficulty in distin- guishing at the clock rate of the IC the static current from the current which flows when the output valuesof the gates change i.e. when switching (called dynamic current hereafter). Also a built in current testing method has been proposed [9, 111 which places a cir- cuit for measuring currents, so-called ammeter, in the IC. Though the operating clock of the proposed circuit is fast, since its operating margin is small, when the manufacturing fluctuations are considered, its fault detection capability is expected to decrease.

On the other hand in current testing the observa- tion point is only the voltage source terminal (VDD or

ISSN0882- 1666/93/0005-O073 0 1993 Scripta Technica, Inc.

GND). Thus it is sufficient to apply test vectors to excite the fault for testing. That is in the conventional test generation method for stuck-at faults based on the path sensitization, the excitation of a fault and the propagation of the fault information to the primary output are necessary. However in current testing only the excitation of a fault is necessary. Thus it is well known that the number of test vectors is smaller compared with the stuck-at fault tests [ 10,12 - 141. To cope with the problem mentioned above it has been proposed to slow the clock for current testing [4, 10, 12, 141. But when an IC circuit is tested at a clock rate slower than its inherent clock rate, stuck-open faults due to the charge distribution cannot always be detected.

In this paper a circuit for measuring the current including dynamic current that is a circuit for built-in current testing is proposed which measures the integral of the current over a unit time. In addition a test sequence generated here makes the numbers of transitions of the gate outputs almost equal between two consecutive vectors. In section 2. the fault model used, and in section 3. the proposed circuit for built-in current testing are explained, respectively. In section 4. the test sequence generation method and in section 5. the test generation algorithm and experimental results are presented.

In this paper CMOS combinational circuits consisting only of fully complementary CMOS basic gates (NOT, NOR, NAND) are considered, in which PMOS transistor circuits and nMOS transistor circuits are used in a dual manner. Also current testing of this paper is fundamentally different from the DC test in that a test vector is applied to detect a fault and the current is measured for each test vector.

2. Fault Model and Test Input

2.1. Fault model

The kind of faults that can be detected by measuring current are the ones which cause a large static current when a circuit is faulty. Thus in this paper the kind of fault considered is the one which is described by the fault model defined next.

Definition 1. A fault for which the logical value of the line is fixed at logical ''11'("0) is called a stuck-at-1 (0) fault of the line (SA-l(0)). When stuck-at-1 and stuck-at-0 are not distinguished, it is called a stuck-at fault (SAF).

Definition 2. If, irrespective of the value of the voltage at the gate terminal of a MOS transistor always conducts, then it is called a stuck-on fault (SONF).

Definition 3. A short between the gate terminal and the silicone substrate of a transistor is called a gate oxide short fault (GOSF).

Definition 4. If, when an input vector is applied to the primary input lines of a circuit with a fault, its effect appears in the circuit (an abnormal static current flows), then the fault is said to be excited. The input vector in that case is called a test vector for the fault. Also if test vectors must be applied in some order, then the set of the test vectors with the order is called a test sequence.

Stuck-open faults of transistors, open circuit faults, and short circuit faults are not considered in this paper. However some of the stuck-open faults of MOS transistors and the open circuit faults which cause the gate terminal of a transistor to float are reported to be detectable by current testing. Also in this paper tests are generated only for single faults. However when there are multiple faults, if they are excited, an abnormal current flows. Therefore current testing can also be applied to multiple faults [lo, 121.

2.2. Teat set

Conditions for detecting faults given in Definitions 1-3 by current testing are presented below.

Lemma 1. By applying logical value " 0 or "1" to each line all the SAF and GOSF can be detected by current testing.

Proof. From the fault model, if SA-1(0), then the voltage level of that line is VDD (GND). If the fault is GOSF between the gate terminal of nMOS(pM0S) and the substrate, then its gate terminal voltage is GND(VDD). Thus by applying the complementary voltage, that is the complement of its logical value, to this line, a conducting path between VDD and GND is formed and current testing becomes possible. Q.E.D.

Lemma 2. A test vector to detect a SONF in a gate is the same as the test vector to excite a SAF of the gate.

Proof. For a test vector to excite a SAF the gate output for the fault-free case is different from that for the faulty case. In a SONF the gate terminal of the transistor can be considered stuck at one of the logic

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values. If it is fault-free, either this transistor or its counterpart in the pair is on-state but not both. If it is faulty, then both of them are on-state. Hence, if a test vector for SAF is applied to the gate, SONF can be detected by current testing. Q.E.D.

Theorem 1. SAF, SONF and GOSF can be de- tected by applying test vectors for detecting SONF in a gate.

Proof. This follows from Lemmas 1 and 2. Q.E.D.

Based on Theorem 1 only tests for SONF are considered in this paper.

In Fig. 1 the correspondence between the test vectors for 2-input CMOS NAND gate and the faults detectable by them is shown.

3. Current Testing Circuit

It is desirable to measure the current for detecting faults at the inherent clock rate of the IC. However, when the current is measured using an external tester, because of the load of the system a certain amount of time is necessary to settle the current. Hence the IC must be tested at a considerably slower clock rate. Futhermore, because of sink and source currents (IoH IoL) between the output terminal and the tester the accurate measurement of the current is difficult. To solve these problems built-in testing circuits are con- sidered necessary [9, 101.

To have a testing circuit built in an IC circuit, the following properties must be satisfied.

(1) The voltage drop due to the testing circuit should be small.

(2) The resolution of the current to be measured should be high.

(3) The structure of the testing circuit should be simple.

(4) The area of the testing circuit should be small.

( 5 ) The performance degradation in the normal operation should be small.

In Fig. 2 the testing circuit proposed in this paper is shown. It consists of V-I Translator, Level Trans-

I u c

GND

(a) two-input CMOS NAND gate

A B SAF SONF GOSF(G-bulk)

NB, PA 0 1 Ai.Bo, Co NA NA. PB 1 0 Ao, Bi, Co NB

1 1 Ao. Bo. Ci PA, PB NA.NB

(b) Test set and detectable faults

Fig. 1. Test set for two-input NAND gate.

lator, and Integral Circuitry. In the normal operation

and in the testing operation NGND = Open, TGND = GND, Tmde = "1," TvDD = VDD. If it is fault-free, Tout = "1" and if faulty, To,, = "0." To satisfy ( 5 ) two GND terminals NGN, and TGND are provided.

NGND = TGND = GND, Tmde = "0," TvDD = VDD

Next the circuit operation is explained briefly. In the fault-free state only dynamic current flows in a CMOS logic circuit and there is very little static current. If there is no static current, Nodel = GND, N2 = OFF, Node2 = "1" holds and hence To,, = "1" holds. When a dynamic current flows, if V(Node1) 2 VT(N2), then Node2 = "0." Here V(X) represents the voltage at node X and VdY) represents the threshold voltage of transistor Y. But if Node2 = " 0 holds for a sufficiently short period of time (Fig 3(a)), Tout = "1" is maintained and it is judged fault-free. Furthermore, when there is some dynamic current, if V(Node1) < VT(N2), then Node2 = "1" holds. If there is a fault in the CMOS logic circuit under test, some static current exists in the circuit. In that case, as in the aforementioned case, if V(Node1) 2 VT(N2) then Node2 = "0" holds. If Node2 = "0" holds for a sufficiently long time (Fig. 3(b)), Tout = "0" holds and it is judged faulty. That is the integral of the current through transistor N1 is proportional to the integral of the voltage at Node3. Hence when the testing circuit of Fig. 2 is used, a fault can be detected by measuring the integral of the current in the circuit under test. The parameters of nMOS transistors NZ and N2 are determined by the required voltage at Nodel and the

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VDD TVOD V V VDD

V 1 I

GND GND dl A A GND

NGND TGND

V-l Translator Level Translator Integral Circuitry - - \ /

Fig. 2. Equivalent circuit of testing circuit.

(a) fault-free (b) faulty

Fig. 3. Circuit response in Fig. 2.

I (a) fault-free response ! i I I I

I (b) faulty response ! 1 ! ! !

(c) faulty response with equal IDD

Fig. 4 Example of circuit response.

Tout

operating speed of the circuit under test. The para- meters N2, R2 and ZWZ are decided by the threshold value of the voltage by which the circuit is judged to be faulty or fault-free. Furthermore the values of CI and RZ are determined by the operating speed and the threshold voltage value for the circuit under test. The V-I Translator and Level Translator can be tested by performing a DC test on terminals NGND , TGND , Tmde , TWD. Also the Integral Circuitry is tested by performing an AC test on terminal T W D .

The testing circuit shown in Fig. 2 was simulated by SPICE3 and its basic operation was verified. In Fig. 2 the transistor size (W [pm]/L [pm]) resistance value [ a ] and capacitance value [F] are given. The simulation was done under VDD = 5 V, Temp. = 27"C, and VTN = I VTpI = 0.6 V.

4. Test Sequence Generation

Suppose that the current shown by the line in Fig. 4(a) flows when a test sequence is applied to a fault-free circuit under test. The light line in this case is the voltage at Node3 of the circuit of Fig. 2. Here Ti (ZSiS4) represents the test vectors and zj (Za'jS4) represents the integration of the voltage is obtained when TI and T, are applied, the parameters C1, R1, N2, R2, ZW 2 are set so that the circuit is judged faulty when V (Node3) > Vm, holds. Suppose that a fault is excited when the vector T3 is applied as shown in Fig. 4(b) and that a static current flows. Then though the integral of the voltage at time r3 becomes higher than that for the fault-free case, it cannot be judged faulty, since it does not exceed V,,. The reason why this misjudgment occurs is that the dynamic

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Table 1. Number of changes of gate outputs when 500 random vectors are applied

number of changesn average max min Standard

deviation gate MOSFET fault

Circuit name

adder 76 21 4 183 32 52 0 10 74181 121 470 356 41 69 0 11

crn880 555 1802 1456 172 289 83 30 crn1355 636 2308 1790 208 269 130 24 cm1908 1097 3430 2812 436 562 1 90 61 cm2670 1799 5364 4481 660 878 433 81 crn3540 2482 7504 6234 794 1077 304 121

currents between test vectors are different from each other. Hence as shown in Fig. 4(c) if all dynamic currents are equal, Vm, is equal throughout the integration intervals, and the decision between faulty and fault-free becomes easy. In this paper a genera- tion method of test sequences is discussed which makes all the dynamic currents equal.

about 10% of that, the target number of changes between two consecutive vectors is given as follows:

Target No. = (No. of gates x 0.3) k (No. of gates x 0.03) (1)

4.2. Path sensitization during test vector generation

4.1. Test sequence generation method First some terminologies are defined.

A test sequence generation method is presented which makes the dynamic currents for different vectorsalmost equal, that is which makes the numbers of changes at the gate outputs almost equal. To generate such test sequences, in the paper, first a number is set as a target for the number of changes and then a test sequence is generated which satifies this condition.

In actuality the dynamic current differs depending on the direction of the change at the gate output and the driving capability of the gate. However in this paper the following assumptions are made.

Assumption 1. The dynamic currents for the change "1" + " 0 and for the change " 0 + "1" are equal. Also all the gates have the same driving capability. Futhermore there is no delay or hazard in the circuit.

The number of changes when a pseudorandom sequence is applied to the circuit is chosen as the target number of changes. In Table 1 the number of changes is shown when a pseudorandom sequence consisting of 500 vectors is applied to adder, ALU and ISCAS'85 benchmark circuits. The circuits here all consist of NAND, NOR and NOT only. Since from Table 1 the average number of changes is about 30% of the number of gates and the standard deviation is

Definition 5 . If none of the inputs to a gate share the same fanout points, the gate is called a nonreconver- gent gate.

A gate is called a reconvergent gate if paths from a fanout point reconverge one at that gate.

Definition 6. The level of a line s is defined to be the maximum number of gates from a primary input to s, that is the level of s, lev(s) is defined as

0 (s is a primary input)

1 + m a { lev(il), lev(i2),~~~,lev(i,)} lev( s) =

(2)

Here $ ( l s j s n ) represent the input lines of the gate which has s as its output.

Definition 7. For a gate G on a path P, the inputs of G which are not on P are called off-path input.

Definition 8. For an assignment of logic values to a circuit, a path along which a change in the logic value of an input line of a gate propagates to its output is called apropagatingpath. A path which is not a pro- pagating path is called a nonpropagating path.

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a (01

x (n) : n denotes level of line x

Fig. 5 . Circuit example 1.

Definition 9. A gate which has at least one propagating path is called a propagating gate. A gate which is not propagating is called a nonpropagating gate.

Example 1. In the circuit of Fig. 5 the number in ( ) represents the level of the line. Gates G1 - G5 are nonreconvergent gates, and gates G6 and G7 are re- convergent gates. For path a-e-f-o, inputs b and m are off-path inputs. Also when (A, B) = (0, 1) is applied to the two input NAND gate of Fig. l(a), this gate is a propagating gate, A-C is a propagating path and B-C is a nonpropagating path. That is a change in the logic value of input A is propagated to output C straight- forward, however a change in the logic value of input B is not propagated to the output unless the logic value of A is changed.

Usually a test for SAF consists of setting a test input to the gate under test (D setting) and propa- gating the fault information to a primary output (D drive). On the other hand, in current testing only the excitation of a fault that is setting a test input to the gate, is necessary. Though that can be done by using the D setting of a SAF test, the estimation of the number of changes in the gate outputs seems difficult. Thus in this paper a backward operation, which com- bines the justification operation of D algorithm and the backtrace operation of PODEM, is used to generate a test sequence.

First, values are assigned to the inputs of the faulty gate to excite the fault. Then a path is established from the input line to a primary output. During that operation everytime a gate is passed the 'input values for that gate are determined by the justification operation. To the inputs of the gate the values are assigned that make it a propagating gate. When there are more than one path that can be established, or there are more than one set of input values that can be

assigned, the ones that are expected to cause the larg- est number of changes in the gate outputs are selected. The selection method is going to be discussed later. When the justification operations have been applied up to the primary output, off-path inputs still remain unjustified. To justify those lines, backtrace operations are applied with the assigned values as targets and the values for the primary inputs are determined. If there are some inconsistencies among the logic values (tar- gets) of the unjustified lines, and the generation of test vector is unsuccessful, the same procedure is repeated starting at the same fault along another path.

Example 2. Let us consider a fault on input n of gate G6 of the circuit in Fig. 5 . First assign input values to input (0, n ) to excite the fault in question. After comparing the number of input changes of G4 is larger, then apply the justification operation to input lines f and m. Similarly apply the justification oper- ation to gates G3 and G2 and determine the values of the primary inputs c and d. The sensitized path in this case is o - m - h - f - c(d). Next the backtrace opera- tion is applied to the unjustified lines n and f and the logic values of the primary inputs a, b and j are deter- mined.

Test vectors are generated in order from those for undetected faults of the highest level. Also when the justification operation is performed from the fault in question to the primary inputs, the number of changes in case of teh success of that particular test generation is estimated. When there are more than one sensitiz- able path and more than one input that can be assign- ed, the selection is made according to the following criteria.

Criterion 1. Select a path and input values which can be expected to produce the largest number of changes if the vector generation is successful.

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Rule 1. Select the output line of a gate blocking the propagation.

Rule 2. Select a line which causes the output value of the gate to change.

(a) minimum transitions Rule 3. Select a line which is a nonpropagating

path.

(b) more transitions

Fig. 6. Circuit example 2

Criterion 2. Select a path which has the smallest number of reconvergent gates.

Criterion 3. Select a path which contains the largest number of undetected faults.

The reason that a path and input values with the largest number of changes is selected in Criterion 1 is that since the target number of changes is set to 30% of the number of gates in the circuit, it is considered easier to reach the target if the selection is made so that the number of changes increases.

Theorem 2. During the test vector generation process for a fault, when there is a nonpropagating path in the sensitized path due to the test vector generated most recently, if it can be made a propagatingpath by applying the justification operation to a gate having the nonpropagating path, then the logic value changes for at least one of the paths connecting to off-path inputs to the gate.

Proof. Among the gates on a nonpropagating path there is at least one off-path input which is assigned a logic value that blocks the propagation of the changes in the input values. Hence to make this path propa- gating such logic values must be assigned to the off- path inputs that the changes in the input values can be propagated to the gate output. (Q.E.D.)

Theorem 3. If the output value of a gate changes, then at least one of its inputs changes its value.

The proof theorem is obvious.

Based on these theorems rules for selecting a path can be derived for Criterion 1 when sensitizing a path from the fault under consideration to primary inputs.

Rule 4. Select a line with the high test level number.

The rules 1-4 have the priority representedby their number.

Example 3. Consider setting logic value "1" at line g of the circuit of Fig. 6. Here G1 and G3 are propa- gating gates, and G2 is a nonpropagating gate. Also b - e, e - g and f - g are propagating paths and a - e, c - f and d - f are nonpropagating paths.

(1) The case when the number of changes in the gate output values is the smallest (Fig. 6(a)): Suppose the justification operation is applied to path g - e - a. Since paths a - e and e - g are propagating, changes in logic values can occur only on this path. Hence the number of changes is the smallest.

(2) The case when the number of changes in the gate output values is large (Fig. 6(b)): Suppose that the justification operation is applied along path g - f - c (g - f - d). Since gate G2 is a blocking gate, that is paths c - J and d - f are both nonpropagating, the make G2 a propagating gate the logic value of an off-path input d(c) must be changed. That is the logic values along at least one path from primary inputs to d(c) must be changed. If lev(c) > lev(d), then g - f - c is selected as the path.

As can be seen from this example if a path is select- ed according to rules 1 - 4, more changes can be ex- pected in the gate outputs and the number of changes can be estimated. Criterion 2 is used to increase the probability of success of the test vector generation for the selected path. Also Criterion 3 is used to reduce the number of test vectors. For Criterion 3 the follow- ing theorem holds.

Theorem 4. All the gates which become propagating when a test vector is supplied are testable at the same time.

Proof. This is obvious since the test vectors for SONF for a gate and the input values which make the gate propagating are identical. (Q.E.D.)

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Table 2. Experimental results of test generation

Circuit Target Sequence Untestable Undetected Cwer- Vectors for name change length fault fault age [%] S A F

adder 23f2 9 0 0 100.0 9

cmaao w f i 7 47 0 0 100.0 86 cm1355 191f19 63 0 137 92.3 137 cm 1908 3 2 9 ~ 72 0 79 97.2 165 cm2670 54of54 41 7 258 94.1 478 cm3540 745f74 36 23 496 93.1 260

74181 36f4 52 4 10 96.1 88

** : Results of original TPG syslem (conventional TPG)

procedure TPG-CT /* TPG with counling the number 01 transitions */ pre-processing ; V a l = number of objective transitions; initialize all signal lines; provoke fault simulation; while given faults exist do begin

clear all signal values; counf = 0; provoke consistency operation along a selecled path; while counf < vol do begin

generate a veclor overlapping present vector; /* provoke backtrace lor unjustified lines; ' I i f TPG is success then begin

cortnf += number 01 transitions; if count p= ual then

if count > vnl then

select anolher path;

break;

cancel present palh;

end else begin

end

cancel presenl path; select another palh;

end provoke fault simulation;

end;

Fig. 7. Algorithm of test generation.

Of the input values assigned to a gate by the justification operation the ones which make the gate propagating do not necessarily increase the number of changes. However, from Theorem 4 the test sequence is more likely to be shorter if input values are assigned to the gate which make the gate propagating.

5. Test Generation Algorithm and Experimental Results

A test generation algorithm and the results of test vector generation are presented.

The test generation system used in this paper utili- zes the backword operation of a test generation system for stuck-at faults based on PODEM algorithm. For backword operation the justification operation of D algorithm is also used in addition to the backword operation of PODEM. The D setting and D drive operations are omitted. The fault simulator was modified so that SONF can be simulated. This system is implemented using C on a SUN 4 workstation.

In Fig. 7 the test sequence generation algorithm is shown. In the preprocessing the construction of a fault list and the level assignment is performed along the paths to the primary inputs. Then for the unjustified lines the backtrace operation is applied to determine the primary input values. If the vector generation is successful but if the target number of changes is not reached, the same kind of operations are performed on other undetected faults by overlapping the test vectors. Conversely if the number of changes exceeds the target, the primary input values are removed which were most recently selected for the fault, and the test vector generation is continued for another path. When the target number is reached, the logic values of the corresponding primary inputs for the test vector most recently generated are assigned to the remaining inputs. If for an arbitrary fault the test generation fails for ten different choices of path, the test generation for the fault is halted and it moves on the another fault.

In Table 2 the results of the test sequence generation are given. The untestable fault means faults for which no test vector exists. The undetected fault represents those faults for which the test generation was halted after ten backtrackings and those for which the test generation failed ten times. Also the last column shows the results of the test generation for

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stuck-at faults by the original test generation system. The fault coverage p was calculated by the following equation.

no. of untestable faults + no. of undetected faults

no. of faults )x 100

(3)

For all the circuits the generated test sequences statisfied the target number of changes. Futhermore, the number of generated test vectors is less than that for conventional tests for stuck-at faults.

1.

2.

3.

4.

5 .

6.

6. Conclusions

In this paper a circuit for built-in current testing and a test sequence generation method for the pro- posed circuit have been described. The proposed test- ing circuit can measure the integral of the current over a unit time, its organization is simple and it itself can be tested. Furthermore test sequences can be genera- ted using a part of conventional test generation algo- rithms for stuck-at faults, and test sequences have been generated which satisfy the target number of changes with a less number of test vectors than those for stuck- at faults, that is test sequences for which the numbers of changes in the logic values between test vectors are almost equal.

For future works, detailed simulations on the pro- posed circuit are necessary and the practicality of the testing circuit must be examined. For test generation, methods of sensitizing a path to make the test genera- tion easier also need to be investigated in addition to those which consider only the number of changes. Also in this paper the dynamic current is assumed to be equal regardless of the direction of the changes at the gate outputs and the driving capabilities of the gates. Furthermore delay and hazard also have been neglected. The test sequence generation considering those factors and the application to sequential circuits also need be investigated.

7.

8.

9.

10.

11.

12.

13.

14.

REFERENCES

R. L. Wadsack. Fault modeling and logic simu- lation of CMOS and MOS integrated circuits. Bell Syst. Tech. J., 57, pp. 1449-1474 (May-June. 1978). M. W. Levi. CMOS is most testable. Proc. Int. Test Conf., pp. 217-220 (1981). Y. K. Malaiya and S. Y. H. Su. A new fault model and testing technique for CMOS devices. Proc. Int. Test Conf., pp. 25-34 (1982). J. M. Acken. Testing for bridging faults (shorts) in CMOS circuits. Proc 20th Design Automation Conf., pp. 717-718 (1983). C. F. Hawkins and J. M. Soden. Electrical char- acteristics and testing considerations for gate oxide shorts in CMOS ICs. Proc. Int. Test Conf.,

F. J. Ferguson and J. P. Shen. Extraction and simulation of realistic CMOS faults using induc- tive fault analysis. Proc. Int. Test Conf., pp. 475- 484 (1988). N. K. Jha. Detection multiple faults in CMOS circuits. Proc. Int. Test Conf., pp. 514-519 (1986). M. Hashizume, K. Yamada, T. Tamesada and M. Kawakami. Fault detection of combinational circuits based on supply current. Proc. Int. Test Conf., pp. 374-380 (1988). W. Maly and P. Nigh. Built-in current testing - Feasibility study. Proc. Int. Conf. Circuit-Aided Design, pp. 340-343 (1988). P. Nigh and W. Maly. Test generation for current testing, IEEE Design and Test, 7, 1, pp. 26-38 (Feb. 1990). D. B. I. Feltham, P. J. Nigh, I,. R. Carley and W. Maly. Current sensing for built-in testing of CMOS circuits. Proc. Int. Conf. Computer Design, pp. 454-457 (1988). R. R. Fritzemeier, J. M. Soden, R. K. Treece and C. F. Hawkins. Increase CMOS IC stuck-at fault coverage with reduced ZDDe test sets. Proc. Int. Test Conf., pp. 427-435 (1990). F. J. Ferguson, M. Taylor and T. Larrabee. Testing for parametric faults in static CMOS circuits. Proc. Int. Test Conf., pp. 436-443 (1990). W. Mao, R. K. Gulati, D. K. Goel and M. D. Ciletti. QUIETEST: A quiescent current testing methodology for detecting leakage faults. Proc. Int. Conf. Circuit-Aided Design, pp. 280-283 (1990).

pp. 544-555 (1985).

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AUTHORS (from left to right)

Yukiya Miura received the B.E. and M.E. degrees in electronics engineering from Akita University in 1985 and 1987 respectively. He joined NEC from 1987 to 1989. He finished the doctoral program in applied physics in 1992. Currently he is as assistant professor in the Faculty of Technology at Tokyo Metropolitan University. He has been working on testing methods for logic circuits and design for testability. He is a member of Information Processing Society and IEEE.

Yasushi Wada received the B.E. degree in applied physics from Osaka University in 1991. He is currently in the doctoral program of the Faculty of Engineering of Osaka University. He has been working on test methods for logic circuits.

Kozo Kinoshita received the B.E. in communications engineeringfrom Osaka University in 1959. He completed the doctoral program at the same university in 1964. He became an assistant professor in the Faculty of Engineering of Osaka University after Ph.D and became an associate professor in 1966. In 1978 he joined Hiroshima University as a professor. Since 1989 he has been working on fault diagnosis of logic circuits and design for testability. He is the author of Fault Diagnosis of Digital Circuits, Volume 1 (Kogaku Tosho Publishing Co.) and Design of VLSI I1 (Iwanami Shoten). He is a member of Information Processing Society, Institute of Electrical Engineers of Japan, and IEEE.

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