DESIGN OF HILBERT TRANSFORMER FOR SOLID-STATE ENERGY METER

Bojan Anđelković, Milunka Damnjanović, Faculty of Electronic Engineering Niš

Abstract – The measurement of reactive power is gaining interest in modern energy meter chips. In order to calculate reactive power it is necessary to shift phase of voltage signal for 90° relative to current. Hilbert transformer is a digital filter that can be used for this purpose. The filter design procedure and its hardware implementation are presented in this paper. 1. INTRODUCTION

Modern electrical devices besides resistive introduce reactive non-linear loads into power lines so the active energy no longer represents the total energy delivered to customers [1]. Therefore, the measurement of reactive energy becomes very important for energy distributors. In order to calculate reactive power, a dedicated DSP block of an energy meter has to perform the Hilbert transform to get a constant phase shift of 90°.

Hilbert transformer described in this paper is a part of solid-state electrical energy meter. DSP block in this chip has two inputs for the current and voltage signals. The filter should introduce a constant phase shift of 90° in voltage signal while keeping amplitude response as flat as possible. In that way appropriate signal for reactive power calculation is generated.

The filter design algorithm and coefficients optimisation process are described at the beginning. After that, hardware implementation of filter basic building blocks and the complete filter architecture is presented. Synthesis, placement and routing procedures used for circuit layout generation are given in more detail.

2. FILTER DESIGN ALGORITHM

In order to simplify hardware implementation and achieve savings in power consumption, the filter is designed with hardwired coefficients. Therefore the coefficients optimisation process is based on their determining in the form of power of two or canonical signed digit (CSD) with reduced number of non-zero digits [2].

There is a number of advantages provided by CSD code over the ordinary binary representation. Since there are no adjacent nonzero digits in CSD code, less nonzero digits than in the binary representation can be expected. Also, CSD code is expected to be less sensitive to truncation and that can further help in simplifying filter implementation.

Therefore, the following filter design strategy is used:

a) Determine ideal filter coefficients for the target amplitude response using least mean square (LMS) optimisation procedure for linear phase FIR filter design.

b) Convert ideal (infinite precision) coefficients to a set of finite precision integer coefficients

c) For each integer coefficient determine its CSD representation using the algorithm given in [2]

d) Truncate CSD representation by keeping only a specified number of most significant nonzero digits.

Number of filter taps, as well as precision of the coefficients are varied until the desired filter response is achieved. In order to have more efficient hardware implementation number of taps and digits in coefficients are optimised to be as low as possible.

Since flat amplitude response is required only in narrow band around line frequency of 50 Hz, during LMS optimisation process weighting function corresponding to 40 Hz and 60 Hz is set to a large value. Outside of that band weighting function is set to 1.0. However, if we make amplitude response symmetrical around the frequency 0.25fclk, where fclk is filter clock frequency, all odd coefficients in impulse response become zeroes which reduces hardware complexity [3]. Therefore, the same value of weighting function is set for frequencies symmetrical to 40 Hz and 60 Hz around 0.25fclk.

Hilbert transformer is designed according to the following specifications:

• Pass band: 0.5 Hz-2.048 kHz

• Pass band (normalised): 0.000125-0.499875

• Clock frequency: 4.096 kHz

• Symmetry: negative

While optimising filter coefficients the goal was to minimise pass band amplitude response variation in narrow band around 50 Hz. The key features of the designed Hilbert transformer are given in Table 1. while its amplitude response around 50 Hz is shown in Figure 1.

0.92

0.94

0.96

0.98

1

1.02

1.04

1.06

0.01 0.011 0.012 0.013 0.014 0.015

Magnitude

Frequency f/fclk Fig. 1. Hilbert transformer amplitude response around

frequency of 50 Hz (0.0122)

Zbornik radova XLVIII Konf za ETRAN, Čačak, 6-10 juna 2004, tom IProc. XLVIII ETRAN Conference, Čačak, June 6-10, 2004, Vol. I

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TABLE 1. Hilbert transformer features

Number of taps 31 Coefficients precision [bits] 14 CSD precision 4

Filter coefficients truncated to 4 digit CSD code are generated by the developed C program and given in Table 2. Since amplitude response is symmetrical, all odd coefficients are zeros.

TABLE 2. Hilbert transformer impulse response coefficients

Coefficient Value CSD representation h( 0) = -h(30) 0.710938 1 x ( +1/2^0 -1/2^2 -1/2^5 – 1/2^7 ) h( 1) = -h(29) 0 0 h( 2) = -h(28) 0.260742 1 x ( +1/2^2 + 1/2^6 -1/2^8 -1/2^10 ) h( 3) = -h(27) 0 0 h( 4) = -h(26) 0.0488892 1 x ( -1/2^4 + 1/2^6 - 1/2^9 -1/2^14 ) h( 5) = -h(25) 0 0 h( 6) = -h(24) -0.223145 1 x ( -1/2^2 + 1/2^5 - 1/2^8 - 1/2^11 ) h( 7) = -h(23) 0 0 h( 8) = -h(22) -0.272461 1 x ( -1/2^2 – 1/2^5 + 1/2^7 + 1/2^10 ) h( 9) = -h(21) 0 0 h(10) =-h(20) -0.207031 1 x ( -1/2^2 + 1/2^4 -1/2^6 – 1/2^8 ) h(11) =-h(19) 0 0 h(12) =-h(18) -0.0189819 1 x (-1/2^6 -1/2^8 + 1/2^11 + 1/2^14 ) h(13) =-h(17) 0 0 h(14) =-h(16) 0.554443 1 x (+1/2^1 + 1/2^4 - 1/2^7 -1/2^12 ) h(15) 0 0

3. HARDWARE IMPLEMENTATION

The general FIR filter architecture can be simplified by exploiting symmetry in Hilbert transformer impulse response. Hardware implementation of symmetrical filter is given in Fig 2.

z-1 z-1 zz -1-1 y(n)

x(n)

h(0)h(1)

symm

h(N-1) h(N-2)

symm

Fig. 2. Implementation of FIR filter with positive and

negative impulse response symmetry

Impulse response symmetry is controled by symm signal which can be +1 for positive and -1 for negative symmetry. In this way the number of multipliers is reduced by half. Considering the architecture shown in Fig. 2, two basic building blocks for constructing the filter can be recognised: CSD multiplier and tap adder (Fig. 3).

a

sign

b

x(n)CSDMultiplier

Tap Adder

h(k)y(n) y(n)=h(k) x(n)⋅

s=a sign+b⋅s Fig. 3. Filter basic building blocks

Fig. 4 shows more detailed schematic of the CSD multiplier.

Having in mind the form of CSD filter coefficients shown in Table 2, the multiplier has to enable multiplication of input signal by every CSD digit and division by its corresponding power-of-two weight. It is constructed with two rows of full adders and one 16-bit adder at the output. Multiplication by +1/-1 CSD digit is implemented by XOR gates. Specifically, multiplication by -1 is implemented by inverting the multiplicand and setting one of the available LSBs in adder array to logic one. Since this architecture has three LSB positions free but there are four CSD digits, it is necessary to reduce CSD code to have at least one positive digit. Division by power-of-two weight can be implemented by simple bit shifting of the input signal to the right for a specific number of positions. Flip-flop at the output is used for signal synchronization with clock. The adder Σ is implemented as ripple carry adder.

x1[15:0]

d2

d3

x2[15:0]

x3[15:0]

x0[15:0]

FA FA FAFA

FA FA FAFA

16

16

16

d116x1i[15:0]

x2i[15:0]

x3i[15:0]

ROW1

ROW2

s0[15:0], c0[15:0]

s1[15:0], c1[15:0]

s[15:0]

sout[15:0]

Σ

z-1z-1

Fig. 4. 16 bit by 4 non-zero digits CSD multiplier

(CSDM16x4)

Using the same idea for +1/-1 multiplication, tap adder can be simply implemented as illustrated in Fig. 5.

sign

a

16

cin

in1

in2

sum

b16

16s

Σ

Fig. 5. Tap adder architecture (TA16)

Using filter basic building blocks it is a straightforward task to map CSD coefficients into the filter architecture shown in Fig. 6. It consists of 8 CSD multipliers (CSDM16x4) and 16 tap adders (TA16). Bit shifting is denoted by “<<” symbols. Delay elements “z-1” are implemented as flip-flops. At the filter output, overflow detection and saturation logic is incorporated. Hilbert transformer contains also clock and reset signals that are not shown in this Figure.

In order to compensate for the delay introduced by Hilbert transformer and make quadrature signals, the current signal should be passed through an all-pass filter as shown in Fig. 7.

84

CSDM16X4

x0 x1 x2 x3d1

d2

d3sout

TA16

a

b

sign

s

TA16

a

b

sign

s

TA16

a

b

sign

s

h(8)

xh8[

15:0

]

0

>>>>>>>>

10527

11

0

voltage[23]&voltage[23:9]

x0 x1 x2 x3d1

d2

d3sout

a

b

sign

s

a

b

sign

s

a

b

sign

s

z-1z-1z-1z-1z-1z-1z-1z-1

s5s6l s5l b4 s4b5

TA16

a

b

sign

s

a

b

sign

ss11

z-1z-1 z-1z-1

s11l s12z-1z-1 z-1z-1

s12lb10

1

s10

1

TA16

a

b

sign

s z-1z-1

a

b

sign

s z-1z-1

s9lb8

1

s8

1

TA16

a

b

sign

s z-1z-1

bs z-1z-1

s9 s10lb9 b11

000 0

xh10

[15:

0]

xh12

[15:

0] h(10)

CSDM16X4

x1 x2 x3d1

d2

d3sout

>>>> >>>>

82 64

x0 x1 x2 x3d1

d2

d3sout

11

1

xh14

[15:

0]

CSDM16X4

x1 x2 x3d1

d2

d3sout

h(14)

>>>> >>>>

124 71

x0 x1 x2 x3d1

d2

d3sout

01

1

h(12)

CSDM16X4

x1 x2 x3d1

d2

d3sout

>>>> >>>>

146 811

x0 x1 x2 x3d1

d2

d3sout

11

0

TA16

a

b

sign

s

a

b

sign

sz-1z-1z-1z-1

s6s7l b6

TA16

a

b

sign

s

a

b

sign

sz-1z-1z-1z-1

s7s8l b7

CSDM16X4

x0 x1 x2 x3d1

d2

d3sout

TA16

a

b

sign

s

TA16

a

b

sign

s

TA16

a

b

sign

s

h(0)

xh0[

15:0

]

0

>>>>>>

752

11

1

shift_voltage[14:0]

x0 x1 x2 x3d1

d2

d3sout

a

b

sign

s

a

b

sign

s

a

b

sign

s

z-1z-1z-1z-1z-1z-1z-1z-1

s1 s0s2l s1l

s15

b0b1

TA16

a

b

sign

s z-1z-1

a

b

sign

s z-1z-1

s15lb14

1

s14

1

TA16

a

b

sign

s z-1z-1

a

b

sign

s z-1z-1

s13lb12

1

s12

1

TA16

a

b

sign

s z-1z-1

bs z-1z-1

s13 s14lb130

000 0

xh2[

15:0

]

xh4[

15:0

]

h(2)

CSDM16X4

x1 x2 x3d1

d2

d3sout

>>>> >>>>

106 82

x0 x1 x2 x3d1

d2

d3sout

01

1

xh6[

15:0

]

CSDM16X4

x1 x2 x3d1

d2

d3sout

h(6)

>>>> >>>>

112 85

x0 x1 x2 x3d1

d2

d3sout

11

1

h(4)

CSDM16X4

x1 x2 x3d1

d2

d3sout

>>>> >>>>

144 96

x0 x1 x2 x3d1

d2

d3sout

11

1

TA16

a

b

sign

s

a

b

sign

sz-1z-1z-1z-1

s2s3l b2

TA16

a

b

sign

s

a

b

sign

sz-1z-1z-1z-1

s3s4 s4l b3

voltage[23]&voltage[23:9]

Overflow/UnderflowDetection and Saturation

Logic

Fig. 6. Hilbert transformer implementation details

It can be shown that in order to construct the signal with

phase shift of 90° relative to Hilbert transformer output, all-pass filter should be implemented by (N-1)/2 flip-flops, where N equals the number of taps in Hilbert transformer [3].

All-passFilter

HilbertTransformer

current

voltage voltage_shifted

current_delayed

Fig. 7. All-pass filter and Hilbert transformer incorporation

All building blocks and the complete filter hardware implementation are described in VHDL and verified in Active HDL simulator. Appropriate simulation results are shown in Fig. 8. As it can be seen, signal at Hilbert transformer output (Voltage_shifted) is phase shifted for 90° relative to input signal (Voltage).

4. SYNTHESIS, PLACEMENT AND ROUTING

Logic synthesis of VHDL models is performed in program Ambit Build Gates which is a part of Cadence

design package [4]. As target technology AMI Semiconductor 0.35um CMOS standard cell library is used. Synthesized Verilog netlist is simulated again and the filter functionality is verified.

Fig. 8. Hilbert transformer simulation results

After floorplanning, placement and routing in Silicon Ensemble [4], the circuit layout is generated. Also, a clock tree is established.

During this process I/O pins were placed and power rings were constructed. Verilog netlist file generated after this step is again simulated to verify the circuit. The filter was generated as block in order to be incorporated into the complete energy meter chip. Obtained filter area is 865.5 x 967.5um.

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5. CONCLUSION

With more and more non-linear reactive loads in electrical devices the reactive power measurement becomes very important for energy distributors.

Hilbert transformer presented in this paper is a part of energy meter chip. It is used to introduce a constant phase shift of 90° in voltage signal. In that way, a quadrature signal necessary to calculate reactive power is generated.

The filter design procedure used for determining impulse response coefficients in CSD form is described. In this way multiplierless filter implementation is possible and some savings in area and power consumption are achieved. Also, the developed filter blocks can be used for realisation of all other digital filters in the chip.

At the moment, a prototype of the energy meter chip is expected and some measurements will be performed to verify the filter VLSI implementation.

ACKNOWLEDGEMENT

This work was supported in part by the Ministry of Science and Life Environment Protection of Serbia, through the Projects IT.1.02.0075.A and IT.1.01.0076.B realized in Technology Development area.

REFERENCES

[1] E. Moulin, “Measuring reactive power in energy meters”, Metering International, Issue 1, pp. 52-54, 2002.

[2] ---, “Dual Band Quadrature Digital Block Up Converter Implementation - Technical Report”, Microelectronics Centre, Middlesex University, London, 2001.

[3] ---, “Digital Down Converter Implementation - Technical Report”, Microelectronics Centre, Middlesex University, London, 2001.

[4] Cadence 2003 Documentation

Sadržaj – Merenje reaktivne snage postaje sve značajnije u savremenim kolima za merenje potrošnje električne energije. Da bi se izračunala reaktivna snaga potrebno je da se signal napona fazno pomeri za 90° u odnosu na struju. Hilbertov transformator je digitalni filtar koji može da se koristi u tu svrhu. Procedura za projektovanje filtra i njegova hardverska implementacija opisani su u ovom radu.

PROJEKTOVANJE HILBERTOVOG TRANSFORMATORA ZA

INTEGRISANI MERAČ POTROŠNJE ELEKTRIČNE ENERGIJE

Bojan Anđelković, Milunka Damnjanović

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