Design of Capacitive Displacement Sensors for Chip Alignment

Center for High-rate Nanomanufacturing

Design of Capacitive Displacement Sensors for Chip Alignment

Jose Medina

Professor N. McGruer


Outline

1. Introduction2. Displacement sensors3. Capacitive sensors4. FEM simulations5. Readout circuit6. Scaled models7. Experiments8. Conclusions


Introduction

Approach

1. Assemble

2. Alignment

3. Transfer

2


Introduction

• Requirements– Accuracy to nm– Cost effective– Fast– Compatible

• Fabrication• Electronics• Actuator (nanopositioner)

– Variable gap– Connections to only

one side


Displacement Sensors

Criteria Probe-based Optical Thermal Capacitive

Accuracy + + + + +/+ + +/+ +Range - /+ + + +/+ + +/+ +Speed + + - +Fabrication - -- + + + +Electronics integration + - + + + +Parasitic forces - /+ + + -/+ --Power consumption +/+ + -/+ + + +

A. A. Kuijpers, ‘Micromachined Capacitive Ling-Range Displacement Sensor for Nano-

positioning of Microactuator Systems’, PhD thesis, Universiteit Twente


Capacitive sensors

Capacitive sensor literature– Widely used

• Drug delivery, temperature/humidity sensors, automotive, positioners

– No sensor moves in two dimensions

‘Modeling and Optimization of a Fast ResponseCapacitive Humidity Sensor’, Tetelin

‘Perspectives on MEMS in Bioengineering: A NovelCapacitive Position Microsensor’, Pedrocci


Capacitive sensors

Electrodes on substrate and template


Capacitive sensor

C=Q/V=f(geometry)

Chip alignment: connections only on one electrode

gnL

dx

dC

g

xwnL

g

AC overlap 1

~

-6 -4 -2 0 2 4 60

0.2

0.4

0.6

0.8

1

1.2x 10

-4

displacement [um]

capa

cita

nce

[pF

/um

]

analytical and numerical capacitance

C13 analy

C23 analyC12 analy

C12//(C13 s C23) analy

C13 numer

C23 numerC12 numer

C12//(C13 s C23) numer


Capacitive sensor

Complete system

Equivalent circuit


Capacitive sensor

Cantor set geometry– First level

– Second level

– Third level

-80 -60 -40 -20 0 20 40 60 80 100

1.57

1.58

1.59

1.6

1.61

1.62

x 10-4

displacement [um]

capa

cita

nce

[pF

/um

]

filtered output capacitance, 3x3x3x3 model, g=20 um

-4 -3 -2 -1 0 1 2 3 40.8

1

1.2

1.4

1.6

1.8

2

displacement [um]

capa

cita

nce

[pF

]

three groups, bottom substrate glass, g=0.1um


Capacitive sensor

Central fractal geometry

– First level

– Second level

– Third level

gnL

dx

dC 1


FEM simulations

Numerical method2

2

1CUW

v

ni

ielemkkkkk

elem

iiziyixvEEEdvEW

1

2222

,,,2

1

2

1

6

5

4

3

2

1

34

24

23

14

13

12

234,6

224,6

223,6

214,6

213,6

212,6

234,2

224,2

223,2

214,2

213,2

212,2

234,1

224,1

223,1

214,1

213,1

212,1

..

....2

1

W

W

W

W

W

W

C

C

C

C

C

C

UUUUUU

UUUUUU

UUUUUU

UE

U

02

A. Hiekes, SIEMENS; Baxter, Capacitive Sensors


FEM simulations

Modeling scenarios• Closed system

• Open boundary– Natural boundary condition

– Trefftz domain

– Infinite elements

ANSYS, Inc


FEM simulations

-4 -3 -2 -1 0 1 2 3 40

0.5

1

1.5

2

2.5

3

3.5x 10

-3

displacement [um]

capa

cita

nce

[pF

/um

]

capacitance simulations g=0.1 um

c12c13

c14

c15

c23c24

c25

c34

c35c45

-3 -2 -1 0 1 2 3

0

1

2

3

x 10-4

displacement [um]

capa

cita

nce

[pF

/um

]

capacitance simulations g=0.1 umc12c13

c14

c15

c23c24

c25

c34

c35c45


FEM Simulations

Models– Doped Si substrates– Glass top substrate– Glass bottom

substrate

-4 -3 -2 -1 0 1 2 3 40.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5x 10

-3

capa

cita

nce

[pF

/um

]

3x3x3x3 electrodes g=0.1 um

wired susbtrates

glass bottom subsglass top subs

5 conductors


Readout Circuit

Converter– transforms a signal to another more convenient

Voltage applied at capacitor

dt

dVCgAC

dt

dVV

dt

dgAC

dt

CVd

dt

dQiC ),(),(

)(

)cos())sin(( tACtAdt

dCiC


Readout circuit

Alignment precision and converter performance

Circuits– Oscillator– AC-bridge– Transimpedance amplifier

– Switched-capacitor

– Sigma-Delta modulator

BWGBW

CCTK

VC

amp

psB

inrms )(

)2(21min

]/[2

min HzFdCdv

vC

o

nrms

BWf

GBWeC

f

KTC

VC

s

ampnT

s

T

inrms

)2)((122

min


Readout circuit

Transimpedance amplifier

Synchronous demodulator

Low pass filter

fso RIV

)sgn( inino VVV

ininout VsRC

RCV

RCs

CssV

1

1

1

1)(


Readout circuit

Switched-Capacitor Amplifier

sf

so

fo

ss

VC

CV

CVQ

CVQ

2

1

φ2

φ1


Readout circuit

Sigma-Delta modulator

Cap-to-digital converter based on SC modulator


Scaled Models

Scaled models

– How do and C scale with geometry?

dxdC

Cx

/min

min

w

wwxx

g

nLw

xxw

wxx

w

g

nL

CC

CCCfC ijout

4

22

22)(

22

1312

1312

minx

g

nL

dx

dC

x

out

0


Scaled Models

Theoretical accuracy

Scaled models

''

'),,,()',',','( minmin n

n

L

L

g

gngLwxngLwx

n

n

L

L

g

ggLnwCgLnwC outout

''

'),,,()',',','(

nL

gCx

minmin


Experiments

Two PCBs – Large w/g ratio

• Max accuracy?

– Small w/g ratio• Geometry performance?

Large w/d ratio Top board Bottom board

Trace width 0.12’’ 3.048 cm 0.25’’ 6.350 cm

Separation traces 0.12’’ 3.048 cm 0.47’’ 11.938 cm

Separation groups

0.36’’ 9.144 cm

Short w/d ratio Top board Bottom board

Central group

(mm)

Width 0.03’’ 0.762 0.06’’ 1.524

Spacing traces 0.03’’ 0.762 0.03’’ 0.762

Spacing subgroups 0.09’’ 2.286 0.12’’ 3.048

Lateral group

(mm)

Width 0.15’’ 3.81 0.3’’ 7.62

Spacing traces 0.15’’ 3.81

Spacing groups 0.45’’ 11.43 0.54’’ 13.716


Experiments

Setup– Stage– PCBs– Readout circuit

• AD7745

– Connectors, wires– Computer


Experiments

Results: large feature board

0 5 10 15 20 25 30

4

5

6

7

8

9

10

11

12

13

displacement [mm]c

ap

ac

ita

nc

e [

pF

]

simulation and experiments gap 1 mm

experiment a

experiment bsim 1mm

sim1.5 mm

0 5 10 15 20 25 30 35

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

displacement [mm]c

ap

ac

ita

nc

e -

C(d

isp

l=0

) [p

F]

simulation and experiments gap 1 mm

experiment a

experiment bsim 1mm

sim1.5 mm

• Experiments greater capacitance

• Sim and experiments same profile• Experiments different results

1.6 1.8 2 2.2 2.4 2.6 2.8

15.975

15.98

15.985

15.99

15.995

16

16.005

16.01

displacement [mm]

ca

pa

cit

an

ce

[p

F]

experimental results, gap 1 mm

• Accuracy – 5fF (specs 4fF)– 0.1mm (calculations 2 μm)

• Sim/exp results further for long displacements

0 5 10 15 20 25 30 35 40-0.5

-0.45

-0.4

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

displacement [mm]c

ap

ac

ita

nc

e -

C(d

isp

l=0

) [p

F]

simulation and experiments

experiment 3 mmsim 3 mm

experiment 6 mm

sim 6 mm

experiment 12 mmsim 12 mm


Experiments

Results: small feature board• Cap increases with displacement!• Similar profiles• Good performance

at short gap• Min largest gap

3mm (u=0.762 mm)

0 5 10 15 20 25 30 35 40-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

displacement [mm]

ca

pa

cit

an

ce

[p

F]

central fractal test board

exp g 1 mm

exp g 2 mmexp g 3mm

exp g 4mm

sim g 1mm

sim g 2 mmsim g 3 mm

sim g 4 mm


Conclusions

Simulations– DC capacitance

• Ground close than at infinite• 5 electrodes + stage

– Sim/exp further for large gaps• Cap to stage dominant

– Variations between experiments• Plates not parallel, gap varies

– Increase cap with displacement• C13 and C23 decrease • C12 dominant, board ‘perturbs’ E


Conclusions

Sensor design suggestion– Central fractal geometry– Width depends upon min/max gap

• Min: g/w < 1/3 for last level to take over, ideally <1/10• Max: g/w < 1 to avoid instabilities

– Capacitor width w, #levels u

– Chip 15x15 mm sq sensor 0.5x0.5 mm sq

153 nuw


Conclusions

Min feature size 1 um 1 um 0.1 um 1 um

w strip-group 1 1-3 um 1-3 um 100-300 nm 1-3 um

w strip-group 2 1-15 um 1-15 um 0.1-1.5 um 1- 291 um

w strip-group 3 5-75 um 5-75 um 0.5-7.5 um 0.1 – 1.5 mm

w strip-group 4 25-375 um 25-375 um 2.5-37.5 um

w strip-group 5 0.125-1.875 mm 12.5-187.5 um

w strip-group 6 0.0625-0.9375 mm

Max gap 25 um 0.1 mm 1 mm 0.1 mm

Min gap 20 nm 20 nm 10 nm 20 nm

Max gap 25 um 0.1 mm 1 mm 0.1 mm

#sets n 5 7 9 49+2

Xmin scaled 240 nm 34 nm 26 nm 5.8 nm

Xmin calculated 4.8 nm 0.68 nm 0.53 nm 0.11 nm


Thank you for you attention

Acknowledgments– Advisor: Professor McGruer– Professors: Adams, Busnaina, Muftu,

Papageorgious, Sun – Students: Prashanth, Juan Carlos Aceros,

Peter Ryan, Andy Pamp, Siva, Harris Mussolis


Capacitive sensors

Definition Capacitance

g

A

V

QC

s

Conductor a

Conductor b

Vs

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+ + + + + + + + + + + ++

+

- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

e-

Q

Q

E

dt

dVCgAC

dt

dVV

dt

dgAC

dt

dQiC ),(),(


FEM Simulations

Convergence

0 20 40 60 80 100 1200.94

0.95

0.96

0.97

0.98

0.99

1

1.01

1.02

1.03

nodes per surface electrode

capa

cita

nce(

node

s)/c

apac

itanc

e(5

node

s)

convergency, 3x3 model, g=0.1 um

c12c13

c14

c15

c23

c24c25

c34

c35

c45cout



sf

so

fo

ss

VC

CV

CVQ

CVQ

2

1

• Sampling phase (φ1 on, φ2 off)• Charge-transfer phase (φ1 off, φ2 on)

ssfss CVCCVQ )00()0(1

Switched-Capacitor amplifier

φ2

φ1

fofos CVCVCQ )0()00(2


Correlated Double Sampling

• Sampling phase

)0())(())((1 osfosinosin VCVVCCVVCCQ

• Processing phase

)()0)(()0)((2 osoutfosos VVCVCCVCCQ

inf

out VC

CnV

2


Simulations switched-capacitors

Time (ms)

V (volts)


Bandwidth switched-capacitors

-60

-50

-40

-30

-20

-10

0

Mag

nitu

de (

dB)

109

1010

1011

1012

1013

1014

1015

-90

-45

0

Pha

se (

deg)

Bode Diagram

Frequency (rad/sec)

Ao=1e3, Cp=Cf/10

Ao=1e3, Cp=Cf

Ao=1e3, Cp=Cf*10

Ao=1e5, Cp=Cf/10

Ao=1e5, Cp=Cf

Ao=1e5, Cp=Cf*10

212 CVA

VC

A

VC

A

VQ o

op

oo

1)(

o

o

o

oo

s

sA

ss

sAsA

2

21

2

21

C

CCC

sC

CCCsA

pp

op

oo

Documents

Design of Capacitive Displacement Sensors for Chip Alignment