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1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations 9.2 One-Stage Op Amps 9.3 Two-Stage Op Amps 9.4 Gain Boosting 9.5 Comparison 9.6 Output Swing 9.7 Common Feedback 9.8 Input Range Limitations 9.9 Slew Rate 9.10 High-Slew-Rate Op Amps 9.11 Power Supply Rejection 9.12 Noise in Op Amps Chapter 6: Operational Amplifiers

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Page 1: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

1

Design of Analog Integrated Circuits

Textbook Chapter 9

9.1 General Considerations

9.2 One-Stage Op Amps

9.3 Two-Stage Op Amps

9.4 Gain Boosting

9.5 Comparison

9.6 Output Swing

9.7 Common Feedback

9.8 Input Range Limitations

9.9 Slew Rate

9.10 High-Slew-Rate Op Amps

9.11 Power Supply Rejection

9.12 Noise in Op Amps

Chapter 6: Operational Amplifiers

Page 2: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

2

Op Amp Design Challenge

Three decades ago

•General-purpose blocks as an “ideal” op amp

•Design effort is to satisfy an ideal op amp

- infinite gain

- infinite input impedance

- zero output impedance

Today

•Design effort is to make trade-offs for a specific

application, often sacrificing the unimportant

aspects to improve the critical ones.

•E.g., gain error vs speed, open loop gain vs VDD

Page 3: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

3

Performance Parameters

• Gain(Precision)

• Small-signal Bandwidth(Speed): 3-dB/fu

• Large-Signal behavior (e.g. slew rate)

• Output Swing (especially for Low supply voltage)

• Linearity

• Noise and offset

• Supply Rejection

• Input CM Range, Input/Output Impedance

• Power dissipation

Page 4: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

4

One-Stage Op Amps

• Low-frequency gain:

• Bandwidth: usually proportional to 1/(CL*Rout)

• Output Swing (single-side): VDD-3VOV

• Mirror pole in single-ended circuit

• Noise: two input devices and two “load’ devices

( || )m ON OPg r r

Page 5: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

5

Telescopic Cascode Op Amps

• Low-frequency gain:

• Output Swing (single-side): VDD-5VOV

• Mirror pole at node X (at node Y) in single-ended

• Difficult to short telescopic op amp output to input

• Noise: input noise mainly has four devices contribution

2 2( || )mN mN ON mP OPg g r g r

Page 6: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

6

Example 9.5

Shorting their input and output to form an unity-gain buffer

To keep M2 and M4 in saturation

When , M4 is in triode, others are saturated;

M2, M4 are saturated;

M2, M1 in triode,M4 is in saturation.

2 4

4

4 4 2

and

( )

out X TH out b TH

X b GS

b TH out b GS TH

V V V V V V

V V V

V V V V V V

4 in b THV V V

4 4 2( )b TH in b GS THV V V V V V

4 2( )in b GS THV V V V

Page 7: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Specifications: VDD = 3V, differential output swing = 3V, power dissipation

= 10mW, voltage gain = 2000. Assume nCox = 60 A/V2, pCox = 30

A/V2, n = 0.1V1, p = 0.2V1 (for an effective channel length of 0.5

m), = 0, VTHN = VTHP = 0.7V.

1.5mA1.5mA

Telescopic Cascode Op Amps Design

Power budget: IM9 = 3mA, IMb1 + IMb2 =

330A.

Output swing: Node X(Y) positive swing =

1.5V and M3-M6 are in saturation. Then, for

left half circuit, we have VOD7 + VOD5 +

VOD3 + VOD1 + VOD9 = 1.5V. Since M9 is

carrying largest current, VOD9 0.5V is

chosen. Four cascode transistors are shared

with 1V. Because of lower mobility, we

allocate overdrive of M5~M8 are 300mV, i.e.

|VOD5 = VOD6 =|VOD7 = VOD8 0.3V,

obtaining VOD1 + VOD3 0.4V.

Page 8: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CM level & bias: Minimum allowable input CM level = VGS1 + VOD9 = 1.4V.

Vb1, min = VGS3 + VOD1 + VOD9 = 1.6V. Vb2, max = VDD (VGS5 + VOD7) = 1.7V.

- Finally, DC bias voltage circuits and a CMFB circuit are necessary

W/L: By ID =(1/2)Cox(W/L)(VOD)2, (W/L)14 = 1250, (W/L)58 = 1111,

(W/L)9 = 400.

Gain: Av gm1[(gm3ro3ro1) (gm5ro5ro7)]=1416. In order to increase the

gain, we recognize )/()/(2 DDoxom IILWCrg DIWL / , where

1/L. We can therefore increase the width or length, or reducing the drain

current.

Modulation: Since M1~M4 appear in signal path for keeping

minimum capacitance, we double the width and length of M5~M8 to

increase ro (gm remains constant). Choosing (W/L)58 = 1111m/1m and

p=0.1V-1, then Av 4000. VDS1=VGS1-VTHNVGS1=0.2+0.7

Telescopic Cascode Op Amps Design

Page 9: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

Gate Bias Voltage Generation

• Ensure bias voltage to track the input CM level

• Choose Mb1 to be a narrow, long, “weak” device

9

1 , 1,2 , 1

, 1 1,2 1,2 3,4( )

b in CM GS GS b

GS b GS TH GS

V V V V

V V V V

Page 10: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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• NMOS input higher gain

• NMOS input Lowering the pole at folding point

• PMOS input is less sensitive to flicker noise

• Slighter Higher Output Swing than telescopic

• Higher Power dissipation, lower voltage gain, lower pole

frequency and higher noise

• Input and output can be shorted: A better input CM range

1 3 3 3 1 5 7 7 7 9| | {[ ( || )] || [ ]}V m m mb o o o m mb o oA g g g r r r g g r r

Folded Cascode OP Amp

Page 11: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Specifications: VDD = 3V, differential output swing = 3V, power dissipation =

10mW, voltage gain = 2000. Assume nCox = 60 A/V2, pCox = 30 A/V2, n

= 0.1V1, p = 0.2V1 (for an effective channel length of 0.5 m), = 0, VTHN

= VTHP = 0.7V.

Power budget: IM11 = 1.5mA, IM9 + IM10 = 1.5mA, IMb1 + IMb2 + IMb3 = 330A.

Output swing: one side o/p swing = 1.5V, M3-M10 in saturation.

Choose VOD5,6 0.5V, VOD3,4 0.4V, VOD7,8 = VOD9,10 0.3V.

W/L: (W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)710 = 278.

O/p CM level: CMmin = VOD7 + VOD9 0.3V+0.3V0.6V,

CMmax = VDD - VOD5 - VOD3 3.0V-0.5V-0.4V 2.1V,

thus CMoptimum = 1.35V.

Folded Cascode OP Amp Design

Page 12: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Determine (W/L)1,2: minimum input CM level = VGS1 + VOD11.

Minimum dimensions of M1,2: If input and output are shorted, then VGS2 + VOD11 =

1.35V. With VOD11 = 0.4V as initial guess, we have VGS1 = 0.95V VOD1,2 = 0.95-0.7 =

0.25V, and (W/L)1,2 = 400.

Maximum dimensions of M1,2: The maximum dimensions of M1,2 are determined by the

tolerable input capacitance at nodes X and Y.

CM level & bias: Minimum allowable input CM level = VGS1 + VOD11 = 0.95V+0.4V

=1.35V. Vb1, min = VGS7 + VOD9 = 0.7V+0.3V+0.3V=1.3V. Vb2, max = VDD (VGS3 + VOD5)

= 3.0V- (0.7V+0.4V+0.5V)=1.4V.

Gain: gm = 2ID / (VGS VTH) = 2ID / VOD, we have gm1,2 = 0.006 A/V, gm3,4 = 0.0038 A/V,

gm7,8 = 0.05 A/V.

For L = 0.5 m, rO1,2 = rO7-10=13.3k, and rO3,4 = 2rO5,6=6.67k.

The overall gain 400.

How to increase the gain?

1.Increase ro by decreasing bias current or increase channel length

2.Increase gm by increasing W/L or bias current

Folded Cascode OP Amp Design

Page 13: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

13

Low Voltage Single-ended Output

• Left implementation wastes one threshold voltage

• Still, single-ended output is unfavorable due to half

output swing and a mirror pole

• Note that almost all the differential output circuits need

a CMFB

Fig. (a) VX=VDD-|VGS5|-|VGS7|Vout,max=VDD-|VGS5|-|VGS7|+|VTH6|

Page 14: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

14

Two-Stage Op Amps

• Voltage headroom in today’s design is constrained with

low supply voltage and large output swing

• Gain:

• Output Swing: Vdd-2VOV

Page 15: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

15

Two-Stage Op Amps with cascode devices

• Voltage headroom in today’s design is constrained with

low supply voltage and large output swing

• Gain:

• Can we have more stages? Feedback stability limits

Page 16: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Gain Boosting

• Increase the output impedance without adding more

cascode devices.

Routt A1gm2ro2ro1

•Avoid headroom limitation, PMOS common-source

stage is better, but M3 could go in triode

•Folded-cascode inserts one more stage

Page 17: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Differential Folded Cascode Gain Boosting

The minimum level at the

drain of M3 is equal to VOD3 +

VGS5 + VISS2.

The minimum allowable level

of VD3 is given by VOD3+VOD1,2

+ VISS1.

Page 18: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Gain Boosting in Signal Path and Load

• Gain boosting can be utilized in the load current source

• To allow maximum swings, A2 employs NMOS-input.

Page 19: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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• In fully-differential op amps, the output CM level is usually

not well defined.

- Case 1: , Vx,Vy decreases, Iss triode;

- Case 2: In reverse, Vx,Vy increases, M3,M4 triode.

Common-Mode Feedback

3,4 / 2D SSI I

Page 20: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Conceptual topology

• Measure output CM level;

• Compare with a reference;

• Apply the error to correct the level.

Page 21: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CM Sensing Techniques

R1 and R2 or I1 and I2 must

be large enough to ensure

that M7 or M8 is not

“starved” when a large

differential swing appears

at the output.

If Vout2 is quite higher than Vout1,

I1 must sink both IX (Vout2

Vout1)/(R1 + R2) and ID7.

Consequently, if (R1 + R2) or I1is not sufficiently large, ID7

drops to zero and Vout,CM no

longer represents the true

output CM level.

Page 22: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

22

CMFB using MOSFETs in triode region

• M7 and M8 operate in deep triode region,

THoutoutoxn

THoutoxnTHoutoxn

ononP

VVVL

WC

VVL

WCVV

L

WC

RRR

2

1

11

21

21

87

RP is a function of Vout1 + Vout2 but

independent of Vout2 Vout1.

Page 23: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

23

Differential-mode Voltage

Common-mode Voltage

outout VV ,

CMFBV constant

CMFBV outout VV ,

IB

IB/2+I IB/2-I

Q1

Q2 Q3

Q4

Q5

Q6

IB

IB

IB

IB/2+IIB/2-I

Vout+

VCMFB

Vout-

VREF

CMFB Using Differential Pairs

Page 24: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB Techniques

• Control cascade current source

• Control tail current source

Page 25: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB Techniques

• Deep triode sensing feedback

- Limited Output Swing Due to the drop of M7 and M8

- Large C Reduce the drop and increase M7 and M8

- Device variation Output CM is not constant

• Deep triode folded-cascade sensing feedback

- Improved output swing without the drop of M7 and M8

5

7,8 1 2

1

2( ) 2

b GS

Dn ox out out TH

V V

W IC V V VL

ID

Page 26: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB Techniques

• Modification of deep triode sensing feedback

• The output level is relatively independent of device

parameters and lowers sensitivity of Vb

Page 27: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CM Feedback Techniques

• Modification of deep triode sensing feedback

• M17, M18 reproduces the drain of M15 a voltage equal to the

source voltage of M1 and M2

Page 28: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB Techniques

• Another type of CM feedback topology

• Diode-connected loads’ output CM level is well-defined

• Differential small signal gain

• Common-mode work as a diode-connected

• Low supply voltage design

3

3 3

Output CM= | |

| |

DD GS

SD GS

V V

V V

3 3 1

3 3

| | / 2

| | | |

SD GS F

GS TH

V V R I

V V

Page 29: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB in Two-Stage Op Amps

• CMFB around second stage, but not for first one

• CMFB from second stage to first stage

• 3 or 4 poles, which makes it difficult for the loop stable

Page 30: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB at both Stages

• All the drain currents are copied from Iss

• The differential voltage gain is equal to

Page 31: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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CMFB for Cascode First Stage

• First stage use deep triode feedback loop to avoid loading.

• Achieving high gain

Page 32: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

32

Slew Rate of Telescopic Op Amp

• Each side appears a ramp with slope equal to

• The total slew rate for Vout1- Vout2 equal to

maxSlew rate |outdV

dt

Page 33: Design of Analog Integrated Circuitscc.ee.ntu.edu.tw/~ecl/Courses/105AIC/lock/Analog_Chapter...1 Design of Analog Integrated Circuits Textbook Chapter 9 9.1 General Considerations

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Power Supply Rejection

• Power line contains noise

• PSRR(power supply rejection ration):

- Gain from input to output divided by the gain from

supply to the output

• At low frequency