Design for Testability Design for Debugusers.ece.utexas.edu/~mcdermot/vlsi-2/Lecture_17.pdf · Why Scan design? • Makes internal circuit access much more direct to allow for controllability

EE 382MEE-382M VLSI–II

Design for Testability&

Design for Debug

Bob Molyneaux Mark McDermottMark McDermottAnil Sabbavarapu

The University of Texas at AustinEE 382M Class Notes Foil # 1

Agenda

• Why test?y

• Scan: What is it? What is it good for?

• Snapshot! : Debug Scanout

• Embedded Memory Testing• Embedded Memory Testing

• JTAG

• Summary


Why Test?Why Test?


The Manufacturing Process is Imperfect








Test Techniques

Functional: Make it do what it does.

Structural: Divide and conquerStructural: Divide and conquer


Functional Test

Does my chip execute all architectural instruction

?sequences?

In the presence of all possible data streams?possible data streams?


Structural Test

Does SPC1 do its job?

D MCU d it j b?Does MCU do its job?

Still checking functionality but divide and conquer activity is taking place.


Structural Test

•Do the NOR gates do their job?

F1

•Does the AND gate do its job?

A

B D

C F

G

HF5F2 E

F6

4

F3

Still checking functionality but divide and conquer activity is taking place.

F4


Structural Test

Thesis

If we can prove every gate in the part functions then we

can conclude that the part workscan conclude that the part works.

C llCorollary

Structural ≠ Scan But it makes most sense.


Basics of ScanBasics of Scan


Basics of Scan

F1F7S

A

B D

C F

G

HF5F2F8

E

SRAM

B D G

F6F3F9

F4F0


Basics of ScanSCAN IN

F1F7S

A

B D

C F

G

HF5F2F8

E

SRAM

B D G

F6F3F9

F4F0


SCAN OUT

Convert a Memory Element to a Scan CellCM

CCMemory

element

data in data out

Scannable

C

Register BC A

B

data in Scan out

Master Register Slave Register

Scan in


A data out

Scan Design Components

(1) scan cell (3) scan in and scan out(2) scan chain (4) scan clock

PI (Scan in)scan chain

PO (Scan out)

PI (Scan in)scan chain

scan chain

PO (Scan out)scan chain

scan cell

scan cellscan A clockdata in data outscan in


sca cescan outSystem clock

scan B clock

Why Scan design?

• Makes internal circuit access much more direct to allow for controllability and observabilityy y

• Converts a sequential test generation problem into a combinational test generation problem

• Enables automatic test pattern generation (ATPG)• Enables automatic test pattern generation (ATPG)

• Enables use of low-pincount, low cost testers (ATE)Enables use of low pincount, low cost testers (ATE)


Stuck-At TestingSCAN IN

Test for C stuck-at 1

F1F7S

A

B D

C F

G

HF5F2F8

E

SRAM

B D G

F6F3F9

F4F0


SCAN OUT

Stuck-At TestingSCAN IN Load Scan Chain

Test for C stuck-at 1Load Scan Chain

0S

A

B D

C F

G

H1

E

SRAM

B D G

1

1


SCAN OUT

Stuck-At TestingSCAN IN Pulse Clock

Test for C stuck-at 1Pulse Clock

?S

Test Result

A

B D

C F

G

H?

E

SRAM

1

B D G

?

?


SCAN OUT

Stuck-At TestingSCAN IN Unload Scan Chain

Test for C stuck-at 1Unload Scan Chain

0S

A

B D

C F

G

H1

E

SRAM

1

B D G

1

1


SCAN OUT

Scan-based Structural Test

Scan Inputs

s

Control and clock inputs

PrimaryI/O’s

(no connection) can

chai

ns

logi

c

logi

c

logi

c

logi

cTester

clock inputs

Primary(no connection) s PrimaryI/O’s

(no connection)

Scan Outputs


Snapshot!Snapshot!Debug Scanout


Debug Scanout

St l k d t t tSCAN IN

SCAN IN

SCAN IN

Stop clocks and scan out state

SRAM

SRAM


SCAN Out SCAN Out SCAN Out

Debug ScanoutShadow Scan: Capture state and scan out while running

SCAN IN

SCAN IN

SCAN IN

p g

SCAN IN (TDI)

SRAM

SRAM


SCAN Out SCAN Out SCAN OutSCAN Out (TDO)

Embedded SRAM TestingEmbedded SRAM Testing


Memory BIST

Func Data [31:0]

MBIST Data [7:0] MBIST Data [7:0]

Func RW Cntl

MBIST ON

MBIST ON

Func RW Cntl

MBIST ON

MBIST ON

MBIST

Func Address

MBIST RW Cntl

Array 1MBISTEngine

MBIST Address

Func Address

MBIST RW Cntl

Array 2MBIST Address

Address Mix

MBIST ONFail

MBIST Address

Address Mix

MBIST ONFail

TDI

TCU


TDO

TCU

Macro Test

Scan In

Array

Scan Out


Survey of Embedded SRAM Test Methods

UsabilityUsability in JTAG Usable in Efficient Efficient

Design and ChipAt Speed Flexible

MBIST Yes Yes Yes Mod High Mod Mod Low-Mod

Usability in Burnin

in JTAG based Debug

System Test

Efficient Test

Efficient Bitmap

and Verification Effort

Chip Area

Init sequence g

No Yes No High Low Low V Low V Low

only

Macro Test (scan-based)

Externally stored

patterns

Yes No No Varies Varies Varies V Low None

( ) patterns

FunctionalTest

Externally stored

patterns and full pin

contact

No No No High Mod High Mod LowRAMTEST(pin-based)

Externally stored

patterns


JTAG Test Access Port


JTAG Paradigm

Data Reg 3

Data Reg 2

Data Reg 1

JTAG ControlTMS TAP

FSM

TDO

JTAG ControlTCK FSM

Instruction RegTDI


TAP FSM

Select -IR-Scan

Select-DR-Scan

1

Test-Logic-Reset

Run-Test/Idle

0 1 (TMS)

1

0 1IR-Scan

Capture-IR

DR-Scan

Capture-DR

01

Idle0

0

1

000

Shift-IR

Exit1-IR

Shift-DR

Exit1-DR 11

0 0

11

00

Pause-IR

Exit2-IR

Pause-DR

Exit2-DR

00

1 1

0

00

Update-IRUpdate-DR

1

1 0 1 0

1


TAP Instruction Register OperationOperation

Actual Instruction Register

(LSB)(MSB) Parallel output

TDI Shift Register

Actual Instruction Register

TDO

Fixed capture value

(a) Capture-IR (b) Shift-IR (c) Update-IR


Summary• Why Test

– Manufacturing Process is Imperfect

Wh S• Why Scan– Deeply Sequential IC becomes Combinational

• Debug ScanDebug Scan– Catch bugs while running

• Memory Testing– BIST– Macro Test– Functional TestFunctional Test

• JTAG Protocol– Debug access to registers and actions in chip


BACKUPBACKUP


Examples of Scan Flip-flops and L t hLatches


inp

nout

FLOP with SCAN BC

LSCAN GADGET LK

ACLK

SCAN GADGET

ACLK

Scan_outScan_in

ACLKB

FUNCTIONAL

DoutDin

ACLK

ACLKB

l k


clock

The Basic Scan Flip-Flop (Logical View)

PH2 PH1QDATA

CLK#

CLK

PH2CLK# SIACLK

SOMode Function Clk Sca Scb

BCLK

SOMode Function Clk Sca Scb

normal

scan

Q = Data

Q=si

so=Q

rising edge =0

=0 =1

=0

=0

=0

=1


Scan n-type LATCH (Logical View)

QCLKDATA

PH1SI

ACLK

DATA

BCLKSO

mode Function Clk Sca Scb

normal Q = Data

Q=si

=0

captures on falling

=0

0 =1

=0

=0


scan Q=si

so=Q=0 =1

=0

=0

=1

Reset/Set Scan MSFF Logic Diagrams

Reset MSFF

data DATA

Set-Reset MSFF

datareset_b

reset_b

setDATA

Set MSFF

dataset

DATA

QCLK

Basic Scan MSFF

PH2 PH1QDATA

CLK_BSI

ACLKSO

BCLK


Enable Scan MSFF Logic DiagramsEnable Set-Reset MSFF dataset

DATAreset b

Enable Reset MSFF

datareset_b

DATA

CLK B reset_b

MCLKenable

MCLKenable

TEST_LOCAL_OVRD CLK

CLK_B

CLK_B

MCLK

TEST_LOCAL_OVRD

Enable MSFF

Enable Set MSFF

dataset

DATA

CLK

MCLK

enable

TEST_LOCAL_OVRD

MCLKenable

TEST_LOCAL_OVRD CLK

CLK_B

CLK

CLK_B

PH2 PH1QDATA

CLK_B

CLK

SI

Basic Scan MSFF


SI

ACLKSO

BCLK

Reset/Set Scan MSFF QA Logic Diagrams

Reset MSFF QA

Q’ DATA’Set-Reset MSFF QA

Set MSFF QA

Qreset_b

DATA

reset_b

Q’set

DATA’

Q’set

DATA’

PH2 PH1QDATA

CLK

DATA’Q’

Basic Scan MSFF

PH1CLK_B

SI

ACLKSO

BCLK

DATAQ


Time Borrowing Scan MSFF Logic Diagrams

Time Borrowing MSFF

CLK BTime Borrowing DelayMCLK

CLK

CLK_BTime Borrowing Delay

PH2QDATA

CLK

Basic Scan MSFF

PH2 PH1CLK_B

SI

ACLKSO

BCLK


Reset/Set Scan MSFF ASYNC Logic Diagrams

Reset Basic Scan MSFF

PH2 PH1QDATA CLK

PH1CLK_B

SIACLK

SOBCLK

reset b

ATPG_Mode

Set Basic Scan MSFF

PH2 PH1QDATA CLK

_

CLK_BSI

ACLKSO

BCLK

set

ATPG_Mode_b


Reset/Set Scan PH1 Latch

Reset PH1 LATCH

data DATA

Set-Reset PH1 LATCH

datareset_b

reset_b

setDATA

Set PH1 LATCH

dataset

DATA

QCLK

Scan PH1 LATCH

PH1QCLK

SI

ACLKSO

BCLK

DATA


ACLK BCLK

Enable Scan PH1 LatchEnable Set-Reset PH1 LATCH dataset

DATAreset b

Enable Reset PH1 LATCH

datareset_b

DATA

CLK _

MCLKenable

CLK

MCLKenable

TEST_LOCAL_OVRD

MCLK

TEST_LOCAL_OVRD

Enable PH1 LATCH

Enable Set PH1 LATCH

dataset

DATA

S PH1 LATCH

MCLK

enable CLK

TEST_LOCAL_OVRD

MCLKenable

CLK

TEST_LOCAL_OVRD

PH1QCLK

SI

Scan PH1 LATCH

DATA


SI

ACLKSO

BCLK

Scanout is Not!

DFTSCAN

Not a Test StructureDoesn’t mean scanout pinDoesn’t mean scanout pin of a Scan flop

Scanout Design Completely Independent from Scan Design


Scanout Snapshot Mode Algorithm

• Load the scanout chain

0 1

0 1

• Shift out the data out the ITC

0 1


Scanout Signature Mode Algorithm

0 00

• Initialize the scanout chain

Shift the chain as the observation node creates new data

0001 0

• Shift the chain, as the observation node creates new data

000

• XOR the data in the chain with the observation nodeLoop

0101 0

O e da a e c a e obse a o ode


IO Loopback• Goal: Eliminate the need for full-speed, high pin-

count functional tester for IO testing at HVM

• Key Defect Based IO Test Method to Detect Local/Random Defects – DFT to enable “loop” to be stressed to failure– DFT to enable loop to be stressed to failure– DFT to detect 1st fail and all fail within signal groups– Delta between 1st fail and all fail used to screen Defects in

the IO Loop.p


What is IO Loopback?

Compare Vtt12

patterngenerator ATE

Compareerror

data

generator ATE(optional)

bus clock strobe


Documents

Design for Testability Design for Debugusers.ece.utexas.edu/~mcdermot/vlsi-2/Lecture_17.pdf · Why Scan design? • Makes internal circuit access much more direct to allow for controllability