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Design For Testability
2013.06.03
Sungho Kang
2
Outline
• Introduction
• What is Test?
• Why DFT (Design for Testability)?
• Design for Testability Techniques
• Conclusion
Introduction
3
Determine requirements
Write specifications
Design synthesis and Verification
Fabrication
Manufacturing test
Chips to customer
Customer’s need
Test development
VLSI/SOC Implementation Flow Introduction
4
Current Design Trends Size of SOC devices increases about double every year Rapid increase of silicon size makes test cost higher Complex DFT methodology for high performance Higher test time drive us large ATE investment
Introduction
2006 2007 2008 2009 2010 2011
5
Design Constraints
Area Speed Power Testability
Introduction
Test
6
Format Covert
LoadPattern
Timing
Drive
Compare
What is Test?
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Defect and FaultWhat is Test?
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Stuck-at Fault Only one line in the circuit is faulty at a time The fault is permanent The effect of the fault is as if the faulty node is tied to either Vcc
(s-a-1), or Gnd (s-a-0) The function of the gates in the circuit is unaffected by the fault
A B C
0 0 00 1 01 0 01 1 1
Fault-Free Gate
Vcc
A
BC
Fault: A s-a-1
A B C
0 0 00 1 11 0 01 1 1
Faulty Gate
What is Test?
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Yield
WaferDefects
Faulty chips
Good chips
Unclustered defectsWafer yield = 12/22 = 0.55
Clustered defects (VLSI)Wafer yield = 17/22 = 0.77
What is Test?
10
Test Process
TestProcess
Parts forManufacturing Line
Bad partswhich fail Test
(BF)
Good partswhich pass Test
(GP)
Bad partswhich pass Test
(BP)
Defect Level =BP
GP + BP
What is Test?
Test Cost Trend Constraints : Test Time, Test Pin, Test Data Volume, ATE Investment Target : Test Time Reduction / Test Pin Reduction Transistor production cost reduction exponentially Test cost does not change Test cost can be higher than production cost in future
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[ ITRS Roadmap ]
What is Test?
Test Cost Chip cost
Example : mobile AP (more than 3 million FFs)Die & Substrate / Packaging 75%Manufacturing 25%
– Assembly 40%– Test 40% -> 10% overall– Etc. 20%
Test Process : CP1->CP2->FT->SLT Wafer test : 48% (CP1-ambient temp, CP2-hot temp) Final test : 27% System level test : 25%
12
Why DFT?
AP Manufacturing Cost Qualcomm MSM8960 (2012)
Dual core with baseband (up to 1.7GHz) Scorpion TMSC 28nm / Wafer 300mm Die (die edge seal) 86mm2 Total die per wafer : 700
Manufacturing costFinal tested die : $11Packaged die : $17
– excludes Samsung DDR2 dieTested packaged die : $20
– Excluding Samsung DDR2 package embedded within the package
13
Why DFT?
AP Manufacturing Cost Samsung Exynus 4412 (2012)
Quad core (up to 1.4 ~ 1.7GHz) ARM A9 32nm HKMG / Wafer 300mm Die (die edge seal) 74.3mm2 Total die per wafer : 840
Manufacturing costFinal tested die : $8.00Packaged die : $10.80Tested packaged die : $12.10
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Why DFT?
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Test Pattern and Fault DetectionWhy DFT?
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ATPG Automatic Test Pattern Generation (ATPG)
Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models
FaultList
ATPGCircuit Tests
FaultModel
Why DFT?
17
Design-for-Testability (DFT) Definition
Any design effort to reduce test costs The process of including special features to make a device
easily testable Objective
To reduce in overall design cycle times and test costs without sacrificing the quality of the product
Why need? Difficulty in ATPG : Not effective for large sequential circuits
Advantage Test generation is easy
Disadvantage Area, Timing, Power and Pin Overheads
Why DFT?
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DFT for SOC
RF/AnalogCore
User Defined
Core
User DefinedCore
DRAM
IP
ROM
IP
IP
UDL
BIST Mem BISTTest AccessSoC Test Controller
IO P
ad
IO P
ad
RF/AnalogCore
User Defined
Core
User DefinedCore
DRAM
IP
ROM
IP
IP
UDL
IO P
ad
IO P
ad
Why DFT?
19
IC Cost vs DFT
amount of DFT
testing cost
production cost
total cost
packaging cost
no DFT
Why DFT?
20
DFT Rule Checking
Scan Design, Boundary Scan DesignMemory BIST Design, Logic BIST Design
DFT Rule CheckingStatic Timing Analysis
Test Pattern Generation
Logic SimulationTest Vector Translation
DFT Rule Checking
Full Timing Simulation
DFT Rule Checking
Test Synthesis
Verilog/VHDL Netlist
ATPG
DFT FlowDFT Techniques
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Ad-Hoc DFT Methods Good design practices through experience are used as
guidelines: Test Point Insertion Partition Initialization
DFT Techniques
TEST / NORMAL
QCLR
C
QCLR
CCLEAR
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Scan Test Convert each flip-flop to a scan register
Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register
Contents of FFs can be scanned out and new values scanned in
scan out
scan-in
inputs outputs
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
Flop
LogicCloud
LogicCloud
A MUX is added
DFT Techniques
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Logic BIST
PRPG
Logic BISTcontroller
MISR
Scan chain
Scan chain
Scan chain
Scan chain
Control unitsequences all
activity
Pseudo-RandomPattern Generator
All flops placedinto large number of
relatively shortscan chains
Multiple Input Signature Registercompresses responses into a signature
DFT Techniques
24
Memory BIST
Comparator
Pattern Generator
Controller
RAMTest C
ollar (MU
X)
BIST Module
RAM Controller
Go/No-Go
Patterns: Writing/Reading 0s, 1s,Walking 0s, 1sGalloping 0s, 1s
DFT Techniques
Compress the test patterns Need a decompression units to make original test Patterns Reduction
The size of ATE memory The width of ATE channel Test application time
Test Compression DFT Techniques
SFF SFF SFF SFF SFF SFF
SFF SFF SFF SFF SFF SFF
SFF SFF SFF SFF SFF SFF
Combinational Logic
Decompressor Compressor
26
IEEE 1149.1 Boundary Scan
IDCODE Register
Instruction register
Bypassregister
TAP
MUX
BS Test bus circuitry
TDO
TCK
TDI
TMS
I/O Pad Boundary-scan cell
Boundary-scan path
GlueLogic
S out
TRST
DFT Techniques
27
The Principle of Boundary ScanDFT Techniques
28
1500 Standard for SOC Core test interface between an embedded core and the system chip Test reuse for embedded cores
DFT Techniques
Core
Scan Chain
Scan ChainWBR
WBR
WBR
WBR
WBR
WBR
WBY
WIRWSI
PI PO
WSO
TAMIN TAMOUT
WRCK, WRSTn, WDC
SelectWIR, ShiftWR, CaptureWR, UpdateWR
29
TAM (Test Access Mechanism) Test access mechanism (TAM)
Defined as user-defined test data communication structure Carries test signals from source to module, and module to sink Tests module interconnects via test-wrappers May contain bus, boundary-scan and analog test bus components.
CPUADC
Mem.
PCI
TAM
CUT
TestSource
TestSink
TestPattern
TestResponse
DFT Techniques
30
Conclusion
Test quality
Test cost reduction
Conclusion