Chris Fernandez, Dakota Folger-Reeder, and Michael Shullick

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Design Decisions

On Deck

● History● CPU Choice● Board Layout and Architecture● PPU● Impact

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Brief History of Nintendo and the NES

➔ 1889◆ Nintendo founded in Japan as a playing card

manufacturer➔ 1966

◆ Nintendo shifts to toys➔ 1975

◆ Nintendo has success with arcade games like Donkey Kong

➔ 1983◆ Nintendo’s Family Computer (“Famicom”) released in

Japan◆ Video games crash in North America

➔ 1984◆ Nintendo releases the Advanced Video System home

computer (flopped)➔ 1985

◆ Nintendo released the Nintendo Entertainment System

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NES Dissection

So what’s inside?

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CPU - MOS Technology 6502

● Introduced in 1975, a sixth of the cost of competitors● Designed by same engineers of the Motorola 6800● Cost reduction performed by removing extra features of Motorola 6800

and use of new fabrication technology for depletion-mode MOSFETs.● Used in many famous applications

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6502 Specifications

● Proprietary derivative of the 6502 manufactured by Ricoh

● Accumulator-based with only 6 special registers

● 8-bits, little endian● 16 bit addresses● 1-3 MHz clock● 56 instructions● Fast “zero page” mode for

faster access to first 256 addresses in memory, intended to be quasi-registers

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Ricoh 2A03 - Deviations from MOS 6502

● Hardwired to disable BCD mode of 6502

● Memory-mapped components:○ APU○ DMA○ Game controller polling

● Different versions for different regions

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Architecture

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Memory

● Memory is split between the CPU and the PPU(Picture Processing Unit)

● CPU Memory is divided into 3 main parts, ROM in the cartridges, the CPU RAM, and I/O registers

● CPU and PPU interact only through I/O registers

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Memory and I/O

● The Zero Page memory addressing, which is the first page in memory was also mirrored three times between $0800 and $1FFF.

● If data is written to $0000 it is also written to $0800, $1000, and $1800.● The I/O registers are located between $2000 and $401F● There are 8 main I/O registers, with them being mirrored every 8 bytes

between $2008 and $3FFFF● Addresses $4000 to $4013 are used for sound, and controller input

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Game Cartridges

● Depending on the cartridge games use different amounts of the CPU memory

● If the game has 16 kB of ROM then it only uses $C000-$FFFF● If it has 32 kB of ROM it uses the all of the assigned memory for ROM

which is $8000-$FFFF

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Registers

● CPU had three special purpose registers, and three for general purposes● PC, SP, and Accumulator were the three special purpose registers

○ The SP did not have a stack overflow detection and would just wrap around from $00-$FF○ The Accumulator stored the results of operations and could be used to hold values taken

from memory

● Two Index registers were used for general addressing or as a counter● Processor Status Register held 7 flags based on the result of instructions

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Interrupts

● There are three types of interrupts, IRQ, Non-Maskable Interrupts (NMI) and Reset

● IRQs are generated by either Memory Mappers or by software○ Can be ignored if the Interrupt Disable Flag is set

● NMIs is generated by the PPU at the end of each frame○ Can be ignored if bit 7 of PPU Control Register 1 is clear

● Reset interrupts are generated when the system is first turned on or the reset button is pressed

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Picture Processing Unit (PPU)

● The custom PPU, known as the Ricoh RP2C02, was developed by Ricoh Company, Ltd. for Nintendo

● Has eight registers, visible to the CPU by its address spaces $2000-$2007

● The PPU is responsible for interpreting data to properly display the orientation, spatial position, color, and shape of sprites

● Runs 3 times faster than the CPU clock speed

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NES board, PPU framed in red, CPU in blue

Picture Processing Unit (PPU) cont.

● The PPU sends 240 visible scan lines of sprite data to televisions to create graphical frames

● Finite set of 54 hardware controlled colors for a total of 25 concurrent colors on screen

● Able to display up to 64 moving objects on screen at a time

● Resolves at a whopping 256 × 240 pixels ● Extended capabilities through the usage of

mappers 15

NES graphical output to TV

PPU Memory Designation

● PPU operates in smallest graphical unit of “tiles”

● 8 kB (2 tiles of 4 kB) of ROM/RAM allocated on the Game Pak itself for tiles data

● 2 kB of external RAM to store extra maps/nametables

● 32 bytes of internal SRAM for color data● 288 total bytes of internal DRAM for Object

Attribute Memory (OAM)16

Internals of NES Game Paks

PPU Attribute Tables

● 64-byte 8x8 arrays that control spatially which color pallet should be applied to the objects in the array

● Each byte in the array is responsible for a 4x4 tile (32x32 pixel)

● This means every two-bits in a byte has the information for a quadrant of a graphical tile

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Attribute Table example

PPU Rendering Process ● Each frame is 89,342 PPU clock cycles long● The PPU renders 262 total scanlines per frame, each lasting for a total of

341 PPU cycles ● Each rendered tile takes 4 memory accesses, each requiring 2 PPU cycles

per access ● Using a combination of latches, shift registers, and counters the PPU is

read in the data from memory● This data is held in the latches until it is time to be fed to the appropriate

shift registers (every 8 clock cycles)

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19PPU Timing Diagram

Impact & Legacy

● Poor design of front-loading cartridge● Lockout malfunction ● Judged the second greatest console of all time by PC Magazine● Succeeded by the Super Nintendo Entertainment System (SNES)● NES Classic Edition released in 2016 (still unavailable everywhere)

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References

● https://wiki.nesdev.com/w/index.php/PPU● https://wiki.nesdev.com/w/index.php/PPU_registers● https://wiki.nesdev.com/w/index.php/PPU_rendering● https://en.wikipedia.org/wiki/Picture_Processing_Unit● https://fms.komkon.org/EMUL8/NES.html● http://nesdev.com/NESDoc.pdf

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