Design and Verification of an Image Processing CPU Using UVM

byGreg Tumbush

Tumbush Enterprises

Co-authorMilos Becvar

EM Microelectronic-US

TUMBUSHENTERPRISES

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Introduction:•Work performed at EM Microelectronic-US•Co-author, Milos Becvar, did design and software•EM’s ASICs

•Mixed signal•Very low power•Optimized for area•Small design teams•Short development times•Low cost, high volume

•Not satisfied with previous verification results

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Design of CPU: overview•Why a CPU?•Not a trivial effort, need to justify•CPU requirements for our application

•No support for C/C++ or legacy SW•Efficient execution of application•Small silicon area•Multiplication and division•Support of hardware accelerator

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Design of CPU: architecture

ProgramMemory

(1K x 16b)

PC(9:0)

+1

Instr.Decod

er

BranchAddr.

Registers16 x 16b Ra

Rb

Imm8RegB

RegA

DataMemory

(512 x 16b)

Control Signals

ALU

DIVIDE

OperandA

Flags

Result

Control Signals

Result

MultiplierStage1

MultiplierStage2

Control Signals

Data_Read

Reg_WB_Lo

Reg_WB_Hi

Instruction Fetch

Instruction Decode &Register Read

Execute / Mult1 WB/Mult2 MultWB

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Design of CPU: hazards•Data hazards

ADD R1, R0 ;; R1=R1+R0SUB R2, R1 ;; R2=R2-R1

<branch instruction><instruction after branch>

<multiply instruction><cannot write into register>

Old value of R1 used

Always executed

•Structural hazards

•Control hazards

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Verification of CPU: overview•Unique verification challenges•Chosen methodology must:

•have a quick development time •randomly generate instructions•steer the randomly generated instructions into interesting corner cases•use functional coverage to stop the testbench once functional coverage is obtained

•UVM is a tough sell to the uninitiated

UVM

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Verif. of CPU: architecture

Firmware Agent

Firmware RAM I/F

Instructions

Image Agent

Image I/F

Image

slave

Scoreboard

Golden CPU Flags

Golden CPU Regs

Hardware Accelerator Transaction Level Model,

and checkers

CPU Transaction Level Model and checkers

Data RAM RAM I/F DUT (CPU+Hardware Accelerator)

RAM Agent

Golden RAM

ram_trans firmware_results

Image File

image_transinstruction

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Verif. of CPU: UVM Agent

Agent

Driver

Sequencer

transactions

pin level

Monitor

pin level

*_trans

to subscriber

uvm_analysis_port (1 or more)

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Verif. of CPU: Firmware Agent•An active agent•Sequencer creates instruction objects•Driver “assembles” instruction objects•Monitor:

•Collects state of CPU•Stores information in a firmware_results object•Passes firmware_results object to subscriber•Collects machine code fetched by DUV•Stores machine code in instruction object•Passes instruction object to subscriber

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Verif. of CPU: instructionclass instruction extends uvm_sequence_item; `uvm_object_utils(instruction) function new(string name=""); super.new(name); endfunction rand opcode_e opcode; rand src_dest_e Rb, Ra; rand bit [9:0] Addr; …… static string instruction_str; function string get_instruction(); endfunctionendclass

See in waveform!

Disassembler

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Verif. of CPU: firmware_resultsclass firmware_results extends uvm_sequence_item; `uvm_object_utils(firmware_results) logic signed [15:0] gp_reg[16]; logic SF, OF, ZF, CF; logic [FIRMWARE_RAM_ADDR_WIDTH-1:0] PC, RAR; logic [15:0] instr_code; bit ram_write; bit [RAM_ADDR_WIDTH-1:0] write_addr; bit [RAM_DATA_SIZE-1:0] data_write; …endclass

State of CPU

Write transaction

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Verif. of CPU: scoreboard Scoreboard (CPU portion only)

Firmware Agent

uvm_analysis_port #(instruction) instruction_aport

uvm_analysis_port #(firmware_results) firmware_results_aport

gold_subscriber

implicit analysis_export

rtl_subscriber

implicit analysis_export

uvm_analysis_export #(instruction) gold_aexport

uvm_analysis_export #(firmware_results) rtl_aexport

instruction objects

firmware_results objects

uvm_analysis_port #(firmware_results) rtl_firmware_results_aport;

uvm_analysis_port #(firmware_results) gold_firmware_results_aport;

firmware_results objects

firmware_comparatoruvm_analysis_export #(firmware_results)

gold_firmware_results_export;uvm_analysis_export #(firmware_results)

rtl_firmware_results_export;

firmware_results objects

instruction objects firmware_results objects

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Verif. of CPU: gold_subscriberclass gold_subscriber extends uvm_subscriber #(instruction);

`uvm_component_utils(gold_subscriber) firmware_results firmware_results_h; uvm_analysis_port #(firmware_results) gold_firmware_results_aport; function void build_phase (uvm_phase phase); // create gold_firmware_results_aport object endfunction function void write(instruction t); case (t.opcode) ADD: firmware_results_h.gp_reg[t.Rb] = val(t.Ra) + val(t.Rb); .... endcase gold_firmware_results_aport.write(firmware_results_h); endfunctionendclass

Golden model

Send to gold_firmware_results_aport

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Functional Coverage•Instructions can be grouped

•Two 16-bit operands•One 16-bit operand•One 16-bit operand and 8-bit immediate•etc.

•Create coverpoints for each operand, immediate,etc•Cross coverpoints for each instruction group•Monitor cross coverage, reduce probability if coverage=100%

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Functional Coverage: LDRall_opcodes_Ra_Imm8: coverpoint instr.opcode { bins opcodes[] = {…, LDR, STR, …}; option.weight = 0; }all_Ra: coverpoint instr.Ra{ option.weight = 0;}Imm8_range: coverpoint instr.Imm8 { bins maximum = {(2**8)-1};  bins mid = {[1:(2**8)-2]}; bins minimum = {0}; option.weight = 0;}all_opcodes_Ra_Imm8_x_Ra_x_Imm8_range: cross all_opcodes_Ra_Imm8, all_Ra, Imm8_range;

Monitored during simulation

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Results•Design spec to verification closure: 12 man weeks•~14,000 coverage bins•350,000-450,000 random instructions required•100% statement coverage with no extra tests.•No additional bugs found during system level verification•Verified assembler as well•Silicon evaluation revealed no bugs

First Pass Success!

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Agenda:•Introduction•Design of CPU•Verification of CPU•Functional Coverage•Results•Summary

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Summary•A custom cpu is warranted in some situations•Don’t forget the software task•Verifying a CPU is hard!•Don’t try to test everything at the block level•UVM appropriate for small ASICs/FPGAs•UVM appropriate for block level verification•Thanks to EM Microelectronic-US