Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell

Microelectronics Reliability xxx (2014) xxx–xxx

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Design and analysis of noise margin, write ability and read stabilityof organic and hybrid 6-T SRAM cell

http://dx.doi.org/10.1016/j.microrel.2014.08.0120026-2714/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author at: Department of Polymer and Process Engineering,Indian Institute of Technology, Roorkee 247667, India. Tel.: +91 1332 285662; fax:+91 1332 273560.

E-mail addresses: [email protected], [email protected] (B. Kumar).

Please cite this article in press as: Kumar B et al. Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAMicroelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.08.012

Brijesh Kumar a,b,c,⇑, Brajesh Kumar Kaushik b, Yuvraj Singh Negi a

a Department of Polymer and Process Engineering, Indian Institute of Technology, Roorkee 247667, Indiab Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee 247667, Indiac Department of Electronics and Communication Engineering, Graphic Era University, Dehradun 248001, India

a r t i c l e i n f o

Article history:Received 18 December 2013Received in revised form 8 August 2014Accepted 11 August 2014Available online xxxx

Keywords:All-p organic SRAMHybrid SRAMNoise marginOrganic complementary SRAMRead stabilityWrite access time

a b s t r a c t

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). Theperformance in terms of static noise margin (SNM), read stability and write ability for all-p organic(Pentacene–Pentacene), organic complementary (Pentacene–C60) and hybrid complementary (Penta-cene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-Dnumerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios.The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verifiedwith reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cellis validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid andorganic SRAM cells are optimized for achieving best performance of read and write operations and there-after, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than theall-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On theother hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the readstability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, thisorganic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access timein comparison to the hybrid cell. To achieve an overall improved performance, the organic complemen-tary SRAM cell is designed such that the access transistors are pentacene based p-type instead of oftenused n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access timein comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and readstability that too at substantially lower width of p-type access OTFTs.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Over the last decade, aggressive efforts have been devoted todevelop the organic electronic circuits. Undoubtedly, organic elec-tronics is predicted to have a range of vital and high-end applica-tions, such as flat panel display, light emitting diode (LED) [1],radio frequency identification (RFID) tag [2], sensor [3], static ran-dom access memory (SRAM) [4], e-paper [5], organic photovoltaiccells [6] and flexible integrated circuits [7]. Organic material offersan opportunity to produce thin film transistors (TFTs) on a largearea, with considerably lower cost and process temperature thantheir inorganic counterparts. Consistent advancements in organicmaterial based fabrication techniques would encourage researchers

to exploit various flexible substrates, such as paper [8], plastic [9],glass [10] and fiber [11] for low cost and light-weight flexible elec-tronic applications. Cost effective fabrication of organic TFTs(OTFTs) on the flexible substrate can eventually derive huge benefiton various fronts.

Organic memory design and fabrication has been identified asone of the rapidly emerging research area by International Tech-nology Roadmap for Semiconductor (ITRS)-2012. Organic materialsbased memory devices have attracted lots of interest due to theirbetter structural flexibility and low cost solution processability[12]. Inexpensive and fast memory devices characterized by longerdata retention time and higher density are in huge demand.Organic memory demonstrates unique characteristics being non-volatile, flexible, inexpensive, lightweight and capable of printingcomponents directly on to the flexible substrates [13,14]. Thesememory devices are potentially useful in organic RFID tags (tran-sponder chip), smart cards and disposable circuitry [15,16].

M cell.

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2 B. Kumar et al. / Microelectronics Reliability xxx (2014) xxx–xxx

Storage capacity and operational speed are two major factors indetermining the efficiency of a memory circuit [17]. The perfor-mance of silicon-based memory is quite good, however, the pro-duction cost and flexibility of silicon based SRAM is an obviousconstraint. Silicon based SRAM cells are widely employed in thehigh performance integrated circuits [18], however, organic SRAMstill requires serious efforts for a reasonable performance. Only fewSRAM cell designs based on organic TFTs have been reported[4,16,19] till date. Takamiya et al. [4] demonstrated a pentacenebased 5-T organic p-type SRAM cell that significantly reduced theSRAM cell area by 20% and write time by 69% over the conventional6-TFT cell. Later, Fukuda et al. [19] in 2011 reported a DNTT {dinap-tho [2,3-b:20,30-f] thieno [3,2-b]thiophene}, p-type organic semi-conductor (OSC) based 6-T SRAM cell with a bias supply of 4 V.This all-p organic SRAM exhibited the write access time and staticnoise margin of 2 ms and 0.44 V, respectively. Recently, Guerinet al. [16] in 2013 reported an organic SRAM cell operating at50 Hz using polytriarylamine based p-type and Acene-diimidebased n-type organic TFTs.

Most of the OTFT-based SRAM cells are designed using only p-type transistors [4,19] due to higher mobility and better intrinsicstability of p-type materials in comparison to n-type. However, acomplementary design is beneficial in terms of low static powerconsumption, high noise margin and operational robustness. Forsuch complementary organic SRAM cell both p- and n-type transis-tors should exhibit comparable mobility and threshold voltage (Vt).However, the unavailability of high mobility n-type organic tran-sistor enforced researchers to propose an all p-type organic SRAMcircuit. These all p-type designs also faces several challenges interms of low voltage swings, poor balance between pull-up andpull-down operation, high power dissipation and low noise mar-gins. Taking these limitations into account, a hybrid complemen-tary circuit was first proposed by Dodabalapur et al. [20]. Thishybrid inverter circuit design replaced the n-type organic transis-tor by an inorganic hydrogenated amorphous silicon (a-Si:H) TFT.

Several researchers [20–24] have extensively studied invertercircuits based on organic and/or inorganic transistors, however,no attempt has been made to analyze the hybrid SRAM cell. Takingcognizance of this fact, this research paper compares the perfor-mance of various SRAM cells, made up of organic and/or inorganicmaterial combinations through 2-D numerical device simulation.The simulation result of each device is verified with respect toreported experimental results [21,25]. Motivated by the prior out-comes demonstrating remarkable merits of different TFTs, thisresearch paper analyzes SRAM cells based on fully organic andhybrid designs. The static and dynamic behavior of the memorycell are analyzed by different device combinations. Subsequently,performance parameters including static noise margin, read stabil-ity and write access time are obtained and compared at differentcell and pull-up ratios. Additionally, this research paper comparesthe performance of organic complementary SRAM cell based on n-type and p-type access transistors.

This paper is arranged in five sections along with the currentintroductory Section 1. The summary of independent designs ofdifferent TFTs is presented in Section 2. The performances of all-p, hybrid complementary and organic complementary SRAM cellwith different TFT combinations are analyzed at different cell andpull-up ratios in Section 3. A comparison between the perfor-mances of organic SRAM cell with p- and n-type access transistorsis presented in Section 4. Finally, Section 5 summarizes the impor-tant outcomes of the proposed work.

2. Performance of organic/inorganic p- and n-type devices

This section comprehensively presents the characteristics of allthe TFTs employed for different SRAM designs. The dimensions and

Please cite this article in press as: Kumar B et al. Design and analysis of noise mMicroelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.08.012

properties of pentacene, C60 and ZnO based TFTs are shown inTables 1 and 2, respectively.

The devices and later on the circuits are analyzed using finiteelement based Silvaco Atlas 2-D numerical device simulator [26].It incorporates Poole-Frenkel mobility (PFM) model that effectivelyanalyzes DC, transient and small signal AC behavior of the analogand digital circuits. The simulated performance parameters of thedevices in terms of drain current, threshold voltage, mobility, on-off current ratio and leakage current are compared with thereported experimental results [21,25] in Table 3. The simulatedresults of all TFTs are in good agreement with the experimentalresults with an average error of 8% and 5.7% for threshold voltageand mobility, respectively. Among all TFTs, pentacene based TFTshows superior performance along with smallest threshold voltageand reasonable mobility. Compared to ZnO based TFT, C60 deviceexhibits inferior performance in terms of mobility (lower by 13%)and threshold voltage (higher by 20%) due to a significant reduc-tion of 72% in the capacitance per unit area. Large leakage current(Ileakage) is noticed in the ZnO based TFT. This current is seven timeshigher in comparison to the C60 based TFT, as summarized inTable 3.

3. Performance of SRAM cell with different TFT combinations

The performance of an SRAM cell is characterized mainly interms of SNM during stand by and read operations. Besides this,the time required to read the stored data correctly without flippingit and the speed of modifying the stored data during write opera-tion are other important performance parameters. With downscal-ing of feature size, retaining the performance of cell at same level isbecoming increasingly challenging. While selecting the W/L ratiosfor the three TFTs (pull-up, pull-down and access as shown inFig. 1), the two basic requirements are (1) non-destructive readingof the stored information and (2) successful modification of thestored data during write operation.

The ratio of transconductances of pull down to access transistorknown as the cell ratio (bc) determines the cell stability during readoperation. However, the transconductance ratio of the pull-up tothe access transistor, termed as the pull-up ratio (bp) determinesthe writing ability of the cell. The performance of SRAM cell interms of SNM, readability and writability for different combina-tions of TFTs is discussed in the following subsections. The SRAMconfigurations are simulated under mix-mode, wherein, each inputfile is split into two parts; one of them describes the circuit net-list,and the other explains device simulation and model parameters.

3.1. Static noise margin

The stability of an SRAM cell is an important parameter thatdetermines the retention of stored data both in standby and readaccess modes. The stability, usually defined by the SNM is a mea-sure of maximum static noise voltage that the cell can withstandwithout altering the stored data [30]. This can be representedgraphically by plotting superimposed voltage transfer characteris-tics (VTCs) of two symmetrical inverters resulting in two-lobedcurve. The area inside the two lobes is a measure of sensitivity ofthe cell to the external noise, whereas, the SNM is representedby the side of the maximum possible nested square between thetwo superimposed curves. In all-p type SRAM cell design, it is nec-essary that the drain current of load TFT be kept constant whichcan be achieved by connecting the gate and source terminals ofthe load leading to zero-Vgs load logic (ZVLL) as shown in Fig. 2.In this configuration, the load TFTs (P3, P4) are always conductingregardless of input and output voltage levels, since the conditionVgs > Vt is satisfied.

argin, write ability and read stability of organic and hybrid 6-T SRAM cell.


Table 1Dimensional parameters and material combinations of TFTs used in SRAM cell designs.

Device dimension Organic TFTs Inorganic TFT

Pentacene (p-type) [21] C60 (n-type) [25] ZnO (n-type) [21]

Channel length (L) (lm) 90 100 90Channel width (W) (lm) 500 1000 500Insulator thickness (tox) (nm) 12.5 (Al2O3 + SiO2) 144 (SiO2 + TiSiO2) 12.5 (Al2O3 + SiO2)OSC thickness (tosc) (nm) 50 (Pentacene) 60 (C60) 60 (ZnO)Thickness of S/D (ts/td) (nm) 10 (Al) 101 (LiF + Al) 10 (Al)Gate thickness (tg) (nm) 10 (n+ Si) 30 (p-Si) 10 (p-Si)

Table 2Pentacene, C60 and ZnO semiconductor properties used for TFTs in different SRAM cell designs.

Properties Organic TFTs Inorganic TFT

Pentacene [10,21,27,29] C60 [25,26] ZnO [26,28]

Band gap, Eg (eV) 2.2 2.6 3.3Electron affinity (eV) 2.8 3.7 4.5Density of conduction band, NC (cm�3) 1 � 1021 1 � 1021 2 � 1020

Density of valance band, NV (cm�3) 1 � 1021 1 � 1021 2 � 1020

Doping concentration (cm�3) 4 � 1017 4 � 1014 4 � 1014

Permittivity 4.0 4.5 2.0

Table 3Comparison between simulated [22] and experimental performance parameters for different p- and n-type devices.

TFT device semiconductor Cox (nF/cm2) Ids (lA) Vt (V) l (cm2/V s) Ion/Ioff Ileakage (A)

Sim. Exp. Sim. Exp. Sim. Exp. Sim. Exp. Sim. Exp.

Pentacene TFT [21] 350 3.7 3.5 �0.65 �0.6 1.0 1.03 1.34 � 104 2.1 � 104 2.6 � 10�10 1.8 � 10�10

C60: n-TFT [25] 96.5 5.2 5.3 1.3 1.13 0.92 1.0 0.84 � 105 1 � 105 6.2 � 10�11 5 � 10�11

ZnO: n-TFT [21] 350 2.7 2.5 1.1 1.05 1.06 1.12 0.7 � 104 1.2 � 104 4.2 � 10�10 2.1 � 10�10

P2

N2

P1

N1

N3

BLB BL

Datab Data

WL

N4

VDD

12

Fig. 1. Schematic of hybrid/organic complementary SRAM cell.

P2

P4

P1

P3

P5

BLB BL

Datab Data

WL

P6

VDD

2 1

Fig. 2. Schematic of all-p organic SRAM cell.

VIN2,VOUT2

VIN1,VOUT1

VILVOL

VIH

VOH

INV2

INV1

V OU

T, V IN

(V)

VIN, VOU (V)

VIN2,VOUT2

VDD

Fig. 3. VTCs of two symmetrical inverters of p-type SRAM in ZVLL configuration.

B. Kumar et al. / Microelectronics Reliability xxx (2014) xxx–xxx 3

Fig. 3 shows the VTCs of two symmetrical inverters, INV1 (P1,P3) and INV2 (P2, P4) of all-p SRAM cell. Point VIN1 in VTC repre-sents the input voltage required to switch the driver TFT (P1) fromlinear to the saturation region while the load TFT is operating in


the saturation (P3). Similarly, voltage VIN2 is the input voltagewhen the load TFT switches (P4) from saturation to linear regime,while, driving TFT remains in saturation (P2). When VIN liesbetween 0 and VIN1, the driver and load TFTs operates in linearand saturation region, respectively.

Considering equal current flowing through two TFTs, the outputvoltage [31,32] can be expressed as

VOUT ¼ f lin;satðVINÞ ¼ VIN � Vt;D

þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiVDD þ Vt;D � VINð Þ2 � 1

kR

� �V2

t;L

s; 0 < VIN < VIN1 ð1Þ

where Vt,D and Vt,L are the threshold voltage of driver TFT (P1, P2)and load TFT (P3, P4), respectively and kR is the transconductance




ratio of load to the driver. Furthermore, the driver and load TFTsoperates in saturation and linear regime, when input voltage liesbetween VIN2 and VDD leading to the output voltage expression as

VOUT ¼ f sat;linðVINÞ ¼ Vt;L � kR

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1

k2R

V2t;L �

1kR

VDD þ Vt;D � VINð Þ2s

;

VIN2 < VIN < VDD ð2Þ

For an input voltage between VIN1 and VIN2, both TFTs operate inthe saturation region. Since, most of the organic TFTs exhibit highoutput resistance, therefore VIN1 and VIN2 can be assumed at anapproximately same potential i.e VIN [32].

The current relation for driver and load TFTs operating in satu-ration region can be expressed as

kL

20� Vt;Lð Þ2 ¼ kD

2ðVIN � VDD � Vt;DÞ2 ð3Þ

where kL and kD are the respective transconductance of load anddriver transistors. On solving, VIN1 and VIN2 can be expressed as

VIN ¼ VIN1 ¼ VIN2 ¼ VDD þ Vt;D �

ffiffiffiffiffiffiffiffiffiffiffiffi1kR

� �sVt;L ð4Þ

Additionally, the corresponding output voltage VOUT1 and VOUT2

can be derived by substituting VIN1 and VIN2 in Eqs. (2) and (3),respectively.

VOUT1 ¼ VDD �


� �sVt;L ð5Þ

VOUT2 ¼ Vt;L ð6Þ

Furthermore, to calculate the noise margin, a point (VIN2 andVOUT2) is marked on the transfer characteristics of inverter-2, asshown in Fig. 3. From this point, a straight line (y = x) is drawn thatforms the right-top corner (at the intersection point of straight linewith VTC of inverter-1) of the largest possible nested square in thelobe. With the known expression of the transfer curve, the SNM interms of side length of the fitted square can be obtained as [31,32]:

SNM ¼ VDD �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiVDD þ Vt;D �


� �sVt;L

!2

þ 1kR

� �V2

t;L

vuut ð7Þ

Noise margin strongly depends on the VDD, kR and thresholdvoltages of driver and load TFTs. The width of a load transistor(connected in zero-Vgs mode) should be much higher than the dri-ver to achieve an adequate pull down response [33]. The resultingbutterfly curves for the inverters of p-SRAM cell during standbyand read (access) modes are shown in Fig. 4(a). The SNM duringhold state is 1.46 V that closely matches with the analytically cal-culated value of 1.5 V with an error of 2.6%.

To achieve high noise margins, the output high voltage, VOH

should be high enough. However, in only p-type designs, the valueof VOH is limited to VDD–Vt,L [31,33]. It is due to threshold voltagedrop across the load TFT, since it remains always in ‘ON’ condition,thereby attaining a lower magnitude even in the standby mode.During read operation, the high to low transition of inverter isnot as steep as obtained during standby mode. It is due to thereduction in the strength of pull down transistor. A slow pull downaction reduces the area of the lobe and thus SNM too. The SNM plotduring read operation at different cell ratios of p-SRAM cell isshown in Fig. 4(b).

The noise margin is near to the desired value (SNM in standbymode) at bc of 20 and reduces significantly with scaling down ofthe cell ratio. This cell is found unstable at bc 6 5, since the poten-tial difference of the two complementary storage points is zerothat is due to stronger access transistors. This in-turn produces


ambiguity in reading the two storage nodes. Similarly, the butterflycurves obtained during hold and read modes for the hybrid andorganic complementary SRAM cells are plotted in Fig. 5(a) and(b), respectively. The width of pull-up transistors, P1 and P2 inall the proposed SRAM cells is 500 lm, whereas, the width ratioof pull-down to the pull-up transistor is ten and eighteen for thehybrid and organic complementary SRAM cell, respectively.

The hold SNM of hybrid SRAM cell is almost two times of theSNM of all p-SRAM. High noise immunity due to larger noise mar-gins is one of the major benefits of using complementary SRAMdesigns. Compared to the hybrid cell, the organic complementarySRAM cell shows a reduction of 18% in the SNM, since the highto low transition is not that much steep. It is due to a reductionof 15% and 72% in the mobility and capacitance, respectively ofC60 based TFT in comparison to ZnO. Combined plots of readSNM for hybrid and organic SRAM with respect to the cell ratioare illustrated in Fig. 6. Compared to organic complementary cell,the read SNM of hybrid cell is higher and a proportional reductionis observed for both the cells with scaling down of cell ratio up tofive. In addition, the hybrid cell exhibits a sharp fall in the readSNM for the cell ratio below five. It is due to a high leakage currentof ZnO based transistor as well as a significant change in the poten-tial of stored data with an effect of increasing the strength of accesstransistors.

3.2. Read operation

During a read operation, the cell is coupled to the bit linesthrough the access transistors. The word line voltage turns onthe access transistors that allow the logical state of the cell to besensed through the bit lines. Prior to turning on the access transis-tors, both the bit lines are pre-charged to the VDD/2 level. When theaccess TFTs are tuned on, it allows the flow of the charge from BL tonode-1 as well as from node-2 to BLB (if 0/1 is stored at node-1/2).Therefore, a voltage divider is formed through access and pulldown transistors between the pre-charged bit line potential andground. The sense amplifier [34] as shown in Fig. 7 senses thepotential difference of bit lines. This sensing amplifier sends analert to the word line to be reverted from the current state aftersensing the potential difference in the bit lines. This in turn isolatesthe bit lines from the cell, thereby leading the node potential toreturn back to their previous values. During a read access the nodevoltage deviates from its standby state that strongly depends onthe cell ratio. A smaller cell ratio translates to the lowering ofpotential difference of the complementary storage, therebyincreasing the possibility of flipping the state.

The operational circuit of complementary SRAM cell for storage‘0’ at node-1 (Data) and ‘1’ at node-2 (Datab) is illustrated in Fig. 8.A smaller cell ratio can force an unintended change in the storedinformation [18] by increasing the node potential (storage-0)above the threshold voltage of pull down TFT. Therefore, to avoidthe violation of stored data during a read access, the condition thatmust be satisfied, is given as

Vmax;node-1 < Vt;N2 ð8Þ

where Vmax,node-1 and Vt,N2 represent the maximum voltage at node-1 and threshold voltage of N2 transistor, respectively.

To access the stored data during a read operation, it is straight-way required to build up a voltage difference between the bit linesbut without altering the node voltages too much. To meet out thisrequirement, following condition should be satisfied.

RonðN1Þ < RonðN3Þ ð9Þ

where Ron(N1) and Ron(N3) are respective resistance of pull-downTFT, N1 and access TFT, N3. This implies that the N1 transistorshould be stronger than N3. This can be achieved by keeping the



(a) (b)

0 2 4 6 8 100

2

4

6

8

10

Data, Datab (V)

Read mode

Stand-by modep-SRAM

Dat

ab, D

ata

(V)

0 5 10 15 20

0.0

0.5

1.0

1.5 p-SRAM

Rea

d SN

M (V

)

βC

Fig. 4. (a) Butterfly curves during standby and read mode; (b) read SNM (RSNM) as a function of cell ratio for all-p SRAM cell.

(a) (b)

0 2 4 6 8 10

0

2

4

6

8

10

Dat

ab, D

ata

(V)

Data, Datab (V)

Read mode

Stand-by mode

Hybrid-SRAM

0 2 4 6 8 100

2

4

6

8

10

Dat

ab, D

ata

(V)

Organic Comp.-SRAM

Data, Datab (V)

Read mode

Stand-by mode

Fig. 5. Butterfly curves during standby and read mode for (a) hybrid; and (b) organic complementary SRAM cells.

0 5 10 15 20

0

1

2

3

4

Organic Comp.-SRAM

Hybrid-SRAM

βc

Rea

d SN

M (V

)

Fig. 6. Read SNM with respect to cell ratio, bc for hybrid and organic complemen-tary SRAM cells.

Access Transistor 2 4-T SRAM Cell

Access Transistor 1

WL

BLBLB

Datab Data

Sensing Amplifier

VBLB

0 at node 1; VBL-VBLB < 0 1 at node 1; VBL-VBLB > 0

2 1

VBL

VDD

Fig. 7. Block diagram of SRAM cell along with sensing amplifier in read mode.


width of pull down transistor much wider than the access transis-tor. During a read access the transistor N3 operates in saturation,whereas N1 in linear region. Considering same current in both TFTs.

kN3

2VDD � Vnode-1 � Vt;nð Þ2 ¼ kN1

22ðVDD � Vt;nÞVnode-1 � V2

node-1

n oð10Þ


kN3

kN1¼ W=Lð ÞN3

ðW=LÞN1<

2ðVDD � 1:5Vt;nÞVt;n

ðVDD � 2Vt;nÞ2ð11Þ

By symmetry, same relation is considered for TFTs N2 and N4 asspecified by Eq. (11).

Transient response of hybrid SRAM during reading of 0 (1) and 1(0) at the Data (Datab) node is shown in Fig. 9(a) and (b), respec-tively, whereas respective waveforms for organic complementarySRAM are presented in Fig. 10(a) and (b), respectively. After turn-ing ON the access transistors, the bit line voltage (VBL) is decreased(Figs. 9(a) and 10(a)) in both the cells, but potential of the Datanode is maintained close to the 0 level, since TFT N1 is operating



P2

N2

P1

N1

N3

BLB BL

Datab Data

WL

N4

VDD

12

OFF

OFF

ON

ON

Fig. 8. Operational circuit schematic of hybrid/organic SRAM cell for storage ‘0’ atData and ‘1’ at Datab nodes.


in the linear region. On the other hand, potential at Datab nodedecreases quickly in the hybrid cell, whereas, a minute drop isobserved in organic complementary cell. This is due to large leak-age current in the ZnO based TFT. A seven times higher leakagecurrent is observed in n-type ZnO TFT in comparison to the C60

based TFT, as summarized in Table 3. This enables the conductionin transistor N2 even at zero Vgs that in turn reduces the node(Datab) potential. Therefore, the potential of complementary bitline (VBLB) rises minutely.

The p-SRAM cell operates in a slightly different way to the con-ventional cell, wherein the load TFTs conducts as a constant

(a)

0 2 4 6 8 10

0

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

Hybrid-SRAMWL

Datab

Data

BLBLB

Fig. 9. Transient response of pentacene–ZnO SRAM cell during read access (bc = 20) for (a

(a)

0 2 4 6 8 100

2

4

6

8

10Organic Comp.-SRAM

Data

Datab

BL

BLB

WL

t (ms)

Pote

ntia

l (V)

Fig. 10. Transient response of pentacene–C60 SRAM cell during read access (bc = 20) for (a


current source as shown in Fig. 2. Considering the same storageas discussed earlier (‘0’ at Data and ‘1’ at Datab nodes), the poten-tial at the Data node always lies near the threshold voltage of loadtransistor, therefore the output voltage does not pull down to theground level [33]. Additionally, the voltage pulls up below theVDD level even in the standby mode. During read operation, thepotential of Data node increases from Vt,,L due to flow of chargefrom BL to the node-1, thereby reducing the potential VBL. Simi-larly, a fall is observed in the potential of Datab node that resultsin a proportional rise in the magnitude of VBLB as shown inFig. 11(a) and (b), correspondingly to storage 0 and 1, respectivelyat the Data node.

The read access time of a cell is characterized by the time takenfor jVBL � VBLBj potential to attain a threshold level after turning ‘ON’the access transistors. Here, the threshold level of 1.5 V is consid-ered, since a slight increment in this difference voltage can reducethe cell stability of hybrid cell substantially, as shown in Fig. 9(a).The hybrid SRAM cell shows an increment of 46% in the read accesstime in comparison to the organic complementary SRAM cell, assummarized in Table 4. This is due to changing the potential ofone bit line only during read operation. However, in the organicSRAM cell, the potential of both the bit lines changes simulta-neously, thereby requiring lesser time to attain the required differ-ence voltage. Additionally, an increment of 26% and 22% in the cellstability is observed for the organic SRAM cell in comparison to theall-p and hybrid SRAM cell. The SNM of three different SRAMcell designs are analyzed, wherein their performance can be

(b)

0 2 4 6 8 100

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

BLB

BL

Datab

DataWL

Hybrid-SRAM

) storage ‘0’ at Data and ‘1’ at Datab; and (b) storage ‘1’ at Data and ‘0’ at Datab nodes.

(b)

0 2 4 6 8 100

2

4

6

8

10

Pote

ntia

l (V) WL

BL

BLBDatab

Data

t (ms)

Organic Comp.-SRAM

) storage ‘0’ at Data and ‘1’ at Datab; and (b) Storage ‘1’ at Data and ‘0’ at Datab nodes.



(a) (b)

0 2 4 6 8 100

2

4

6

8

10

WL

t (ms)

Pote

ntia

l (V)

BLB

BL

Data

Datab

p-SRAM

0 2 4 6 8 100

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

p-SRAM

BLB

BL

WL

Datab

Data

Fig. 11. Transient response of p-SRAM cell during read access (bc = 20) for (a) storage ‘0’ at Data and ‘1’ at Datab; and (b) storage ‘1’ at Data and ‘0’ at Datab nodes.

Table 4Reading time and magnitude of stored data during read operation (bc = 20) for different SRAM cells.

SRAM design Class of SRAM cell Reading time (ls) Magnitude of stored data during read access (V) Difference in magnitude of storage (V)

Storage-1 Storage-0

Organic all-p Type-1 95 8.1 0.5 7.6Organic (pentacene–C60) Type-2 72 9.9 0.3 9.6Hybrid (pentacene–ZnO) Type-3 105 8.1 0.2 7.9


summarized as Type-3 > Type-2 > Type-1 (Section 3.1). The readstability and reading time performance of three different SRAMcells can be summarized as Type-2 > Type-1 > Type-3 as depictedin Table 4.

3.3. Write operation

To perform a write operation, appropriate biasing voltage needsto be applied at the bit lines that forces the cell to be placed in therequired logical state. For writing ‘1’ at the node-1 and ‘0’ at thenode-2, a biasing of magnitude VDD and 0 is applied at the BL andBLB, respectively [16,19]. Before the write operation (0/1 at node1/2), P2 and N1 operates in the linear region, whereas P1 and N2in ‘OFF’ state, as shown in Fig. 8. When the access transistors areturned ‘ON’ by applying appropriate biasing at the word line, thepotential of node-2 reduces below the threshold voltage of N1transistor that flips the state. At Vnode-2 = Vt,n, TFTs P2 and N4 oper-ates in the linear and saturation regions, respectively. The currentin the potential dividing network formed by P2 and N4 can beexpressed as

kP2

20� VDD � Vt;p� �2 ¼ kN4

22ðVDD � Vt;nÞVt;n � V2

t;n

n oð12Þ

On solving, the transconductance ratio can be expressed as

kP2

kN4<

2ðVDD � 1:5Vt;nÞVt;n

ðVDD þ Vt;pÞ2ð13Þ

ðW=LÞP2

ðW=LÞN4<

lnCox;n

lpCox;p� 2ðVDD � 1:5Vt;nÞVt;n


Similarly;ðW=LÞP1

ðW=LÞN3<

lnCox;n

lpCox;p� 2ðVDD � 1:5Vt;nÞVt;n


where lp (ln) and Cox,p (Cox,n) are the mobility and capacitance ofp-type (n-type) transistor, respectively.


Figs. 12–14 show the transient responses during write opera-tion of hybrid, organic complementary and all-p SRAM cell, respec-tively. As discussed earlier, the access transistor should be strongerthan the pull up transistor to attain a potential close to the BL andBLB terminals. The write-1 and write-0 access times are defined asthe time taken to attain 90% and 10% level of VDD, respectively afterapplying appropriate WL signals (VDD = 10 V and 0 V in case ofhybrid/organic and all-p SRAM, respectively). Write-0 time is lesserin comparison to write-1 for all three SRAM cells, since the poten-tial of node-2 that stores level-1 discharges first. This turns ‘OFF’the N1 transistor as the potential reaches below the threshold volt-age. Thereafter, the node-1 attains a potential close to VDD [17]. Thehybrid SRAM cell shows a reduction of 72% and 86% in the write-1and write-0 time, respectively as compared to the organic comple-mentary cell due to higher transconductance of the ZnO basedtransistor.

For the SRAM cell, two major sources of cell instability are theread and the write failure. The read failure represents the flippingof state during read access, whereas the write failure is flipping ofthe cell storage during write cycle. The cell stability during readaccess is quantified by the minimum voltage difference betweenthe complementary storage over the time. However, during writeoperation, it is characterized by the time required to flip the stateof the cell.

The major design issue in the SRAM cell is the conflict betweenthe read and write stability. As discussed previously, the cell ratioshould be large enough to enable the read access without alteringthe stored data. However, it degrades the writing ability due toreduction in the strength of access transistor that in turn raisesthe write access time. Similarly, the pull-up ratio should be smallenough to increase the write ability but it deteriorates the perfor-mance of cell during read access. Fig. 15(a) and (b) illustrates theplots of write-1 access time and potential difference of the comple-mentary storage (during read operation) with respect to the cellratio for hybrid and organic SRAM cells, respectively. A similar plotfor all-p SRAM cell is shown in Fig. 16.



(a) (b)

0 2 4 6 8 100

2

4

6

8

10

Data

WL

BL

Hybrid-SRAM

Pote

ntia

l (V)

t (ms)4 5 6 7

0

2

4

6

8

10

Pote

ntia

l (V)

t (ms)

Datab

Data

Hybrid-SRAM

Fig. 12. Transient response of hybrid-SRAM cell during write operation (a) ‘1’ and ‘0’ at the Data node; and (b) Data and Datab potential at bp = 0.2.

(a) (b)

0 2 4 6 8 100

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

BL

WL

Data

Organic Comp.-SRAM

4 5 6 70

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

Datab

DataOrganic Comp.-SRAM

Fig. 13. Transient responses of organic complementary SRAM cell during write operation (a) ‘1’ and ‘0’ at the Data node; and (b) Data and Datab potential at bp = 0.2.

(a) (b)

0 2 4 6 8 100

2

4

6

8

10p-SRAM

Pote

ntia

l (V)

t (ms)

Data

BL

WL

4 5 6 70

2

4

6

8

10 p-SRAM

Datab

Data

t (ms)

Pote

ntia

l (V)

Fig. 14. Transient responses of all-p SRAM during write operation (a) ‘1’ and ‘0’ at the Data node and (b) Data and Datab potential at bp = 0.2.


Table 5 summarizes the write access time (‘1’ and ‘0’), potentialdifference of complementary storage during read operation andthe optimized cell and pull-up ratios to perform both read andwrite operations for all three SRAM configurations. Compared tohybrid SRAM cell, the organic complementary cell shows inferiorwriting ability i.e approximately two times higher write-1 time.On the contrary, an improvement of 70% in its read stability is


observed in comparison to the hybrid cell that makes it morerobust against the external noise. Additionally, all-p SRAM cellshows a reduction of 32% in the write-1 time and an incrementof 37% in the read stability in comparison to the hybrid cell. Theread stability is highest for organic complementary cell due to low-est leakage current of the C60 based TFT in comparison to the ZnOand pentacene based TFTs [21,25]. The optimized cell ratio and pull



(a) (b)

0 5 10 15 2040

60

80

100

120

140

βc=2.4

βc

Writ

e A

cces

s Ti

me

(μs) Hybrid-SRAM

10

8

6

4

2

0

Write Access

Read Access

Potential Difference (1/0) (V)

0 5 10 15 200

200

400

600

800

Writ

e A

cces

s Ti

me

(μs)

10

8

6

4

2

0

βc

Write Access

Read Access


Organic Comp.-SRAM

βc=1.5

Fig. 15. Combine plots of write-1 access time and potential difference of complementary storage during read access for (a) hybrid and (b) organic complementary SRAM cellswith respect to the cell ratio.

0 20 40 60 800

30

60

90

120

150

180

Read Access

Write Access

p-SRAM

βc


Writ

e A

cces

s Ti

me

( μs)

βc=17.510

8

6

4

2

0

Fig. 16. Plot of write-1 access time and potential difference of complementarystorage during read access for all-p SRAM with respect to the cell ratio.

P2

N2

P1

N1

P5

LBBLB

Datab Data

WL

P6

VDD

2 1

Fig. 17. Schematic of organic complementary SRAM cell with p-type access TFTs.


up ratio for hybrid SRAM cell is 2.4 and 0.24, respectively. On theother hand, the optimized cell (pull up) ratio is obtained as 1.5(0.083) and 17.5 (1.2) for organic complementary and all-p organicSRAM cells, respectively. The write ability of three different SRAMcells are observed where the performance is Type-1 > Type-3 > Type-2 as depicted in Table 5.

4. Pentacene–C60 based SRAM cell with p-type access transistors

This section analyzes and discusses the effect of using p-typeaccess transistor instead of n-type access transistor in organic com-plimentary SRAM cell. The SRAM cell based on three combinationsof TFTs were discussed in the previous section. Based on this anal-yses, it was observed that the pentacene–ZnO based SRAM cellexhibited highest SNM and good writing ability, whereas theorganic complementary cell showed good reading ability with low-est reading time. On the other hand, the all-p SRAM cell demon-strated a reasonable response during read and write operationbut exhibited lowest SNM that increases the possibility of

Table 5Write access time (‘1’ and ‘0’), potential difference of complementary storage during read

SRAM design Class of SRAM cell Write-1 accesstime (ls)

Writtime

Organic all-p Type-1 67 10Organic comp. (pentacene–C60) Type-2 195 90Hybrid comp. (pentacene–ZnO) Type-3 99 33


disturbing the cell stability with even a small external noise volt-age. However, to achieve a fairly good performance in all threeaspects, the organic complementary SRAM cell is designed with ap-type access transistor in place of the n-type. This change is moti-vated by the fact that the major problem in pentacene–C60 basedcell arises due to weaker strength of the access transistors. Theschematic of organic complementary SRAM cell with p-type accessTFTs (P5 and P6) is shown in Fig. 17. It can be observed that otherTFTs are similar to the organic SRAM cell as discussed earlier.

The butterfly curve of the cross-coupled inverters during readaccess (bc = 20) is illustrated in Fig. 18(a). Compared to the organiccomplementary cell with n-type access transistors, this cell showsa reduction of 27% in the SNM during read access due to an incre-ment in the strength of access transistors but the magnitude ofstorage level ‘1’ and ‘0’ remains almost similar to the previous cell,as shown in Fig. 18(b). It is due to small leakage current of the C60

based pull-down TFT that helps in retaining the potential of nodein the standby mode.

During write operation, the write-1 access time of pentacene–C60 SRAM cell with n-type access TFTs, is 371 ls at bp = 0.2(Fig. 13(a)). However, a significant reduction of 79% in the writetime is observed for pentacene–C60 SRAM cell with p-type access

, optimized cell and pull up ratio for all three SRAM cells.

e-0 access(ls)

Potential differencein ‘1’ and ‘0’ during read (V)

Optimized bc Optimized bp

6.3 17.5 1.27.8 1.5 0.0834.6 2.4 0.24



(a) (b)

0 2 4 6 8 100

2

4

6

8

10

Read mode

Data, Datab (V)

Dat

ab, D

ata

(V)

Organic Comp.-SRAM (p-Access)

0 2 4 6 8 100

2

4

6

8

10Organic Comp.-SRAM (p-Access)

WL

Data

Datab

t (ms)

Pote

ntia

l (V)

Fig. 18. (a) Butterfly curve during read access (bc = 20); and (b) transient response during read operation for pentacene–C60 organic SRAM cell with p-type access TFTs.

(a) (b)

0 2 4 6 8 100

2

4

6

8

10

t (ms)

Pote

ntia

l (V)

WL

BL

DataOrganic Comp.-SRAM (n-Access)

4.5 4.8 5.1 5.4 5.70

2

4

6

8

10WL=10V

t (ms)

Pote

ntia

l (V)

Organic Comp.-SRAM (n-Access)

BL

Data

Datab

BLB

Fig. 19. Transient response of organic complementary SRAM cell with n-access TFTs during write operation (bp = 0.28) (a) ‘1’ and ‘0’ at the Data node; and (b) Data and Databpotential.

(a) (b)

0 2 4 6 8 100

2

4

6

8

10

BL

WL

Data

Organic Comp.-SRAM (p-Access)

t (ms)

Pote

ntia

l (V)

4.5 4.8 5.1 5.4 5.70

2

4

6

8

10

Pote

ntia

l (V)

t (ms)

Organic Comp.-SRAM (p-access)

WL=0

Datab

BLB

BL

Data

Fig. 20. Transient response of organic SRAM cell with p-access TFTs during write operation (bp = 0.28) (a) ‘1’ and ‘0’ at the Data node; and (b) Data and Datab potential.


TFTs with same bp. Moreover, the cell with p-type access TFTs dem-onstrates reasonably good behaviour at bp of 0.28. On the otherhand, the cell with n-type access TFTs shows a poor write responsedue to a reduction in the strength of access transistors with anincrease in the pull-up ratio. Fig. 19(a) and (b) shows the transientresponse and the transition of states at Data and Datab nodes,respectively for pentacene–C60 based organic SRAM cell consisting


of n-type access TFTs. It is observed that this cell shows inability tofollow the bit line signal properly and attains the voltage levels of9 V and 1 V against the 10 V and 0 V, respectively that too withquite large write access time of 802 and 730 ls, respectively. Onthe other hand, the cell with p-type access TFTs shows good writ-ing capability with an adequate follow up of the bit line potentialas shown in Fig. 20(a) and (b). Thus, a significant improvement



Table 6Comparison between the performance of organic SRAM cell with p- and n- type access OTFTs at bc = 10 and bp = 0.55.

Access OTFTs (organic complementary SRAM) Write access time (ls) Read stability

Write-1 Write-0 Potential difference of storage ‘1’ and ‘0’ (V) RSNM (V)

C60 based n-type Infinite Infinite 9.5 2.5Pentacene based p-type 131 115 9.2 1.7

Table 7Static and dynamic performance of organic all-p, hybrid and organic complementary SRAM cell.

SRAM performance parameters Class of SRAM cell designs

Organic all-p: driver/access/load: p-type-pentacenematerial (Type-1)

Organic comp. driver andaccess: n-type- C60, load:p-type pentacene material(Type-2)

Hybrid comp.driver and access:n-type- ZnO, load:p-type pentacenematerial (Type-3)

Organic comp.load and access:p-type-pentacenedriver: n-type-C60

materials (Type-4)

SNM (V) 1.46 3.1 3.4 2.7

Read operation Reading time (ls) 95 72 105 76Difference in magnitude ofstorage during read access (V)

7.6 9.6 7.9 9.2

Write operation Write-1 access time (ls) 67 195 99 131Write-0 access time (ls) 10 90 33 115

Ratio Optimized bc 17.5 1.5 2.4 10Optimized bp 1.2 0.083 0.24 0.55


of 85% and 88% in the write-1 (115 ls) and write-0 (86 ls) accesstimes, respectively is observed with p-type access TFTs.

The optimized cell and pull up ratios for organic SRAM cell withp-type access transistors are obtained as 10 and 0.55, respectively.The width of p-type access TFT is one sixth of that of the width ofn-type access TFT, whereas the dimensions of pull-up and pull-down TFTs are similar in both the cases. Table 6 summarizes theperformance of organic cell with both p- and n-type access transis-tors at bc = 10 and bp = 0.55. The organic complementary cell withp-type access TFTs demonstrates a reduction of 32% in the readSNM in comparison to the cell with n-type TFTs, however, it is stillhigher by more than two times in comparison to the all-p SRAMcell. Furthermore, in comparison to the cell with n-type accessTFTs, a slight reduction of 3% in the read stability is observed usingp-type access TFTs. Nevertheless, it is higher by two times incomparison to the hybrid cell. Besides this, a major benefit of usingp-type access TFTs is observed in terms of writing ability with rea-sonably lower write-1 and write-0 time, whereas, the cell withn-type access TFTs is unable to flip the state of the cell at the samecell ratio (10) and pull-up ratio (0.55). As a result, the performanceof pentacene–C60 based organic SRAM cell is reasonably good interms of all three aspects (read SNM, read stability and writingcapability) that too at the substantially lower width of p-typeaccess transistors in comparison to its counterpart. The summaryof static and dynamic performance parameters analyzed in termsof static noise margin (SNM), reading time and write access timefor all-p organic (Pentacene–Pentacene), organic complementary(Pentacene–C60) and hybrid complementary (Pentacene–ZnO) aresummarized in Table 7.

5. Conclusion

This research paper compares the performance of all-p, hybridand organic SRAM cell using pentacene, ZnO and C60 based TFTs.The performance of any class of SRAM can vary with the changeof material characteristics, structure and circuit design. The simu-lations are carried out on industry standard ATLAS tool withouttaking into account the gate bias-stress effects and parameter


variability. The results demonstrates that the organic complemen-tary SRAM cell shows good reading ability with high SNM, but low-est reading time and inferior writing capability. On the other hand,hybrid SRAM cell exhibits highest SNM and good writing ability,but an inferior read access performance.

All-p SRAM cell demonstrates a reasonable characteristic for theread and write operations but exhibits lowest SNM. Therefore, toachieve an overall good performance, an organic complementarySRAM cell design is modified by replacing C60 based access TFTswith pentacene based TFTs. This SRAM configuration demonstratedgood writing ability with reasonably lower write-1 (131 ls) andwrite-0 (115 ls) time that too at considerably reduced width ofthe p-type access TFTs. Besides this it showed good stability duringread operation with sufficiently large potential difference betweenthe complementary storage. Based on the comparison carried outamong all the SRAM configurations, it can be concluded that forbetter performance and circuit designing onto the flexible sub-strates, it is advisable to integrate fully organic SRAM cell. But then,it is essential to optimize the devices with higher mobility andlower threshold voltage. Realization of organic SRAM cell with p-type access TFTs stands out to be an overall better option thatachieves a good read stability and writing ability.

References

[1] Mizukami M, Hirohata N, Iseki T, Ohtawara K, Tada T, Yagyu S, et al. FlexibleAM OLED panel driven by bottom contact OTFTs. IEEE Electron Dev Lett2006;27:249–51.

[2] Cantatore E, Geuns TCT, Gelinck GH, Veenendaal EV, Gruijthuijsen AFA,Schrijnemakers L, et al. A 13.56 MHz RFID system based on organictransponders. IEEE J Solid-State Circ 2007;42:84–92.

[3] Brianda D, Opreab A, Courbata J, Barsanb N. Making environmental sensors onplastic foils – review article. Mater Today 2011;14:416–23.

[4] Takamiya M, Sekitani T, Kato Y, Kawaguchi H, Someya T, Sakurai T. An organicFET SRAM with back gate to increase static noise margin and its application tobraille sheet display. IEEE J Solid State Circ 2007;42:93–100.

[5] Tobjork D, Osterbacka R. Paper electronics. Adv Mater 2011;23:1935–61.[6] Tong X, Lassiter BE, Forrest SR. Inverted organic photovoltaic cells with high

open-circuit voltage. Org Electron 2010;11:705–9.[7] Guerin M, Daami A, Jacob S, Bergeret E, Benevent E, Pannier P, et al. High-gain

fully printed organic complementary circuits on flexible plastic foils. IEEETrans Electron Dev 2011;58:3587–93.


http://refhub.elsevier.com/S0026-2714(14)00373-4/h0005




















[8] Kim YH, Moon DG, Han JI. Organic TFT array on a paper substrate. IEEE ElectronDevice Lett 2004;25:702–4.

[9] Moore SK. Just one word—plastics. IEEE Spectr 2002;39:55–9.[10] Klauk H, Halik M, Zschieschang U, Eder F, Schmid G, Christine D. Pentacene

organic transistors and ring oscillators on glass and on flexible polymericsubstrates. Appl Phys Lett 2003;82:4175–7.

[11] Lee JB, Subramanian V. Organic transistors on fiber: a first step towardselectronic textiles. IEEE Tech Dig IEDM 2003:8.3.1–4.

[12] Myny K, Steudel S, Vicca P, Beenhakkers MJ, Van Aerle NAJM, Gelinck GH, et al.In: Turcu Cristina, editor. Organic RFID tags: radio frequency identificationfundamentals and applications, design methods andsolutions. Croatia: INTECH; 2010. p. 311–24.

[13] Yang Y, Ma L, Wu J. Organic thin-film memory. MRS Bull 2004;29:833–7.[14] Baeg KJ, Noh YY, Ghim J, Kang SJ, Lee H, Kim DY. Organic nonvolatile memory

based on pentacene field effect transistors using a polymeric gate electret. AdvMater 2006;18:3179–83.

[15] Prime D, Paul S. Overview of organic memory devices. Phil Trans R Soc A2009;367:4141–57.

[16] Guerin M, Bergeret E, Benevent E, Daami A, Pannier P, Coppard R. Organiccomplementary logic circuits and volatile memories integrated on plastic foils.IEEE Trans Electron Dev 2013;60:2045–51.

[17] Kang SM, Leblebici Y. CMOS digital integrated circuits: analysis and design. 3rded. India: Tata McGraw-Hill; 2003.

[18] Pal PK, Kaushik BK, Dasgupta S. High performance and robust SRAM cell basedon asymmetric dual-k spacer FinFETs. IEEE Trans Electron Dev2013;60:3371–7.

[19] Fukuda K, Sekitani T, Zschieschang U, Klauk H, Kuribara K, Yokota T, et al. A 4 Voperation, flexible braille display using organic transistors, carbon nanotubeactuators, and organic static random-access memory. Adv Funct Mater2011;21:4019–27.

[20] Dodabalapur A, Baumbach J, Baldwin K, Katz HE. Hybrid organic/inorganiccomplementary circuits. Appl Phys Lett 1996;68:2246–8.

[21] Oh MS, Hwang DK, Lee K, Choi WJ, Kim JH, Im S, et al. Pentacene and ZnOhybrid channels for complementary thin film transistor inverters operating at2 V. J Appl Phys 2007;102:076104-1–4-3.


[22] Kumar B, Kaushik BK, Negi YS. Static and dynamic analysis of organic andhybrid inverter circuits. J Comput Electron 2013;12:765–74.

[23] Wang J, Wei B, Zhang J. Fabricating an organic complementary inverter byintegrating two transistors on a single substrate. Semicond Sci Technol2008;23:055003-1–3-4.

[24] Kumar B, Kaushik BK, Negi YS. Organic thin film transistors: structures,models, materials, fabrication and applications – a review. Polym Rev2014;54:33–111.

[25] Na JH, Kitamura M, Arakawa Y. High performance n-channel thin filmtransistors with an amorphous phase C60 film on plastic substrate. Appl PhysLett 2007;91:193501-1–1-3.

[26] Atlas user’s manual. Device simulation software. Santa Clara: SilvacoInternational; 2012.

[27] Shim CH, Maruoka F, Hattori R. Structural analysis on organic thin filmtransistor with device simulation. IEEE Trans Electron Dev 2010;57:195–200.

[28] Blumstengel S, Glowatzki H, Sadofev S, Koch N, Kowarik S, Rabe JP,Henneberger F. Band-offset engineering in organic/inorganic semiconductorhybrid structures. Phys Chem Chem Phys 2010;12:11642–6.

[29] Gupta D, Katiyar M, Gupta D. An analysis of the difference in behavior of topand bottom contact organic thin film transistors using device simulation. OrgElectron 2009;10:775–84.

[30] Grossar E, Stucchi M, Maex K, Dehaene W. Read stability and write-abilityanalysis of SRAM cells for nanometer technologies. IEEE J Solid-State Circuits2006;41:2577–88.

[31] Vusser SD, Genoe J, Heremans P. Influence of transistor parameters on thenoise margin of organic digital circuits. IEEE Trans Electron Dev2006;53:601–10.

[32] Cui Q, Si M, Sporea RA, Guo X. Simple noise margin model for optimal design ofunipolar thin-film transistor logic circuits. IEEE Trans Electron Dev2013;60:1782–5.

[33] Myny K, Beenhakkers MJ, Van Aerle NAJM, Gelinck GH, Genoe J, Dehaene W,et al. Unipolar organic transistor circuits made robust by dual gate technology.IEEE J Solid-State Circuits 2011;46:1223–30.

[34] Taur Y, Ning TH. Fundamentals of modern VLSI devices. 2nd ed. Cambridge,UK: Cambridge University Press; 2009.












































































Documents

Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell