Design Amplifier

8/8/2019 Design Amplifier

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Amplifier DesignGuide

September 2006


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3/200 3

Contents1 Amplifier QuickStart Guide

Using DesignGuides................................................................................................. 1-1

Accessing the Documentation............................................................................ 1-3

Basic Procedures ..................................................................................................... 1-3

Selecting the Appropriate Simulation Type............................................................... 1-7

DC and Bias Point Simulations .......................................................................... 1-7

S-Parameter Simulations ................................................................................... 1-8

Nonlinear Simulations ........................................................................................ 1-8

Tools ......................................................................................................................... 1-15

2 Introduction

List of Available Data Displays ................................................................................. 2-2

References for Power Amplifier Examples............................................................... 2-10

3 DC and Bias Point Simulations

DC and Bias Point Simulations > BJT I-V Curves, Class A Power, Eff., Load, Gm vs. Bias

3-2

DC and Bias Point Simulations > BJT Output Power, Distortion vs. Load R............ 3-4

DC and Bias Point Simulations > BJT Fmax vs. Bias .............................................. 3-5

DC and Bias Point Simulations > BJT Ft vs. Bias .................................................... 3-6

DC and Bias Point Simulations > BJT Noise Fig., S-Params, Gain, Stability, and Circles vs.

Bias ........................................................................................................................ 3-7

DC and Bias Point Simulations > BJT Stability vs. Bias ........................................... 3-10

DC and Bias Point Simulations > FET I-V Curves, Class A Power, Eff., Load, Gm vs. Bias

3-11

DC and Bias Point Simulations > FET Output Power, Distortion vs. Load R ........... 3-13

DC and Bias Point Simulations > FET Fmax vs. Bias .............................................. 3-14

DC and Bias Point Simulations > FET Ft vs. Bias.................................................... 3-15

DC and Bias Point Simulations > FET Noise Fig., S-Params, Gain, Stability, and Circles vs.

Bias ........................................................................................................................ 3-16

DC and Bias Point Simulations > FET Stability vs. Bias........................................... 3-19

4 S-Parameter Simulations

S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circles, and Group Delay

4-2

S-Parameter Simulations > Feedback Network Optimization to Attain Stability ....... 4-5

S-Parameter Simulations > S-Params, Gain, NF, Stability, Group Delay vs. Swept

Parameters ............................................................................................................ 4-6

S-Parameter Simulations > S-Params., Stability, and Group Delay vs. Frequency and Input

Power..................................................................................................................... 4-9


4/2004

5 1-Tone Nonlinear Simulations

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion.................... 5-2

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion (w/PAE) ...... 5-3

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Power ... 5-5

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Power (w/PAE)5-7

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency5-91-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency (w/PAE

5-10

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency &

Power..................................................................................................................... 5-12

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency &

Power (w/PAE) ....................................................................................................... 5-14

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion at X dB Gain

Compression.......................................................................................................... 5-16


Compression vs. Freq............................................................................................ 5-18


Compression (w/PAE) vs. 1 Param........................................................................ 5-20


Compression (w/PAE) vs. 2 Params. ..................................................................... 5-22

1-Tone Nonlinear Simulations > Noise Figure, Spectrum, Gain, Harmonic Distortion 5-24

1-Tone Nonlinear Simulations > Large-Signal Load Impedance Mapping ............... 5-25

1-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power Contours.............. 5-26

1-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power Contours at X dB Gain

Compression.......................................................................................................... 5-281-Tone Nonlinear Simulations > Source-Pull - PAE, Output Power Contours .......... 5-30

1-Tone Nonlinear Simulations > Harmonic Impedance Opt. - PAE, Output Power, Gain5-32

1-Tone Nonlinear Simulations > Harmonic Gamma Opt. - PAE, Output Power, Gain 5-35

6 Statistical Design and Optimization for Amplifiers

Overview of Techniques ........................................................................................... 6-1

Yield Analysis ..................................................................................................... 6-2

Yield Optimization............................................................................................... 6-4

Yield Analysis Displays: YSH, MH, SRP ............................................................ 6-4

Statistical Design Methodology .......................................................................... 6-11Performing Yield Analysis................................................................................... 6-12

Using the Statistical Simulations............................................................................... 6-14

Using the DesignGuide Schematics................................................................... 6-16

Selecting the Appropriate Simulation Schematic ............................................... 6-16

Selecting the Appropriate Data Display.............................................................. 6-17

Choosing Parameter Statistics ........................................................................... 6-17

Yield Analysis Schematics.................................................................................. 6-19


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Linear Analysis Using S-Parameters as Measurements .......................................... 6-20

Linear Analysis Using Group Delay and Noise Figure as Measurements................ 6-23

Linear Analysis Using S-Parameters, Group Delay and Noise Figure as Measurements6-25

Nonlinear Analysis Using 1-Tone Harmonic Balance with Harmonic Distortion and Spectrum

as Measurements................................................................................................... 6-27

Nonlinear Analysis Using 2-Tone Harmonic Balance with Third and Fifth Order Intercepts asthe Measurements ................................................................................................. 6-29

Yield Optimization Schematics ................................................................................. 6-31

Linear Optimization Using S-Parameters as Measurements.................................... 6-32

Linear Optimization Using Group Delay and Noise Figure as Measurements ......... 6-33

Linear Optimization Using S-Parameters, Group Delay and Noise Figure as Measurements

6-34

Nonlinear Optimization Using 1-Tone Harmonic Balance with Harmonic Distortion and

Spectrum as Measurements .................................................................................. 6-35

Nonlinear Optimization Using 2-Tone Harmonic Balance with Third and Fifth Order

Intercepts as Measurements.................................................................................. 6-36

7 2-Tone Nonlinear Simulations

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points.................. 7-2

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points (w/PAE) .... 7-3

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Power . 7-5

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Power (w/PAE)

7-7

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Frequency7-9

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Frequency

(w/PAE) .................................................................................................................. 7-112-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. 1 Param. (w/PAE

7-13

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. 2 Param. (w/PAE

7-15

2-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power, IMD Contours ..... 7-17

2-Tone Nonlinear Simulations > Source-Pull - PAE, Output Power, IMD Contours.. 7-19

2-Tone Nonlinear Simulations > Harmonic Impedance Opt. - PAE, Output Power, Gain, IMD

7-21

2-Tone Nonlinear Simulations > Harmonic Gamma Opt. - PAE, Output Power, Gain, IMD7-24

8 Lumped 2-Element Z-Y Matching Networks

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L for Desired Z

8-2

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L for Desired Z

8-4


6/2006

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L for Desired Y

8-6

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L for Desired Y

8-8

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L to Match Series

R-C or R-L Device.................................................................................................. 8-10Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L to Match Series

R-C or R-L Device.................................................................................................. 8-12

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L to Match Shunt

R-C or R-L Device.................................................................................................. 8-14

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L to Match Shunt

R-C or R-L Device.................................................................................................. 8-16

9 Lumped Multi-Element Z-Y Matching Networks

Lumped Multi-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L, Series L/C

for Desired Z .......................................................................................................... 9-2Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C for

Desired Z ............................................................................................................... 9-3

Lumped Multi-Element Z-Y Matching Networks > Rload, Series L, Shunt C, Series L/C for

Desired Z ............................................................................................................... 9-5

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Shunt C for

Desired Y ............................................................................................................... 9-6

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C, Shunt

L/C for Desired Y ................................................................................................... 9-7

Lumped Multi-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L, Series L/C

to Match Series R-C or R-L Device........................................................................ 9-9Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L/C, Series C to

Match Series R-C or R-L Device............................................................................ 9-10

Lumped Multi-Element Z-Y Matching Networks > Rload, Series L, Shunt C, Series L/C to

Match Series R-C or R-L Device............................................................................ 9-12

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Shunt C Shunt

R-C or R-L Device.................................................................................................. 9-13

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C, Shunt

L/C to Match Shunt R-C or R-L Device.................................................................. 9-14


7/200Using DesignGuides 1-1

Chapter 1: Amplifier QuickStart GuideThe Am plifier QuickS tart Guide is int ended to help you get st ar ted u sing the

Amplifier DesignGuide effectively. For deta iled r eferen ce in form ation, r efer to

subsequent chapters of th is manu al.

The Amplifier DesignGuide includes man y useful simulation set ups a nd da ta

displays for am plifier design. Th e simu lation setu ps a re cat egorized by the t ype of

simu lation desired an d t he t ype of model ava ilable. Most of th e simula tion s etu ps a re

for a na lysis, but th ere ar e some for syn th esizing impeda nce mat chin g networks. The

DesignGuide is not a complet e solut ion for a mplifier designer s, but pr ovides some

useful t ools. Following ar e some featu re h ighlight s.

Simula tions of eight high-efficiency power amplifier examples

A detailed section on st at istical design For most data displays, th e equa tions a re visible on a n E quat ions screen with in

each dat a display file, to mak e it mu ch ea sier to see what is being calculat ed

an d h ow t o modify it if necessa ry.

Note This ma nu al is writt en describing and sh owing access th rough th e cascading

men u preferen ce. If you a re r un ning t he pr ogram th rough t he selection d ialog box

met hod, the a ppear an ce an d int erface will be slight ly differen t.

Using DesignGuides

All DesignGu ides can be accessed in th e Schem at ic window th rough eith er cascading

men us or dialog boxes. You can configur e your preferr ed method in t he Advan ced

Design System Ma in window. Select t he DesignGuide menu.

The comm an ds in t his men u a re a s follows:

DesignGuide Studio Documentation > Developer Studio Documentation is only available

on th is menu if you h ave inst alled the DesignGuide Developer St udio. It brings u p

th e DesignGu ide Developer Stu dio docum ent at ion. Anoth er way to access t he

Developer Stu dio docum ent at ion is by selectin gHelp > Topics and In dex >

DesignGuides >DesignGuide Developer S tudio (from a ny ADS pr ogram window).


8/2001-2 Using DesignGuides

Amplifier QuickStart Guide

DesignGuide Developer Studio > Start DesignGuide Studio is on ly ava ilable on th is

men u if you ha ve inst alled th e DesignGuide Developer St udio. It lau nches t he initial

Developer St udio dia log box.

Add DesignGuide brings u p a directory browser in wh ich you can add a DesignGuide

to your inst allation. This is primar ily int ended for u se with DesignGu ides th at ar e

cust om-built th rough th e Developer Stu dio.

List/Remove DesignGuide brings u p a list of your inst alled DesignGuides. Select an y

th at you would like to uninst all and choose th e Remove button.

Preferences brin gs up a dialog box th at a llows you t o:

Disable the DesignGuide menu comma nds (all except Pr eferences) in th e Main

window by un checking t his box. In t he Schem at ic an d Layout windows, th e

comp lete DesignGu ide menu a nd all of its comm an ds will be rem oved if this box

is unchecked.

Select your preferr ed inter face meth od (cascading menu s vs. dialog boxes).

Close an d rest ar t t he pr ogram for your preferen ce cha nges to take effect.


9/200Basic Procedures 1-3

Note On P C systems, Windows resour ce issues m ight limit th e use of cascading

men us. When m ultiple windows ar e open , your system could become dest abilized.

Thu s th e dialog box menu style might be best for t hese situ at ions.

Accessing the Documentation

To access t he docum ent a tion for th e DesignGuide, select eith er of th e following:

DesignGuide > Amplifier > Amplifier DesignGuide Documentation (from ADS

Schem atic window)

Help > Topics and Index > DesignGuides > Amplifier (from a ny ADS program

window)

Basic Procedures

The feat ur es an d cont ent of th e Amplifier DesignGuide ar e accessible from the

DesignGuide menu found in a ny Advan ced Design Syst em Schem at ic window, as

shown h ere


10/2001-4 Basic Procedures


The eight m enu select ions from DC and B ias Point S im ulations through Lumped

Mu lti-Elem ent Z-Y M atchin g N etworks ar e for selecting var ious simula tion s etu ps

an d am plifier exam ples. These are furt her cat egorized, as explained in su bsequent

sections of th is docum ent .

Ea ch of the eight men u selections from DC and B ias Point S im ulations toLumped

Mu lti-Elem ent Z-Y M atchin g N etworks ha ve addit iona l selections. The men u for

schem at ics for DC an d bias point simula tions appea rs as follows.

Selecting one of these m enu items, such a s BJ T I -V Curv es..., copies a s chem at ic int o

your cur ren t pr oject t ha t is set up for gener at ing a bipolar jun ction t ra nsist orscur ren t-versu s-voltage cur ves.


11/200Basic Procedures 1-5

The BJ T I-V curve schema tic appea rs a s follows.

Ea ch schema tic ha s a sam ple device th at ha s a lready been simulated. The simu lated

resu lts ar e displayed in a dat a display file tha t opens a ut oma tically after t he

schema tic is copied int o your pr oject. Modify th e BJ T by editing its model, or delete

th e device and replace it with a differen t one. The r ed boxes enclose pa ra met ers you

should set, su ch a s t he r an ge of base cur ren ts an d t he r an ge of collector voltages.

After ma king modificat ions, run a simu lation an d th e dat a display will upda te.

Note All schema tics have a sa mple device an d/or m odel, or a sa mple amplifier. The

dat a display that opens a fter you ma ke a menu selection ha s pre-simulated da ta from

th e device or a mplifier. You mu st rep lace the device or a mplifier on th e schema tic and

ru n a new simulation. The data display will be updat ed with the n ew data .


12/2001-6 Basic Procedures


Following are t he r esults of th e simu lation.

Most of th e inform at ion on th is dat a display an d on oth ers in t he DesignGu ide is in aform at th at engineers can easily understa nd.

Tips

We have minimized th e visibility of equations t ha t you sh ould not n eed to

modify. They are in cluded in a separ at e Equ at ions page.

Inform at ion about items on a data display th at you would wan t t o modify is

enclosed in red boxes.

Many of th e data displays have mu ltiple pages. Those tha t do ha ve a note

indicat ing what inform at ion is on oth er pa ges.

If, after selecting a DesignGu ide men u comm an d th at ha s insert ed a schem at ic an d

opened a data display, you re-na me t he schematic and t hen ru n a simulation, th e

most efficient way to display th e resu lts is t o open t he da ta display file th at

corr esponded to th e origina l schem at ic, an d upda te t he defau lt dat aset na me (which


13/200Selecting the Appropriate Simulation Type 1-7

is usu ally th e sam e as t he n ew na me of your schem at ic), to display your latest

simulation results.

Selecting the Appropriate Simulation Type

The Amplifier DesignGu ide is divided in to eight ca tegories for d ifferen t simu lat ion

types. Your design objective and th e type of models you ha ve available will det erm ine

which men u selections you select first .

DC and Bias Point Simulations

If you h ave a N onlinear FE T or BJ T model available, you can sta rt with DC and B ias

Point Simulations, as shown h ere.

These selections can be used t o deter mine da ta su ch a s t he following:

I-V cur ves of a device

Approxima te class A out put power and optimal bias point

Gm, fmax, and ft versus bias

Noise figure an d S-param eters versus bias

Optimal sour ce and load impedances for ma ximu m gain or minimum noise

figure, versus bias


14/2001-8 Selecting the Appropriate Simulation Type


Note While t his DesignGuide is ta rgeted t o power a mplifier designer s, man y of the

schema tics and da ta displays a re qu ite useful for sm all-signa l or low-noise amplifier

designer s a s well.

S-Parameter Simulations

If you ha ve only S-par am eter s (possibly with noise da ta ) available, or want to

simu late an am plifiers sm all-signal per form an ce, sta rt with S-Parameter

Simulations, as sh own h ere.

These can be used to determ ine dat a su ch a s th e following:

Noise figure and NF min, maximum available gain, and S-param eters

Optimal sour ce and load impedances to at ta in the minimum n oise figur e or

ma ximum gain

Feedback network element values to att ain stabili ty

Noise and available gain circles

Sta bility circles an d stability factors

Sta bility and S-para meters versus power (actually th ese require a nonlinear

model.)

Gr ou p Delay

Nonlinear Simulations

If you ha ve a n onlinea r device model available and want th e optima l sour ce an d load

impedan ces at th e fun dam ent al frequen cy (to maximize out put power an d/or

power-added efficiency), use Load-Pull or Source-Pull schemat ics in 1-Tone N onlin ear

Simulations, as sh own h ere.



If you ha ve a n onlinea r device model available and want th e optima l sour ce an d loadimpedan ces at th e fun dam ent al frequen cy (to maximize out put power an d/or

power-added efficiency, or min imize th ird- or fifth -order int erm odulat ion distort ion),

use Load-Pu ll or Sour ce-Pu ll schem atics in 2-Tone N onlinear S im ulations, as sh own

here.





impedances at the funda mental and ha rm onic frequ encies (to ma ximize out put

power a nd /or power-added efficiency), use the Ha rm onic Impeda nce Opt or Ha rm onic

Gamm a Opt schema tics in 1-Tone N onlinear S im ulations, as shown h ere.

The differen ce between t he t wo opt imizat ions is th at in one case, you specify th e

ra nges of allowed rea l an d imagina ry impedances, an d in t he oth er, you specify th e

allowed reflection coefficient s as circular regions on t he Smit h Ch ar t.


impedances at the funda mental and ha rm onic frequ encies (to ma ximize out put

power an d/or power-ad ded efficiency, an d minimize int erm odulat ion distort ion), use

th e Har monic Impeda nce Optimization or Har monic Gam ma Optimization

schem at ics in 2-Tone N onlinear S im ulation, as sh own h ere.

Again , the differen ce between t he t wo opt imizat ions is th a t in one case, you specify

th e ranges of allowed real an d imagina ry impedan ces, an d in th e oth er case you

specify th e allowed reflection coefficient s as circula r r egions on t he Smit h Ch ar t .



If you a lready ha ve an am plifier design, an d you wan t t o cha ra cter ize th e nonlinea r

performance over frequency, power, and other swept parameters, select the

appr opriat e schemat ic from 1-Tone N onlinear S im ulations, as sh own h ere.




The selections for 2-Tone N onlinear S im ulation follow.

Ther e ar e severa l high-efficiency power a mplifier exam ples. Simu lat ions of th ese can

be accessed u nder Power Am plifier Exam ples - By Class of Operation . Included ar e

Class AB th rough Class F, with Dohert y an d Class S exam ples as well.

Amplifier st at istical design is a lso available. These schema tics a nd dat a displays,

which describe steps you m ay ta ke t o minimize perform an ce variat ion a nd ma ximize

yield, can be a ccessed u nder Am plifier S tatistical Design.




If you wan t t o genera te a n ar bitr ar y impeda nce or a dmitt an ce, or m at ch t o a devices

equivalent input or out put circuit, u sing ideal, lum ped element s only, use one of th e

schematics under Lu m ped 2-Elem ent Z and Y Matching N etwork, as sh own h ere.

Lum ped, mu lti-elemen t m at ching net work s can also be used, as shown here.

Note The Pa ssive Circuit DesignGuide includes impedan ce m at ching capa bilities.


21/200Tools 1-15

Tools

These u tilities pr ovide a dded functiona lity t o this DesignGu ide. They can be seen in

the following figure. A br ief descript ion is pr ovided for each below. For more

inform at ion select th e help but ton in t he individua l ut ility.

Transistor Bias UtilityThe Tra nsist or Bias Ut ility provides SmartComponents an d au toma ted-assistan ts for

th e design an d simu lation of comm on r esistive an d active tr an sistor bias n etwork s.

The au tomated capa bilities can determine th e tra nsistor DC par am eters, design a n

appr opriat e network to achieve a given bias point, an d simula te and display the

achieved per form ance. All SmartComponentscan be m odified wh en selected . You

simply select a SmartComponentand wit h litt le effort r edesign or verify th eir

performance.


22/2001-16 Tools


Smith Chart Utility

This DesignGuide Ut ility provides full smit h cha rt capa bilities, synth esis of mat ching

net works, a llowing impedan ce m at ching a nd plott ing of const an t

Gain/Q/VSWR/Noise circles. This guide assum es you ha ve inst alled th e as sociated

DesignGuide with appropriate licensing codewords.

Impedance Matching Utility

The Impeda nce Mat ching Ut ility perform s th e synt hesis of lumped and distr ibuted

impedan ce m at ching n etwork s ba sed on pr ovided specificat ions. The Ut ility feat ur es

au tomat ic simula tion, sensitivity an alysis, an d display setu p to ena ble simple and

efficient component verification.


23/2002-1

Chapter 2: IntroductionThe Amplifier DesignGuide has m any simulation setups a nd data displays that are

useful for am plifier design. The simu lation set ups ar e cat egorized by the t ype of

simu lation desired an d t he t ype of model ava ilable. Most of th e simula tion s etu ps a re

for a na lysis, but th ere a re a lso some for synt hesizing impedan ce ma tching net work s

Note This ma nu al assum es th at you a re fam iliar with a ll of th e basic ADS program

opera tions. For a ddit ional inform at ion, refer to th e ADS S chem atic Capture and

Layoutmanual .

This m anu al is organized as follows:

Reference ta bles in th is cha pter, listing all simu lation setu ps, with links to theappr opriat e manu al pages for det ailed inform at ion

Chapt ers for ea ch t ype of simulation set up, as ident ified on t he DesignGuide

men u (which is accessed from ADS Schem atic wind ow). Deta iled inform at ion on

each simulat ion set up is included.

Note The Power Amplifier examples a re not docum ent ed in deta il, but for th e list of

dat a displays, refer t o Table 2-5. For a list of referen ces for th ese, refer to References

for Power Amplifier Exam ples on page 2-10.


24/2002-2 List of Available Data Displays

Introduction

List of Available Data Displays

The ta bles th at follow list a ll dat a displays th at ar e included with ea ch simu lation.

Table 2-1 shows all dat a d isplays included for DC a nd Bias Point Simula tions.

Table 2-2 shows all dat a displays used for S-Para met er Simu lations.

Table 2-1. DC and Bias Point Simu lations

Simulation Data Displays

BJT I-V Curves, Class A Power, Eff., Load,Gm vs. Bias

BJT_IV_Gm_PowerCalcs.dds, (ClassA_calcs;IV and Gm vs. Bias pages)

BJT Output Power, Distortion vs. Load R BJT_dynamic_LL.dds

BJT Fmax vs. Bias BJT_fmax_vs_bias.dds

BJT Ft vs. Bias BJT_ft_vs_bias.dds

BJT Noise Fig., S-Params, Gain, Stability, andCircles vs. Bias

BJT_SP_NF_Match_Circ.dds, (NF, SP, Gains, at allBias Pts.; Matching at 1 Bias Point; andCircles_Ga_Gp_NF_Stability pages)

BJT Stability vs. Bias BJT_Stab_vs_bias.dds

FET I-V Curves, Class A Power, Eff., Load,Gm vs. Bias

FET_IV_Gm_PowerCalcs.dds, (ClassA_calcs;IV and Gm vs. Bias pages)

FET Output Power, Distortion vs. Load R FET_dynamic_LL.dds

FET Fmax vs. Bias FET_fmax_vs_bias.dds

FET Ft vs. Bias FET_ft_vs_bias.ddsFET Noise Fig., S-Params, Gain, Stability, andCircles vs. Bias

FET_SP_NF_Match_Circ.dds, (NF, SP, Gains, at allBias Pts.; Matching at 1 Bias Point; andCircles_Ga_Gp_NF_Stability pages)

FET Stability vs. Bias FET_Stab_vs_bias

Table 2-2. S-Para meter Simulations


S-Params., Noise Fig., Gain, Stability, Circles,and Group Delay

SP_NF_GainMatchK.dds, (NF, Gain, Stab. Fact.,Matching; Gain, Noise, and Stability Circles; SParameters, Group Delay pages)

Feedback Network Optimization to AttainStability

Gain_and_Stab_opt.dds


25/200List of Available Data Displays 2-3

Table 2-3 shows all dat a displays used for 1-Tone Nonlinea r Simulat ions.

S-Params, Gain, NF, Stability, Group Delay vs.Swept Parameters

SP_NF_GainMatchKsweep.dds (Matching for Gainor NF; Stability Factors and Minimum NF, S Paramsand MAG at 1 Freq.; Group Delay pages)

S-Params., Stability, and Group Delay vs.Frequency and Input Power

Stab_vs_freq_pwr.dds (Stability and S-ParameterPlots; Group Delay pages)

Table 2-3. 1-Tone Nonlinea r Simula tions


Spectrum, Gain, Harmonic Distortion HB1Tone.dds

Spectrum, Gain, Harmonic Distortion (w/PAE) HB1TonePAE.dds

Spectrum, Gain, Harmonic Distortion vs.Power

HB1TonePswp.dds, (Spectrum, Gain Comp.,Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion vs.Power (w/PAE)

HB1TonePAE_Pswp.dds, (Spectrum, Gain Comp.,PAE, Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion vs.Frequency

HB1ToneFswp.dds

Spectrum, Gain, Harmonic Distortion vs.

Frequency (w/PAE)

HB1TonePAE_Fswp.dds

Spectrum, Gain, Harmonic Distortion vs.Frequency & Power

HB1ToneFPswp.dds, (Spectrum, Gain, Harmonics;AM-to-AM, AM-to-PM Plots pages)

Spectrum, Gain, Harmonic Distortion vs.Frequency & Power (w/PAE)

HB1TonePAE_FPswp.dds, (Spectrum, Gain, PAE,Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion atX dB Gain Compression

HB1ToneGComp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression vs. Freq.

HB1ToneGCompFswp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression (w/PAE) vs. 1 Param.

HB1ToneGComp1swp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression (w/PAE) vs. 2 Params.

HB1ToneGComp2swp.dds

Noise Figure, Spectrum, Gain, HarmonicDistortion

HB1ToneNoise.dds

Large-Signal Load Impedance Mapping LoadMapper.dds

Table 2-2. S-Para meter Simulat ions (cont inu ed)




Introduction

Table 2-4 shows all dat a displays used for 2-Tone Nonlinea r Simulat ions.

Load-Pull - PAE, Output Power Contours HB1Tone_LoadPull.dds

Load-Pull - PAE, Output Power Contours at X

dB Gain Compression

HB1Tone_LoadPull_GComp.dds

Source-Pull - PAE, Output Power Contours HB1Tone_SourcePull.dds

Harmonic Impedance Opt. - PAE, OutputPower, Gain

HarmZopt1tone.dds, (Power, Gain, Spectrum; OptSource and Load Zs; and Waveforms pages)

Harmonic Gamma Opt. - PAE, Output Power,Gain

HarmGammaOpt1tone.dds, (Power, Gain,Spectrum; Opt Source and Load Zs; and Waveformspages

Table 2-4. 2-Tone Nonlinea r Simula tions


Spectrum, Gain, TOI and 5thOI Points HB2Tone.dds

Spectrum, Gain, TOI and 5thOI Points(w/PAE)

HB2TonePAE.dds

Spectrum, Gain, TOI and 5thOI Points vs.Power

HB2TonePswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Power (w/PAE)

HB2TonePAE_Pswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Frequency

HB2ToneFswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Frequency (w/PAE)

HB2TonePAE_Fswp.dds

Spectrum, Gain, TOI and 5thOI Points vs. 1Param. (w/PAE)

HB2TonePAE_1swp.dds

Spectrum, Gain, TOI and 5thOI Points vs. 2Param. (w/PAE)

HB2TonePAE_2swp.dds

Load-Pull - PAE, Output Power, IMD Contours HB2Tone_LoadPull.dds

Source-Pull - PAE, Output Power, IMDContours

HB2Tone_SourcePull.dds

Harmonic Impedance Opt. - PAE, OutputPower, Gain, IMD

HarmZopt2tone.dds, (Power, Gain, Spectra; OptSource and Load Zs; and Waveforms pages)

Table 2-3. 1-Tone Nonlinea r Simula tions (cont inued)

http://-/?-http://-/?-



Table 2-5 shows all data displays u sed in t he Power Am plifier Exam ples - By Class of

Operation ca tegory. For r eferen ce inform ation on th ese exam ples, refer t o References

for Power Amplifier Exam ples on page 2-10.

Harmonic Gamma Opt. - PAE, Output Power,Gain, IMD

HarmGammaOpt2tone.dds, (Power, Gain, Spectrum;Opt Source and Load Zs; and Waveforms pages)

Table 2-5. Power Amplifier E xam ples - By Class of Opera tion


Class AB > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassAB.dds

Class AB > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassAB.dds

Class AB > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassAB.dds

Class AB > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_ClassAB.dds

Class B > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassB.dds

Class B > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power HB1TonePAE_Pswp_ClassB.dds

Class B > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassB.dds

Class B > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_ClassB.dds

Class C > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassC.dds

Class C > Spectrum, Gain, Harmonic

Distortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassC.dds

Class C > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassC.dds

Class D > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassD.dds

Class D > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassD.dds

Table 2-4. 2-Tone Nonlinea r Simula tions (cont inued)

http://-/?-



Introduction

Table 2-6 shows all da ta displays u sed in t he Amplifier St at istical Design cat egory.

Class D > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassD.dds

Class E > Load-Pull - PAE, Output PowerContours HB1Tone_LoadPull_ClassE.dds

Class E > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassE.dds

Class E > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassE.dds

Class F > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassF.dds

Class F > Spectrum, Gain, Harmonic

Distortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassF.dds

Class F > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassF.dds

Doherty> Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_Doherty.dds

Doherty > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_Doherty.dds

Doherty > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_Doherty.dds

Doherty > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_Doherty.dds

Class S > Spectrum, Output Power, Distortion,PAE

ClassS_PA_1.dds

Table 2-5. Power Amplifier Examples - By Class of Opera tion (cont inued)




Table 2-6. Amplifier St at istical Design


S-Parameter Simulation Yield Sensitivity Histogram - One(YSH_SParams_One.dds)

Yield Sensitivity Histograms - Four(YSH_SParams_Four.dds)

Measurement Histogram - One(MH_SParams_One.dds)

Measurement Histograms - Four(MH_SParams_Four.dds)

Statistical Response Plots (SRP_SParams.dds)

Group Delay, Noise Figure Simulation Yield Sensitivity Histogram - One

(YSH_GrpDly_NF_One.dds)Yield Sensitivity Histograms - Four(YSH_GrpDly_NF_Four.dds)

Measurement Histogram - One(MH_GrpDly_NF_One.dds)

Measurement Histograms - Four(MH_GrpDly_NF_Four.dds)

Statistical Response Plots (SRP_GrpDly_NF.dds)

S-Parameters, Group Delay, Noise Figure

Simulation

Yield Sensitivity Histogram - One

(YSH_Sparams_GrpDly_One.dds)

Yield Sensitivity Histograms - Four(YSH_Sparams_GrpDly_Two.dds)

Gain, Spectrum, Harmonic Dist. Simulation Yield Sensitivity Histogram(YSH_1Tone_HD_Spect.dds)

Measurement Histogram(MH_1Tone_HD_Spect.dds)

Statistical Response Plots(SRP_1Tone_HD_Spect.dds)

Third- and Fifth-Order Intercept Simulation Yield Sensitivity Histogram(YSH_2Tone_TOI_5OI.dds)

Measurement Histogram (MH_2Tone_TOI_5OI.dds)

Statistical Response Plot(SRP_2Tone_TOI_5OI.dds)
http://-/?-http://-/?-http://-/?-http://-/?-



Introduction

Table 2-7 shows all da ta displays u sed for Lu mped 2-Element Z-Y Mat chin g

Networks.

Table 2-8 shows all dat a displays used for Lu mped Mult i-E lemen t Z-Y Mat chin g

Networks.

Table 2-7. Lumped 2-Elemen t Z-Y Mat ching Net work s

Simulation Data DisplaysRload, Shunt C/L, Series C/L for Desired Z Zdesired1.dds

Rload, Series C/L, Shunt C/L for Desired Z Zdesired2.dds

Rload, Shunt C/L, Series C/L for Desired Y Ydesired1.dds

Rload, Series C/L, Shunt C/L for Desired Y Ydesired2.dds

Rload, Shunt C/L, Series C/L to Match Series R-Cor R-L Device

Zmatch1.dds

Rload, Series C/L, Shunt C/L to Match Series R-C

or R-L Device

Zmatch2.dds

Rload, Shunt C/L, Series C/L to Match Shunt R-Cor R-L Device

Ymatch1.dds

Rload, Series C/L, Shunt C/L to Match Shunt R-Cor R-L Device

Ymatch2.dds

Table 2-8. Lum ped Multi-Elemen t Z-Y Mat chin g Network s

Simulation Data Display

Rload, Series C/L, Shunt C/L, Series L/C forDesired Z

Zdesired1M.dds

Rload, Shunt C, Series L, Series C for Desired Z Zdesired2M.dds

Rload, Series L, Shunt C, Series L/C for DesiredZ

Zdesired3M.dds

Rload, Shunt C, Series L, Shunt C for Desired Y Ydesired1M.dds

Rload, Shunt C, Series L, Series C, Shunt L/C forDesired Y

Ydesired2M.dds

Rload, Series C/L, Shunt C/L, Series L/C toMatch Series R-C or R-L Device

Zmatch1M.dds

Rload, Shunt C, Series L/C, Series C to MatchSeries R-C or R-L Device

Zmatch2M.dds



Rload, Series L, Shunt C, Series L/C to MatchSeries R-C or R-L Device

Zmatch3M.dds

Rload, Shunt C, Series L, Shunt C Shunt R-C orR-L Device

Ymatch1M.dds

Rload, Shunt C, Series L, Series C, Shunt L/C toMatch Shunt R-C or R-L Device

Ymatch2M.dds

Table 2-8. Lum ped Multi-Elemen t Z-Y Mat ching Networks (cont inued)

Simulation Data Display


32/2002-10 References for Power Amplifier Examples

Introduction

References for Power Amplifier Examples

Class AB

[1]Cripps S.C., RF Power Amplifiers for Wireless Communications, 1999 Artech

House, ISBN # 0-89006-989-1.(pa ges 120-125)

[2] Ken ington P.B., High-Linea rit y RF Amplfier Design, 2000 Art ech House,

ISBN # 1-58053-143-1. (pa ges 101-102)

Class B


House, ISBN # 0-89006-989-1. (pages 93-112)


ISBN # 1-58053-143-1. (pa ges 97-101)

Class C


House, ISBN # 0-89006-989-1.(page 124)

[2] Ken ington P.B., High-Linea rit y RF Amplfier Des ign, 2000 Artech House,

ISBN # 1-58053-143-1. (pa ges 102-112)

Class D

[1]Cripps S.C., RF Power Amplifiers for Wireless Communications, 1999 ArtechHouse, ISBN # 0-89006-989-1.(pa ges 130-132)


ISBN # 1-58053-143-1. (pa ges 113-121)

Class E


House, ISBN # 0-89006-989-1.(pa ges 170-177)

[2] Ken ington P.B., High-Linea rit y RF Amplfier Design, 2000 Art ech House,ISBN # 1-58053-143-1. (pa ges 121-122)

Class F


House, ISBN # 0-89006-989-1.(pa ges 132-140)


33/200References for Power Amplifier Examples 2-11


ISBN # 1-58053-143-1. (pa ges 122-123)

Class S


House, ISBN # 0-89006-989-1.(pa ges 246-248)


ISBN # 1-58053-143-1. (pa ges 124-126)

[3] 3. Kahn L.R., Single Sideband Tra nsm ission by En velope E limina tion an d

Rest ora tion, Pr oc. IRE , Vol. 40, Ju ly 1952, pp. 803-806.

Doherty

[1] 1. Cripps S.C., RF Power Amplifiers for Wire less Comm unica t ions, 1999

Artech House, ISBN # 0-89006-989-1.(pa ges 225-239)

[2] 2. Kenin gton P.B., High-Linea rit y RF Amplfier Design, 2000 Artech House,

ISBN # 1-58053-143-1. (pa ges 493-499)

General

[1]1. Sokal N.O. RF Power Amplifiers, Classes A through S, Proc. Wireless and

Microwave Technology 1997 Chanatilly, VA.


34/2002-12 References for Power Amplifier Examples

Introduction


35/2003-1

Chapter 3: DC and Bias Point SimulationsThe tem plates in th e DC and Bias Point Simu lations m enu a re concerned with

choosing a bias p oint , an d its effect s on outpu t p ower, gain, noise figure,

tr an scondu cta nce, etc.


36/2003-2


DC and Bias Point Simulations > BJT I-V Curves, Class A Power, Eff.,Load, Gm vs. Bias

Description

This simu lation setu p genera tes t he I-V cur ves of a BJ T. Var ious dat a depen dent on

th e I-V cur ves, su ch a s t ra nsconducta nce, class A out pu t power, and efficiency ar ealso shown. Both th e base curr ent an d t he collector-to-emitt er voltage are swept.

Needed to Use Schematic

Nonlinea r BJ T model

Main Schematic Settings

Sweep ra nges for ba se cur ren t a nd collector volta ge

Data Display OutputsBJ T_IV_Gm_PowerCalcs.dds, Clas sA_calcs page:

Device I-V curves

Load line set by placing a ma rker on th e I-V cur ves at th e knee, an d by a

user-specifiable maximum VCE.

Maximu m a llowed DC power dissipat ion curve, with m aximu m dissipat ion set

by user.

Given th e load line specified by the kn ee of th e I-V cur ves a nd t he m aximu mVCE:

Optimu m collector voltage an d collector cur ren t, for m aximum power

delivered t o the load wh ile in Cla ss A operat ion

Corr esponding load resistan ce

Corresponding ma ximu m out put power

Corr esponding DC power consu mpt ion

Corr esponding DC-to-RF efficiency

Given a different bias point , specified by a different ma rker:

Load line between t hat mar ker an d the m arker a t t he knee of the I-V curve

Resista nce of th is load line

DC power consu mption a t t his bias point


37/2003-3

Out put power, assum ing the device rema ins in Class A opera tion (AC voltage

does not exceed user-specified VCE, an d does not ent er t he k nee r egion)

DC-to-RF efficiency at th is bias point

Device beta versu s base cur rent at th e VCE specified by one of th e mar kers

Note The es tim at e of DC-to-RF efficiency an d outpu t power a re only

approxima te, since no high-frequ ency effects a re m odeled in t his simula tion.

BJT_IV_Gm_PowerCalcs.dds, IV and Gm vs. Bias page:

Device I-V cur ves

DC tran scondu cta nce (Gm) versu s VCE

DC tran scondu cta nce (Gm) versu s IBB and VCE

DC tra nscondu cta nce (Gm) versus collector cur ren t

Collector curr ent versus base current at one VCE

Table of tra nscondu cta nce values

Schematic Name

BJ T_IV_Gm_PowerCa lcs

Data display name

BJ T_IV_Gm_PowerCa lcs.dds


38/2003-4


DC and Bias Point Simulations > BJT Output Power, Distortion vs. LoadR

Description

This simulat ion set up gener at es th e I-V cur ves of a BJ T an d simulat es th e power

delivered t o a load resistor a s a fun ction of the r esistan ce value, at one bias point.




Sweep ra nges for base cur ren t, collector voltage and load resista nce; bias point an d

frequen cy for out put power versu s load resista nce simulat ion

Data Display Outputs Device I-V curves

Load lines for each of th e load resistan ces

Power delivered to the load a s a fun ction of load r esista nce

Output power a nd ha rmonic distortion a t each load resistan ce

Schematic Name

BJT_dynamic_LL

Data Display Name

BJT_dynamic_LL.dds

Note

The load power simu lations will show less th an optima l results a s th e simulat ion

frequ ency is increa sed, becau se on ly a res istive load is pr esen ted t o th e device. Also,

no impeda nce ma tching is included at th e inpu t.


39/2003-5

DC and Bias Point Simulations > BJT Fmax vs. Bias

Description

This simu lates th e ma ximu m frequen cy of oscillation (th e frequen cy at which t he

ma ximu m a vailable gain dr ops t o 0 dB), versu s bias curr ent , for a par ticula r value o

VCE. It shou ld help you det erm ine how high in frequ ency a device can be used.




VCE, base cur ren t sweep limits, an d frequ ency ra nge for S-para met er simu lation

Data Display Outputs

The maximum available gain versus base curr ent an d frequency

dB(S21) versus base curr ent an d frequency

The maximum frequency of oscillation, which is dependent on a ma rker th at

you move to select th e valu e of collector cur ren t

Schematic Name

BJT_fmax_vs_bias

Data Display Name

BJT_fmax_vs_bias.dds


40/2003-6


DC and Bias Point Simulations > BJT Ft vs. Bias

Description

This simu lates a devices ft, th e frequen cy at which th e sh ort -circuit cur ren t gain

drops to un ity, versu s bias cur ren t, for a par ticular value of VCE. It should h elp you

deter mine h ow high in frequen cy a device can be used.






Short circuit curr ent gain versus base curr ent a nd frequency

Frequency at which t he sh ort -circuit curr ent gain dr ops to 0 dB, at t he collector

bias curr ent specified by a movable ma rk er

Schematic Name

BJT_ft

Data Display Name

BJT_ft.dds


41/2003-7

DC and Bias Point Simulations > BJT Noise Fig., S-Params, Gain,Stability, and Circles vs. Bias

Description

This simulat es th e S-par am eters a nd n oise para met ers of a device, versus bias

volta ge and curr ent , at a single frequen cy. You specify th e collector volta ge sweepra nge and the ba se cur rent sweep ra nge, an d th e single frequency for S-para meter

an d noise ana lysis. The optimal sour ce an d load impedan ces for m inimum noise

figur e an d for m aximu m gain a re compu ted, as well as th e available gain circles,

power gain circles, noise circles, an d source an d load s ta bility circles.



Main Schematic SettingsSweep ra nges for base curr ent an d collector voltage a nd frequ ency for S-par am eter

analysis.


BJ T_SP_NF _Mat ch_Circ.dds, NF, SP, Gains a t all Bias Pt s. page:

Minimum n oise figure versus VCE an d base current

dB(S21), dB(S12), dB(S11), and dB(S22) versu s collector volta ge and ba se

current

Maximu m a vailable gain versus base cur rent an d collector voltage

Associated power gain (with input m at ched for m inimu m n oise figure an d

out put conjugat ely ma tched) versus collector voltage a nd base cur ren t

BJ T_SP_NF _Mat ch_Circ.dds, Mat chin g at 1 Bias Point page:

Minimum noise figur e an d dB(S21) versus collector cur ren t a t a collector

volta ge selected by moving a m ark er on th e I-V cur ves.

DC I-V curves

Smith cha rt with tr aces of th e optima l sour ce reflection coefficients for

min imu m noise figure, an d the following reflect ion coefficient s (gam ma s) at t he

selected bias point:

Gamma source for minimum n oise figure


42/2003-8


Gamma load for ma ximum power gain when input is terminated for

minimu m n oise figur e

Gamm a sour ce for simultan eous conjugate mat ch (with out r egar d to noise)

Gamm a load for simultan eous conjugat e mat ch (with out r egard t o noise)

Listing column s of dat a corr espondin g to th e bias point selected by moving a

ma rk er on t he I-V cur ves:

VCE

IC

Approximat e DC power consumption

S -pa r amet er s, dB

Maximum available power gain, dB

Minimum noise figure, dB

Sopt for minimum n oise figur e in polar coordinat es and in magnitude an d

phase

Zopt for minimum noise figure

Associated power gain in dB, if th e inpu t is ma tched for minimum noise

figur e an d t hen th e out put is mat ched for ma ximu m power gain

Corr esponding load impedance for associated power gain

Sour ce and load impedances for simulta neous conjugat e mat ching (with out

regar d t o noise)

Input an d output impedances when source and load are terminated in 50

ohms

Stability factor, K

Frequency of the S-param eter simulations

BJT_SP_NF_Match_Circ.dds, Circles_Ga_Gp_NF_Stability page:

All at one bia s point selected by moving a ma rk er on th e devices I-V curves:

Sta bility factor, K, and sour ce stability circles. Note th at th e Smith Cha rt

size is fixed, so if th e sta bility circles ar e far out side th e Smith Cha rt , th ey

will not be displayed. If you change the Smith Ch ar t sca ling to Aut o Scale,

th e circles will be visible.


43/2003-9

Available gain an d n oise circles on one Smith Char t, an d power gain circles

on a different Smith Cha rt .

Minimum noise figur e, sour ce impeda nce (Zopt) required to achieve this

noise figur e, an d t he optimal load imp edan ce for power tr an sfer wh en t he

source impeda nce is Zopt

Maximu m available gain, and th e sour ce and load impedances required for

simu lta neous conjuga te m at chin g (only valid if K>1)

Noise figure with th e simu ltaneous conjugate mat ch condition

Noise figure, tr an sducer power gain, and optima l load impedance if th e

sour ce impedan ce is chosen a rbitr ar ily by moving a m ar ker (Gam ma S) on a

Smith Cha rt . This is u seful if you m ust ma ke some compr omise between

noise a nd gain, or if you need t o avoid an un sta ble region.

Tran sducer power gain, and optimal sour ce impedance an d corresponding

noise figure, if th e load impedan ce is chosen a rbitr ar ily by moving a ma rk er

(Gam ma L) on a Smith Cha rt . This is u seful if you need t o avoid an un sta ble

region.

Schematic Name

BJT_SP_NF_Match_Circ

Data Display Name

BJT_SP_NF_Match_Circ.dds


44/2003-10


DC and Bias Point Simulations > BJT Stability vs. Bias

Description

This simu lates th e S-par am eters of a t ra nsistor, with th e base cur rent swept a nd t he

emitt er bias voltage const an t, to determ ine th e sta bility factors as a fun ction of base

cur ren t. It should help you d eterm ine th e dependence of th e sta bility factor on t hebias point .






Stability measure, B1, versus base curr ent a nd frequency

Sta bility factor, K, versus base cur rent an d frequency

Geometr ically-derived load sta bility factor, mu, versus base cur rent an d

frequency

Geomet rically-derived sour ce sta bility factor, mu _prime, versu s base cur ren t

an d frequ ency

Schematic NameBJT_Stab_vs_bias

Data Display Name

BJT_Stab_vs_bias.dds


45/2003-11

DC and Bias Point Simulations > FET I-V Curves, Class A Power, Eff.,Load, Gm vs. Bias

Description

This simu lation setu p genera tes t he I-V cur ves of a F ET. Var ious dat a depen dent on

th e I-V cur ves, su ch a s t ra nsconducta nce, class A out pu t power, and efficiency ar ealso sh own. Both th e gat e an d dra in voltages ar e swept.


Nonlinea r FE T model


Sweep ran ges for gat e an d dra in voltages

Data Display OutputsFET_IV_Gm_PowerCalcs.dds, Clas sA_calcs page:

Device I-V curves

Load line set by placing a ma rker on th e I-V cur ves at th e knee, an d by a

user-specifiable ma ximu m VDS

Maximu m a llowed DC power dissipat ion curve, with m aximu m dissipat ion set

by user.

Given th e load line specified by the kn ee of th e I-V cur ves a nd t he m aximu mVDS:

Optimum drain voltage and dra in curr ent, for m aximum power delivered to

th e load while in Class A operat ion

Corresponding load resistance

Corresponding maximum output power

Corresponding DC power consumption

Corresponding DC-to-RF efficiency

Given a different bias point , specified by a different ma rker:

Load line between th at m arker a nd the mark er at th e knee of the I-V curve

Resistan ce of this load line

DC power consumption at this bias point


46/2003-12


Outpu t power, assum ing the device rema ins in Class A operat ion (AC voltage

does not exceed user-specified VDS, an d does not en ter th e kn ee region)

DC-to-RF efficiency at th is bias point

Note The es tim at es of DC-to-RF efficiency an d out pu t power a re onlyapproxima te, since no high-frequ ency effects a re m odeled in t his simula tion.

FET_IV_Gm_PowerCalcs.dds, IV, Gm vs. Bias pa ge:

Device I-V curves

DC transconductan ce (Gm) versus VDS

DC tr an scondu cta nce (Gm) versu s VGS an d VDS

DC tra nsconductan ce (Gm) versus drain curr ent

Drain curr ent versus gate voltage at one VDS

Table of tran sconductan ce values

Schematic Name

FET_IV_Gm_PowerCalcs

Data Display Name

FET_IV_Gm_PowerCalcs.dds


47/2003-13

DC and Bias Point Simulations > FET Output Power, Distortion vs. LoadR

Description

This simulat ion set up gener at es th e I-V cur ves of a F ET a nd simu lates t he power

delivered t o a load resistor a s a fun ction of the r esistan ce value, at one bias point.




Sweep ranges for ga te voltage, drain voltage and load resista nce; bias point an d

frequen cy for out put power versu s load resista nce simulat ion

Data Display Outputs Device I-V curves

Load lines for each of th e load resistan ces

Power delivered to the load a s a fun ction of load r esista nce

Output power a nd ha rmonic distortion a t each load resistan ce

Schematic Name

FET_dynamic_LL

Data Display Name

FET_dynamic_LL.dds

Note

The load power simulat ions a re going to show less th an optima l results a s th e

simu lation frequ ency is increa sed, becau se only a r esistive load is presen ted t o the

device. Also, no impeda nce matching is included at th e inpu t .


48/2003-14


DC and Bias Point Simulations > FET Fmax vs. Bias

Description

This simu lates th e ma ximu m frequen cy of oscillation (th e frequen cy at which t he

ma ximu m a vailable gain dr ops t o 0 dB), versu s bias voltage, for a par ticular value of

VDS. It should help you det erm ine h ow high in frequen cy a device can be used.




VDS, gate voltage sweep limits, an d frequency ran ge for S-par am eter simula tion


The maximu m available gain versus gate voltage an d frequency

dB(S21) versu s gat e voltage an d frequency

The maximum frequency of oscillation, which is dependent on a ma rker th at

you move to select th e value of dra in curr ent

Schematic Name

FET_fmax_vs_bias

Data Display Name

FET_fmax_vs_bias.dds


49/2003-15

DC and Bias Point Simulations > FET Ft vs. Bias

Description

This simu lates a devices ft, th e frequen cy at which th e sh ort -circuit cur ren t gain

drops t o un ity, versus gat e volta ge, for a pa rt icu lar value of VDS. It should h elp you

deter mine h ow high in frequen cy a device can be used.


Nonlinea r FE T model.




Short circuit cur rent gain versu s gat e voltage an d frequency

Frequency at wh ich th e short -circuit cur rent gain drops to 0 dB, at t he drain

bias curr ent specified by a movable ma rk er

Schematic Name

FET_ft_vs_bias

Data Display Name

FET_ft_vs_bias.dds


50/2003-16


DC and Bias Point Simulations > FET Noise Fig., S-Params, Gain,Stability, and Circles vs. Bias

Description

This simulat es th e S-par am eters a nd n oise para met ers of a device, versus bias

volta ges, at a single frequ ency. You specify th e gat e an d dr ain volta ge sweep ra nges,an d th e single frequen cy for S-para met er a nd n oise ana lysis. The optimal source and

load imp edan ces for m inimu m n oise figur e an d for m aximu m gain ar e compu ted, as

well as t he a vailable gain circles, power gain circles, noise circles, and source and load

st ability circles.



Main Schematic SettingsSweep ran ges for gat e an d dra in voltages an d frequen cy for S-para meter an alysis


FE T_SP_NF _Match_Circ.dds, NF, SP, Gain s a t all Bias Pt s. page:

Minimum n oise figure versus VGS and VDS

dB(S21), dB(S12), dB(S11), an d dB(S22) versus VGS an d VDS

Maximum available gain versus VGS and VDS

Associated power gain (with input m at ched for m inimu m n oise figure an d

out put conjugat ely ma tched) versu s VGS an d VDS

FE T_SP_NF _Mat ch_Circ.dds, Mat chin g at 1 Bias Point page:

Minimum noise figur e and dB(S21) versu s drain cur rent a t a dra in voltage

selected by moving a m ar ker on t he I-V cur ves.

DC I-V curves

Smith cha rt with tr aces of th e optima l sour ce reflection coefficients formin imu m noise figure, an d the following reflect ion coefficient s (gam ma s) at t he

selected bias point:





51/2003-17



Listing column s of dat a corr espondin g to th e bias point selected by moving a

ma rk er on t he I-V cur ve:

VDS

IDS

Approximat e DC power consumption





phase






regar d t o noise)

Input an d output impedances when source and load are terminated in 50

ohms

Stability factor, K

Frequency of the S-param eter simulations

FET_SP_NF_Match_Circ.dds, Circles_Ga_Gp_NF_Stability page:

All at one bia s point selected by moving a ma rk er on th e devices I-V curves: Sta bility factor, K, and sour ce stability circles. Note th at th e Smith Cha rt

size is fixed, so if th e sta bility circles ar e far out side th e Smith Cha rt , th ey

will not be displayed. If you change the Smith Ch ar t sca ling to Aut o Scale,

th e circles will be visible.

Available gain an d n oise circles on one Smith Char t, an d power gain circles

on a different Smith Cha rt .


52/2003-18


Minimum noise figur e, sour ce impeda nce (Zopt) required to achieve this

noise figur e, an d t he optimal load imp edan ce for power tr an sfer wh en t he

source impeda nce is Zopt


simu lta neous conjuga te m at chin g (only valid if K>1)

Noise figure with th e simu ltaneous conjugate mat ch condition

Noise figure, tr an sducer power gain, and optima l load impedance if th e

sour ce impedan ce is chosen a rbitr ar ily by moving a m ar ker (Gam ma S) on a

Smith Cha rt . This is u seful if you m ust ma ke some compr omise between

noise a nd gain, or if you need t o avoid an un sta ble region.

Tran sducer power gain, and optimal sour ce impedance an d corresponding

noise figure, if th e load impedan ce is chosen a rbitr ar ily by moving a ma rk er

(Gam ma L) on a Smith Cha rt . This is u seful if you need t o avoid an un sta bleregion.

Schematic Name

FET_SP_NF_Match_Circ

Data Display Name

FET_SP_NF_Match_Circ.dds


53/2003-19

DC and Bias Point Simulations > FET Stability vs. Bias

Description

This simulates t he S-par amet ers of a tr an sistor, with th e gate voltage swept a nd t he

dra in bias voltage const an t, to determ ine th e sta bility factors as a function of gate

voltage. It sh ould h elp you deter mine t he depen dence of the st ability factor on th ebias point .






Sta bility measur e, B1, versu s gat e voltage an d frequency

Sta bility factor, K, versus gate voltage and frequency

Geomet rically-derived load st ability factor, mu, versu s gate voltage an d

frequency

Geomet rically-derived sour ce sta bility factor, mu_prime, versu s gat e voltage

an d frequ ency

Schematic NameFET_Stab_vs_bias

Data Display Name

FET_Stab_vs_bias.dds


54/2003-20



55/2004-1

Chapter 4: S-Parameter SimulationsThe templat es in th e S-Para meter Simu lations a re for simu lating the sma ll-signa l

cha ra cter istics, su ch as noise figur e, available ga in, st ability, group delay, etc., of a

device or a n a mplifier. Except for t he la st one, these simu lat ions do not r equir e a

nonlinea r m odel, but an am plifier with nonlinear models can be used.


56/2004-2


S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circlesand Group Delay

Description

This simu lates th e S-par am eter s, noise figur e, sta bility, an d group delay of an y

two-port n etwork, versu s frequ ency. You m ay use it with an S-param eter da ta file, orwith a nonlinea r a mplifier model.


Any linea r or nonlinea r m odel, including measu red S-par am eter s


Fr equency sweep ran ge

Data Display OutputsSP_NF _GainMa tchK.dds, NF, Gain , Sta b. Fact., Mat ch ing page:

Minimum noise figur e and n oise figur e with 50 ohm t ermina tions versus

frequency

dB(S21), maximu m a vailable gain, an d associated gain (when th e inpu t is

ma tched for NF min and t he out put is then conjugat ely ma tched), versus

frequency

Sta bility factor, K, and geomet ric sta bility factors, mu _sour ce an d mu _load

versus frequen cy


min imu m n oise figure, source an d load st ability circles, and the following

reflection coefficient s (gam ma s) at a frequ ency selected by m oving a m ar ker :






Listing column s of dat a corr espondin g to th e frequen cy point selected by

moving a mar ker:



57/2004-3




phase






regar d t o noise)

Stability factor, K

SP_NF _Gain Mat chK.dds, Gain , Noise, an d St ability Circles page:

All at one frequen cy selected by moving a ma rk er:

Sta bility factor, K, an d sour ce an d load sta bility circles. Note t ha t th e Smith

cha rt size is fixed, so if th e st ability circles a re far out side th e Smith cha rt , they

will not be displayed. If you change the Smith cha rt scaling to Auto Scale, the

circles will be visible.

Available gain a nd n oise circles

Minimum noise figur e, sour ce impedan ce (Zopt) required to achieve this noise

figur e, an d th e optima l load im pedan ce for power tr an sfer wh en t he source

impedan ce is Zopt, as well as t he t ra nsdu cer power gain with th ese sour ce an d

load impedan ces


simu lta neous conjuga te m at chin g (only valid if K>1), and t he corr esponding

noise figur e

Noise figur e, tr an sducer power gain, and optima l load impedan ce if th e sour ceimpedan ce is chosen a rbitr ar ily by moving a ma rk er (Gam ma S) on a Smith

cha rt . This is useful if you mu st ma ke some compr omise between n oise an d

gain , or if you n eed to avoid an un st able region.

Power gain circles, on a different Sm ith cha rt

Tran sducer power gain, optimal sour ce impedance, an d corr esponding noise

figur e, if the load impedan ce is chosen a rbitr ar ily by moving a ma rk er


58/2004-4


(Gam ma L) on a Smith cha rt . This is useful if you n eed to avoid an un st able

region.

SP_NF_GainMatchK.dds, S Parameters, Group Delay page:

S11 and S22 on Sm ith cha rt s, also with a circle of consta nt VSWR

S21 and S12 (linear units) on polar plots

dB(S21) an d dB(S12) on a r ecta ngular plot

Group Delay in seconds, versus frequency.

Note This plot may be jagged if measu red S-para meter dat a is simu lated, and

th e nu mber of measu red points is sm all.

Schematic Name

SP_NF_GainMatchK

Data Display Name

SP_NF_GainMatchK.dds


59/2004-5

S-Parameter Simulations > Feedback Network Optimization to AttainStability

Description

This schema tic optimizes component values in in put , out put , an d feedback

sta bilizat ion n etwork s, to stabilize a 2-port net work , minimize the m inimum noisefigure, a nd ma ximize gain (dB(S21).) You ma y delete comp onen ts or modify th e

str uctu re of th e sta bilizat ion n etwork s.




Type of opt imizat ion a lgorit hm (gradient , ra nd om, genetic, etc.), goa l weight ing, goa

valu es, an d frequ ency ranges over wh ich n oise figure a nd ga in goals will beevaluated.


Geomet rically-derived sour ce and load st ability factors

Gain , dB(S21)

Minimum noise figure

Values of optimized component s

Schematic Name

Gain_and_Stab_opt

Data display name

Gain_and_Stab_opt.dds

Note

The optimizat ion resu lts m ay vary su bsta nt ially, dependin g on t he t ype of

optimizat ion algorith m used (set on t he N omina l Optimization cont roller) an d on t he

goa ls. Noise figure a nd ga in have been included as opt imizat ion goals. Oth erwise, the

optimizer might find a sta ble network , but with poor per form an ce as a n a mplifier.

The feedback net work topology might be modified, but th e dat a d isplay will also have

to be adjust ed. For example, if you use a tr an smission line (inst ead of lumped

elemen ts) to at ta in st ability and optimize th e length an d/or width of th e line, these

par am eter s can be displayed on t he da ta display by insert ing new listing column s.


60/2004-6


S-Parameter Simulations > S-Params, Gain, NF, Stability, Group Delay vsSwept Parameters

Description

This schem at ic sweeps two par am eter s in a circuit to determ ine how gain, n oise

figur e, ma tching impedan ces, st ability an d group delay depend on t he t wopar am eter s. Often t his sort of a simu lation pr ovides designers with m ore insight t ha n

an optimizat ion. You mu st decide which two para met ers t o sweep, an d you ma y

modify the n etwork to be simu lat ed.




Network t opology, two par am eter s t o sweep an d t heir sweep r an ges, frequen cy rangefor S-para met er simu lation


SP_NF _GainMa tchKsweep.dds, Mat ch ing for Ga in or NF page:

Minimum noise figure versus frequency


ma tched for NF min and t he out put is then conjugat ely ma tched), versus

frequency


ma tched for NF min a nd t he outpu t is th en conjugat ely ma tched), versu s each

swept pa ra meter, with t he oth er pa ra meter held consta nt , at one frequency

selected by a ma rk er

Stability factor versus frequency


min imu m noise figure, and the following r eflection coefficient s (gamm as) at a

frequ ency selected by moving a ma rk er:






61/2004-7


Listing column s of dat a corr espondin g to th e frequen cy point selected by

moving a mar ker:





phase






regar d t o noise)

Stability factor, K

SP_NF_GainMa tchKsweep.dds, Sta bility Factors an d Minimu m NF page:

Sta bility factor, K, versu s both swept pa ra meters a nd frequency

Sta bility factor, K, versu s both swept par amet ers, at one frequency selected bymoving a ma rker

Minimum n oise figure versus both swept par ameters an d frequency

Minimum noise figure versu s both swept pa ra meters, at one frequency selected

by moving a m ar ker

SP_NF_GainMa tchKsweep.dds, S Pa ra ms an d MAG at 1 Fr eq. page:

S-parameters versus both parameters

Minimum noise figure versus both swept parameters

Maximum a vailable gain versus both swept para meters

SP_NF _Gain Mat chKsweep.dds, Group Delay page:

Group delay versus both swept para meters and frequency

Group delay at one combination of th e swept par am eters, versus frequency


62/2004-8


Schematic Name

SP_NF_GainMatchKsweep

Data Display Name

SP_NF_GainMatchKsweep.dds

Note

Some of th e simulat ion r esults on t hese da ta displays can be obta ined via th e ADS

tu ning featu re. However, these data displays show the resu lts in a forma t t ha t m ay

ma ke it easier for you t o an alyze the da ta an d determine what th e optimal par am eter

values a re.


63/2004-9

S-Parameter Simulations > S-Params., Stability, and Group Delay vs.Frequency and Input Power

Description

This schema tic simu lates th e large-signa l S-par am eter s of a d evice, versus frequen cy

an d inpu t power. The st ability factor, K, is compu ted from t hese S-par am eters, u singth e sta nda rd form ula foun d in t extbooks. This simu lat ion set up differs from th e

LSSP cont roller in th at sma ll-signa l mixer mode is u sed to inject a sma ll signa l at th e

ou tput of th e device, while th e inpu t is being dr iven by a la rge signa l sour ce. This

gives a mu ch more r ealistic simula tion of S12 an d S22.


Nonlinea r model, or an am plifier with nonlinear device m odels

Main Schematic SettingsRan ges over which t o sweep th e inpu t s igna l frequen cy an d power


Stab_vs_freq_pwr.dds, Stability an d S-Par amet er P lots page:

S-Param eters versus input frequency and input power

Sta bility factor, K, versus inpu t frequency and inpu t power

St ab_vs_freq_pwr.dds, Group Delay pa ge:

Group delay versu s frequen cy, with t he inpu t power selected by moving a

marker

Schematic Name

Stab_vs_freq_pwr

Data Display Name

Stab_vs_freq_pwr.dds

Note

The st ability factor is only compu ted a t th e frequ ency of th e inpu t s igna l. The

sta bility factors at higher a nd lower frequen cies are n ot compu ted.


64/2004-10



65/2005-1

Chapter 5: 1-Tone Nonlinear Simulations

The tem plates in t he 1-Tone Nonlinear Simu lationsar e for simu lating thelarge-signa l cha ra cter istics of an am plifier or device, such as gain, ha rm onic

distort ion, power-ad ded efficiency, gain compres sion, et c. Setu ps for simu lat ing t hese

versus frequ ency, power, and ar bitr ar y swept par am eter s a re included. Load- an d

Sour ce-pull simulat ions an d impedan ce optimizat ion setu ps a re a lso included. These

simu lations do require nonlinea r model(s).


66/2005-2

1-Tone Nonlinear Simulations

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion

Description

This is th e most ba sic simula tion set up, and it simu lates t he spectr um , out put power

power gain, a nd h ar monic distort ion of a device or a mplifier. A sample power

amplifier is pr ovided. You mu st repla ce this a mplifier with your own device oramplifier, and m odify the biases, as n eeded.


A device or a n a mplifier using non linea r m odel(s)


Inpu t frequen cy an d a vailable source power


Output spectru m and voltage waveform

Ou t pu t power

Tran sducer power gain (power delivered to th e load minus power available from

th e sour ce)

Har monic distortion up to the 5th, in dBc

Schematic Name

HB1Tone

Data Display Name

HB1Tone.dds


67/2005-3

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion(w/PAE)

Description

This simu lation setu p is identical t o th e HB1Tone schema tic, except t ha t it includes

two curr en t probes and nam ed volta ge nodes for calculat ing power-added efficiency. Italso simu lates th e spectr um , out put power, power gain, an d h ar monic distortion of a

device or a mplifier. A sa mple power a mplifier is p rovided. You mu st rep lace th is

amplifier with your own device or amplifier, an d you can modify th e biases, as

described in th e n otes, below.


A device or a n a mplifier using non linea r m odel(s)

Main schematic settingsInpu t frequen cy, ava ilable sour ce power, and bias set tin gs


Output spectru m an d input a nd output voltage waveforms

Ou t pu t power

Tran sducer power gain (power delivered to th e load minus power available from

th e sour ce)

Har monic distortion up to the 5th, in dBc

Power-added efficiency (Pout at fun dam ent al minu s Available sour ce

power)/(DC power consumption)

High supply cur rent

DC power consumption

Therma l power dissipation in t he device or a mplifier

Schematic Name

HB1TonePAE

Data Display Name

HB1TonePAE.dds


68/2005-4

1-Tone Nonlinear Simulations

Note

Only bias su pplies on t he h ighest level schema tic will be included in t he PAE

ca lcula tion. So, for example, if you r eplace th e samp le am plifier with one with t he

bias su pplies included in t he su bcircuit, t hose supplies will not be includ ed in t he

PAE calculat ion. On t he highest level schema tic, you can delete one of th e two

supplies an d/or r eplace th e voltage sources with cur ren t sour ces, and th e PAE

ca lcu lat ion will st ill be valid. You can modify th e componen ts in t he bia s n etwork ,

rea lizing th at th e DC power consu mpt ion is compu ted a s (th e DC voltage at th e

Vs_high node) * (th e DC cur ren t in t he Is_high cu

Documents

Design Amplifier