DES_EDA_609_Lecture2_Oct03_2010

8/8/2019 DES_EDA_609_Lecture2_Oct03_2010

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DES/EDA609 :

Principles of ASIC Design

Jayaraj NarayanaOct 3rd 2010


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Last Class

Course Information

History : Transistors, ICs, Moores Law, etc.

ASICs : Introduction and Types Full-custom, semi-custom ICs Standard-cell, Gate-array

Programmable ASICs

Design Methodology / Flow : ASIC

FPGAs : Introduction

ASICs vs FPGAs : A comparison


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Agenda

ASIC Cell Libraries

CMOS Logic :Logic Levels, Design Rules

Layout, Stick diagrams

Sequential & Data Path Logic Cells

Residue Number Systems I/O Cells


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ASIC Cell Libraries

Cell Library is key part of ASIC design

Options: Design kit , ASIC vendor, third party library

ASIC vendor Library

Phantom library ( empty boxes)

ASIC vendor fills empty boxes after layout hand off

Buy or build library : A Decision

Target for a qualified cell library ( can buy )

Develop a cell library in house

Views : Physical layout, models ( behavioral / timing/ wire-load/routing), Circuit

schematic, test strategy, cell icon.

Characterization : Simulation of each cell with extracted parasitics to determine

switching delays


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CMOS Logic, Layout, Design Rules


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3D Perspective of nMOS Transistor

Polysilicon Aluminum


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Complementary CMOS

Complementary CMOS logic gates

nMOSpull-down network

pMOSpull-up network

a.k.a. static CMOS

pMOS

pull-upnetwork

output

inputs

nMOSpull-down

network

X (crowbar)0Pull-down ON

1Z (float)Pull-down OFF

Pull-up ONPull-up OFF


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Signal Strength

nMOS pass strong 0 But degraded or weak 1

pMOS pass strong 1 But degraded or weak 0

Thus NMOS are best for pull-down network

Thus PMOS are best for pull-up network


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Conduction Complement Complementary CMOS gates always produce 0 or 1

Ex: NAND gate Series nMOS: Y=0 when both inputs are 1

Thus Y=1 when either input is 0

Requires parallel pMOS

Rule ofConduction Complements Pull-up network is complement of pull-down

Parallel -> series, series -> parallel

A

B

Y


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CMOS Gate Design

A 4-input CMOS NOR gate

A

B

C

DY


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Example: O3AI

DCBAY ++= )(


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Example: O3AI

A B

Y

C

D

DC

BA

DCBAY ++= )(


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Layout of Inverter : Detailed Steps

Gnd

Vp

xx


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Inverter Cross-section

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND V

DD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


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Layer Types

p-substrate

n-well

n+

p+

Gate oxide

Gate (polysilicon) Field Oxide

Insulated glass

Provide electrical isolation


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CMOS Process LayersLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+)Green


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Gate Layout

Layout can be very time consuming

Design gates to fit together nicely

Build a library of standard cells

Standard cell design methodology

VDD and GND should abut (standard height)

Adjacent gates should satisfy design rules

nMOS at bottom and pMOS at top

All gates include well and substrate contacts


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Layout

Chips are specified with set of masks

Minimum dimensions of masks determine transistor size (and hence

speed, cost, and power)

Feature sizef= distance between source and drain Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design rules

Express rules in terms of l =f/2

E.g. l = 0.3 mm in 0.6 mm process


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Inverter Layout

Transistor dimensions specified as Width / Length

Minimum size is 4l / 2l, sometimes called 1 unit

Inf= 0.6 mm process, this is 1.2 mm wide, 0.6 mm long


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Example: Inverter


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Example: NAND3

Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates

Metal1 VDD rail at top Metal1 GND rail at bottom

32 by 40


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NAND3 (using Electric), contd.


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Stick Diagrams

Cartoon of a layout.

Shows all components.

Does not show exact placement, transistor sizes,

wire lengths, wire widths, boundaries, or anyother form of compliance with layout or design rules.

Useful for interconnect visualization, preliminary layout

layout compaction, power/ground routing, etc.


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Stick Diagrams

Stick diagrams help plan layout quickly

Need not be to scale

Draw with color pencils or dry-erase markers


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Stick Diagrams




VinVout

VDD

GND


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Stick Diagrams

Metal

poly

ndiff

pdiff

Can also draw

in shades of

gray/line style.


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Stick Diagram - Example I

NOR Gate

OUT

B

A


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Stick Diagrams





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Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

Dimensionless layout entities Only topology is important Final layout generated by

compaction program


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Activity 2

Sketch a stick diagram for a 4-input NOR

gate


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Activity 2 Sketch a stick diagram for a 4-input NOR gate

AVDD

GND

B C

Y

D


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Design Rules


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Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

Unit dimension: Minimum line widthscalable design rules: lambda parameter

absolute dimensions (micron rules)


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Wiring Tracks

A wiring trackis the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch

Transistors also consume one wiring track


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Well spacing Wells must surround transistors by 6 l

Implies 12 l between opposite transistor flavors

Leaves room for one wire track


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Area Estimation Estimate area by counting wiring tracks

Multiply by 8 to express in l


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Example: O3AI

Sketch a stick diagram for O3AI and estimate area

DCBAY ++= )(


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Example: O3AI

Sketch a stick diagram for O3AI and estimate area

DCBAY ++= )(

E l O3AI


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Example: O3AISketch a stick diagram for O3AI and estimate area

DCBAY ++= )(


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Simplified Design Rules

Conservative rules to get you started


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Intra-Layer Design Rules

Metal24

3

1 0

90

W e l l

A c t i v e3

3

P o l y s i l i c o n

2

2

D i f f e r e n t P o t e n t i a lS a m e P o t e n t i a l

M e t a l 1 3

3

2

C o n t a c to r V i a

S e l e c t

2

o r6

2H o l e


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Sequential Logic Cells

Latch

Flip-Flop

Clocked Inverter


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D Latch Design

Multiplexer chooses D or old Q

1

0

D

CLK

Q CLK

CLKCLK

CLK

DQ Q

Q

Old Q


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D Latch When CLK = 1, latch is transparent

Q follows D (a buffer with a Delay)

When CLK = 0, the latch is opaque

Q holds its last value independent of D

a.k.a. transparent latch orlevel-sensitive latch

CLK

D QLatch D

CLK

Q


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D Latch Operation

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q


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D Flip-flop

When CLK rises, D is copied to Q

At all other times, Q holds its value

a.k.a.positive edge-triggered flip-flop, master-slave flip-flop

Flop

CLK

D Q

D

CLK

Q


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D Flip-flop Design

Built from master and slave D latches

QM

CLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latch

Latch

D QQM

CLK

CLK

A negative level-sensitive latch A positive level-sensitive latch


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D Flip-flop Operation

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q

Inverted version of D

Q -> NOT(NOT(QM))

Holds the last value of NOT(D)


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Race Condition

Back-to-back flops canmalfunction from clock skew

Second flip-flop fires Early

Sees first flip-flop change

and captures its result

Called hold-time failure or

race condition


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Timing ConstraintsR1

D QCombinational

Logic

In

CLK tCLK1

R2

D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Minimum cycle time:

T - = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )


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Timing ConstraintsR1

D QCombinational

Logic

In

CLK tCLK1

R2D Q

tCLK2

tc qtc q, cdtsu, thold

tlogict

Hold time constraint:

t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives late

Race between data and clock


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Nonoverlapping Clocks

Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew

Good for safe design

Industry manages skew more carefully instead 1

1 1

1

2

2 2

2

2

1

QMQD


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Clocked Inverter

A series combination of an inverter and a transmissiongate


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Datapath Logic Cells

Adder

Ripple, Carry Save, Carry Bypass, Carry Skip

Carry Look ahead Adders ( Brent-Kung)

Carry Select and Conditional Sum adder


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Adders

A. Conventional number system.

Carry-propagate adders / Ripple carry Adders (CPA / RCA)

Carry-skip adder

Carry-lookahead adder

Carry-select adder

Conditional-sum adder

B. Redundant number system : limited carry propagation

Carry-save adder

F ll Add


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Full-Adder

A B

Cout

Sum

Cin Fulladder


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Full Adder Implementations

Th Bi Add


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The Binary Adder

S A B Ci

=

A= BCi A BCi AB Ci A B Ci+ + +

Co

A B B Ci

A Ci

+ +=

A B

Cout

Sum

Cin Fulladder

d f i f


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Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A B

Delete/Kill= A

B

Can also derive expressions forSand Co based on D and P

Propagate (P) = A + BNote that we will be sometimes using an alternate definition for

Th Ri l C Add


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The Ripple-Carry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

FA FA FA FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

A3 B3

S3

Ci,0 Co,0

(= Ci,1)

Co,1 Co,2

td= O(N)

tadder= (N-1)tcarry+ tsum


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C B Add


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Carry-Bypass Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co, 2Co ,1Co,0Ci,0

F A FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co, 1Co ,0Ci,0

Co,3

Multiplexer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else kill or generate.

Also called

Carry-Skip


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Carry Skip Adder

L kAh d B i Id


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LookAhead - Basic Idea

Co k, f A k Bk Co k, 1, ,( )Gk P kCo k 1,+= =

AN-1, BN-1A1, B1

P1

S1

SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A

L k Ah d T l


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Look-Ahead: Topology

Co k,Gk Pk Gk 1 Pk 1 Co k 2,

+( )+=

Co k, Gk Pk Gk 1 P k 1 P1 G0 P0 Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2


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Carry Lookahead Trees

Co 0, G0 P0Ci 0,+=

Co 1,

G1

P1

G0

P1

P0

Ci 0,

+ +=

Co 2, G2 P2G1 P2 P1G0 P+ 2 P1P0C i 0,+ +=

G2 P2G1+( )= P2P1( )G0 P0Ci 0,+( )+ G 2:1 P2:1Co 0,+=

Can continue building the tree hierarchically.


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Multipliers


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Multipliers

The Binary Multiplication


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The Binary Multiplication

x

+

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1

Canonical Signed Digit Vector


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Note : B = Binary Number, D= CSD vector

Ci+1 is the Carry from the sum of Bi+1 + Bi + Ci ( start with C0=0)

Canonical Signed Digit Vector

Booths Algorithm


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Booth s Algorithm

Booths Algorithm Rules


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g

Booths Algorithm An Example


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Booth s Algorithm An Example

Radix-4 Modified Booths Algorithm


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g

Radix-4 Booths Algorithm Rules


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Radix-4 Versus Radix-2 Booths Algorithm


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Residue Number System: Continued


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A residue number system (RNS)represents a large integer using a set of

smaller integers, so that computation

may be performed more efficiently

We add, subtract or multiply residue

numbers using modules of each bitposition - without any carry.


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Other Datapath Operators


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Subtracter

Barrel-Shifter

Leading-one detector

Priority Encoder Accumulator

Decrementer

All-zeros / ones detector

Register File

FIFO


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Summary

ASIC Cell Libraries

CMOS Logic :Logic Levels, Design Rules

Layout, Stick diagrams

Sequential & Data Path Logic Cells

Residue Number Systems

I/O Cells


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Next Class

ASIC Library Design:

Logical Effort,

Library-Cell Design,

Gate-Array Design,

Standard-Cell Design.

Documents

DES_EDA_609_Lecture2_Oct03_2010