Demonstration of Ultra-thin Tantalum Capacitors on Silicon Substrates for High-frequency and High-efficiency Power Applications

Parthasarathi Chakraborti1, Saumya Gandhi1, Himani Sharma1, P. M. Raj1,

Kamil-Paul Rataj2 and Rao Tummala1 13D Systems Packaging Research Center

Georgia Institute of Technology Atlanta, GA USA 30332

2HC Starck Gmbh Landsberger Straße 94-98

80339 München, Deutschland Email: partho@gatech.edu

Abstract This paper describes an innovative scheme for integrating

thinfilm tantalum (Ta) capacitors on active silicon substrates, an approach that can serve as a roadmap for the potential integration of ultra-thin high density capacitors in near future. The paper describes a new 3D concept for ultra-miniaturized, multi-functional and relatively low-cost power converter modules. The scheme consists of planar tantalum (Ta) capacitors by forming Ta2O5 (30-120 nm thick) dielectric and attaching directly to active or passive Si substrates using ultra-loss dielectrics (Zeon, ZS-100). Capacitors attached directly on Si allow for shorter interconnection length (< 10µm) yielding lower parasitics in loop inductance and planar resistance. Reducing these parasitics results in higher switching frequency (>100 MHz) with fewer Ta capacitors on active Si.

The paper focuses on capacitor fabrication of ultra-thin Ta foils (< 5µm) and their integration on ultra-thin active Si for lowering the parasitics. Consequently, electrical characterization of the above capacitors demonstrates the fundamental electrical superiority of the 3D integrated Ta capacitors.

Introduction Thinfilm active and passive components are the lynchpin

of any electronics industry such as bioelectronics, wireless, wearables, sensing, and computing. The passive components consume as much as 50% of all real estate on system board [1, 2]. However, there are major impediments to their use in many consumer systems requiring low impedance for power storage, power supply and power conversion [3]. Some of these components include batteries, decoupling capacitors and inductors in VRMs[4], among others. The thinfilm decoupling capacitors[5, 6] act as charge reservoirs that can be used to suppress the noise caused by the package parasitics. Their use as discrete components leads to longer interconnect lengths, yielding higher parasitic inductance[7, 8], thus limiting their effective operating frequency [9]. This paper addresses this issue by employing these capacitors in thinner form-factors that can be designed and integrated in new concepts such as 3D Integrated Passive and Active Components (3D IPAC)[1, 9, 10] close to the active components.

Many thinfilm capacitors with high permittivity dielectrics such as Barium Strontium Titanate (BST) and

Barium Titanate (BT) [11-14] achieve high capacitance densities due to their ferroelectric nature yielding high dielectric constants. However, their low stability to frequency and voltage response present several operational challenges. Both of them have Temperature Coefficient of Capacitance (TCC) [15], which leads to loss in capacitance densities at elevated temperatures.

This paper addresses some of the above challenges with ultra-thin Ta foils (< 5µm) and their integration on ultra-thin active Si for lowering the parasitics. Fig. 1 illustrates the proposed planar tantalum capacitors as thinfilms, integrated on active silicon. This direct integration of Ta thinfilms on active silicon opens new avenues to reduce the parasitics by eliminating the inductances from long interconnections.

Fig. 1. Schematic of the integrated planar tantalum capacitor.

As can be seen in Fig. 1, the tantalum foils are integrated on silicon using an adhesive layer, followed by growing the dielectric layer and depositing conducting polymer application to complete the fabrication of the capacitor. Thereafter, the capacitor is encapsulated using a planarization layer and individual vias are drilled to separately access anode, cathode and the active silicon followed by electroplating. This completes the integration of such capacitors as thinfilms on active silicon.

This proposed approach integrated planar tantalum capacitor presents a number of attributes to enhance the thinfilm passives and their integration technologies: 1) positive TCC of Ta2O5 yields higher capacitance at elevated operational temperatures (13% rise at 125oC vs. room temperature); 2) capacitance stability of 0.13 µF/cm2 in response to voltage variation from 1 V till 10 V; 3) optimized anodization conditions yield high insulation strength of dielectric with leakage current of 0.1 pA/nF, frequency

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stability from 40 Hz up to 10 MHz; 4) does not require high temperature processes and is therefore compatible with silicon; 5) the low cost integration process eliminates the use of expensive semiconductor tools; 6) direct integration of the thinfilms on active silicon eliminates loop inductance and parasitics; and 7) finally, it can be used as wafer or package process, as the proposed approach is compatible with large area active silicon and high through-put glass interposers and packages.

Experimental The schematic in Fig. 2 illustrates the integration scheme

of the planar tantalum capacitors on active silicon.

Fig. 2. Process flow for integration planar Ta capacitors on

Silicon.

Tantalum foil (25µm thick, purchased from Sigma Aldrich) was used as anode. 100µm Diameter vias were mechanically drilled through the foil. The foils with drilled vias were then laminated onto the active Si wafer using ultra-low loss adhesive (Zeon dielectric) at a temperature of 200 F and high pressure (100 atm). Vias were drilled through the Zeon dielectric layer to separately access the Cu pads on Si. Tantalum pentoxide, as dielectric, was grown using the known anodization process.

Several parameters such as voltage, electrolyte concentrations and current density were studied to optimize

the anodization conditions. These anodization parameters have been tabulated in Table 1.

Table 1. Anodization conditions to form Ta pentoxide

Electrolyte Phosphoric acid Voltage 60 V Time 180 mins Temperature 85oC Current density 20 mA/cm2

Conducting polymer was used as the cathode with

sputtered copper as the current-collector. The cathode material was chosen because of its self-healing characteristics [16-22] while the distributed planar copper interface lowered the Equivalent Series Resistance (ESR). The cathode was patterned with a subtractive plasma-etching with the patterned copper as the etch mask. The copper also acted as the seed layer in the subsequent steps for electroplating. This completed the capacitor fabrication process. This was followed by lamination of another layer of Zeon dielectric (as planarization layer) on the capacitor at the conditions mentioned above. Finally, vias were drilled through the Zeon dielectric to separately access the anode and cathode followed by electroplating these vias to complete the integration scheme.

The integrated capacitors were then characterized for Break-Down voltage (BDV), leakage current, capacitance density and frequency-stability measurements. Zeiss Ultra60 FE-SEM was used for the morphological analysis. HP 4285A precision LCR meter was used for C-V and frequency- stability measurements. Keithley 6485 picoammeter was used for the leakage current measurements.

Results and Discussions An applied voltage bias of 60 V shows a typical current-

time response as shown in Fig. 3. As can be seen from the figure, the current logarithmic goes down with time. This could be attributed to a thicker tantalum pentoxide barrier formed with passage of time during the process of anodization.

 Fig. 3. Current Vs time plot depicting tantalum anodization

Anodization proceeds through the diffusion of oxide ions and tantalum ions from the electrolyte solution and the

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tantalum metal respectively resulting in the formation of a barrier layer of tantalum pentoxide as shown in Fig. 4 [23]. A thicker barrier impedes the diffusion of the tantalum interstitial and oxide ion flux through the barrier layer which manifests as lower current.

 Fig. 4. Schematic depicting tantalum anodization

The set of equation representing the anodization process are shown in the schematic in Fig. 5 based on the point defect model[24].

 Fig. 5. Set of equations representing tantalum pentoxide formation[24, 25]

Here, Tai5+ represents the tantalum interstitials whereas

VO.. represents oxygen vacancy. It is important to note that

oxide ions interstitials originate from oxygen vacancies and oxygen vacancies diffuse in an opposite direction compared to the diffusion of oxide ions. Therefore, while oxygen vacancies (Fig. 5) migrate towards from electrolyte, the oxide ions migrate away from the electrolyte (Fig. 4). Optical Characterization

Figs. 6 (a – d) show the optical images of the capacitor at different stages of fabrication. Fig. 6a demonstrates the tantalum foil laminated to active silicon using ZIF adhesive. This was followed by anodization and subsequent conducting polymer dispensing on the anodized tantalum foil (Fig. 6b). Thereafter, the copper patterns were evaporated through a shadow mask as shown in Fig. 6c. Thereafter, the conducting polymer was substractively etched using plasma with the copper pattern acting as the mask. The conducting polymer was removed in the process from areas not below the copper patterns (Fig. 6d).

Fig. 6. Capacitor fabrication steps: (a) lamination of Ta foil to

Si wafer, (b) anodization of Ta foil and dispensing of conducting polymer, (c) evaporation or sputtering of Ti/Cu

through shadow mask, and (d) subtractive etching of conducting polymer.

Fig. 7. Vias through the photo-definable dielectric.

Fig. 7 shows the optical image of the blind vias through the photo-definable (SU8) landing copper pads below in step (d). No delamination was observed at the interfaces between

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the planarized ZIF dielectric and anode, ZIF and copper, and, copper and cathode. The thickness of ZIF dielectric used as planarization layer is 22µm. The dielectric thickness was estimated as ~130 nm with higher voltage anodization (60 V) as seen from the micrograph. The interconnects in the form of vias are shown to land on the anodes and the current collector. Electrical Characterization

The capacitance density of the integrated planar tantalum capacitors was measured to be 0.13 µF/cm2 at 100 KHz with 0V bias and 100 mV peak amplitude. Fig. 8 illustrates the capacitance density vs frequency for the integrated planar tantalum capacitors.

Fig. 8. Flat cap density vs. frequency showing Frequency

stability.

Fig. 9. Leakage current and breakdown voltage of integrated

planar Ta caps on Si.

The capacitance density was measured from 40 Hz till 10 MHz and was observed to be ~0.13 µF/cm2 for the entire range of frequencies. The stable values of capacitance density till 10 MHz could be attributed to the low ESR of the cathode, the current collector and cathode interface which shifts the roll-off frequency and consequently, self-resonating frequency to higher values. Moreover, there is no degradation of the tantalum pentoxide dielectric, as the dielectric does not interact unlike in other valve metal oxides such as aluminum oxide, thus, rendering a stable dielectric. This contributes to far less lossiness of dielectric which is also manifested in the

form of low direct leakage current. Fig. 9 illustrates the normalized leakage current vs. voltage.

As shown in Fig. 9, the leakage current was measured below 0.01 nA/nF up to 10 V, followed by a gradual rise. Anodization is known to yield conformal and self-limiting dielectric films with lesser volumetric defect density such as pin-holes and micro-cracks compared to other dielectric deposition techniques such as sputtering and Atomic Layer Deposition (ALD). Furthermore, higher anodization voltage serves to grow thicker dielectric that further brings down the defect density formed in the dielectric. Hence, the low leakage currents could also be attributed to thick dielectric layers formed by the process of anodization. Breakdown voltage for the capacitor was observed to be 30V when the normalized current spiked to 1 µA/nF beyond 30 V. Fig. 10 demonstrates the capacitor behavior as a function of temperature for the integrated planar tantalum capacitors.

Fig. 10. Capacitance density of the integrated planar Ta

capacitors as a function of temperature.

Fig. 11. Voltage stability of the integrated planar Ta

capacitors (cap density vs. voltage).

The capacitance enhancement was observed to be 13% when the measurement temperature was increased from room temperature to 125oC which corresponds to a TCC of 117 ppm/C. The TCC values reported here are slightly higher which could be attributed to the presence of lattice hydroxyl defects.

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Fig. 11 illustrates the voltage stability for the integrated planar tantalum capacitors.

The capacitance density was observed to be fairly consistent at ~0.13 µF/cm2 for the entire range of DC bias from 1-5 V. It is important to note that the integration scheme did not degrade the electrical properties of the planar integrated capacitor in frequency and voltage stabilities of the capacitance density as well as the low leakage values.

Conclusions In summary, an active silicon compatible capacitor

thinfilm technology was demonstrated with superior electrical properties. These included frequency stability up to 10 MHz along with ultra-low leakage current of 0.01 nA/nF up to 10 V. These innovative integration scheme can propel the thinfilm approaches to high-density capacitors at low cost.

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