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6.7.4.2

6.7.4.1

Deliverable Overview

US ATLAS HL-LHC CD-3a Review, July 9-11, 2019

• The global theme of the WBS is interfacing custom and commodity systems.

• 6.7.4.1: Firmware for Hardware Track Trigger Interface (HTT IF) to transmit data between HTT and the processor farm

• 6.7.4.2: Firmware for the Global Trigger to transmit data between the Global Trigger and FELIX

• Firmware for the both systems is fully custom.

Deliverable 6.7.4.1

The hardware track trigger (HTT) are key to operating of the ATLAS experiment during the HL-LHC program The regional tracking will reconstruct tracks with pT>2 GeV at 1 MHz in

selected regions of interest.

The global tracking will reconstruct all tracks with pT>1 GeV at 100 kHz.

The HTT will be connected to commodity data networks through the HTT interface (HTT IF).

We will need to develop data handling firmware that resides in the HTT IF.

Track Processor board

(UPenn)

HTT Interface Network (e.g. Ethernet) Custom data link Event Filter

(Comp. farm) Aurora 64b/44b

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Deliverable 6.7.4.1

Technical challenges Data routing is not trivial because significant data duplication is needed

between the track processor boards in each ATCA shelf.

o We defined specifications for the data distribution architecture and i/o bandwidth. The spec review is in August 2018.

We need to avoid large time skew when the data is delivered from HTT IF to the track processor boards.

o Data sharing through the ATCA backplane requires that.

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Deliverable 6.7.4.2

The global common module is described in WBS 6.7.1

Argonne will develop firmware to connect the global trigger system and FELIX. Most of physics data is from Global Event Processors (GEP) into FELIX.

MUX’s will output mostly monitoring data from.

TTC will be provided by FELIX to all the GCM boards.

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Deliverable 6.7.4.2

The firmware blocks that are needed to be developed are depicted with the green boxes. The FELIX up-link and downlink blocks will instantiate the multi-gigabit

transceivers, provide clock and data recovery, and process GBT frames.

The TTC (Trigger and Timing Control) block will decode the TTC information from the unpacked GBT frames and will provide the data to the entire system.

The Readout formatting block will translate physics or monitoring data into frames for transmission through the high-speed serial links.

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Risks Overview

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Expected Risk

Risk-ID Expiration Title Rank

RD-06-07-04-001 31-Aug-22 Different I/O interface for hardware track trigger (HTT) 90

RD-06-07-04-002 30-Nov-22 Additional data handling needed between GLOBAL and FELIX 60

Risk Overview

• By phase (well into pre-production), list the risks that have been considered (bandwidth estimates are wrong) Loss of key personnel has small impact. Present during all stages.

This is likely to take multiple slides (one per phase?)

• Some questions to ask yourself: What could possibly go wrong?

o FELIX I/O cards may be available late of the performance may be less than expected. The nature of the impact is similar to the considered risks.

If it were your money, what would you hedge against? Inaccurate simulations and, consequently, bandwidth estimates for the forward regions of ATLAS ITk.

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Risks – HTT Interface

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WBS 6.7.4 Type Threat Risk ID RD-06-07-04-001 Status Active

Expires 31-Aug-2022

Title Different I/O interface for hardware track trigger (HTT)

Summary The different throughput and latency requirements on I/O may require different firmware functionality and performance of HTT Interface.

Owner Jinlong Zhang Probability Pre 40% Post 20% Cost Lo $75K Hi $150K Schedule Lo 3.0 Hi 6.0 Tech Impact 1(L) Post Mitg Prob 5(M) Impact Score Cost 2(M) Sched 2(M) Rank=90 Mitigation Capture and refine the different requirements during the design and prototype phase. Response More effort to have one more firmware development cycle. Comments The cost for another prototype cycle 150k. Phase Effected Affects task FTK710850

US ATLAS HL-LHC DOE IPR/CD-3a, July 9-11, 2019, BNL Alexander Paramonov, DAQ

Risks – GLOBAL to FELIX

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WBS 6.7.4 Type Threat Risk ID RD-06-07-04-002 Status Active

Expires 30-Nov-2022

Title Different I/O interface for hardware track trigger (HTT)

Summary The different throughput and latency requirements on I/O may require different firmware functionality and performance of HTT Interface.

Owner Jinlong Zhang Probability Pre 20% Post 10% Cost Lo $75K Hi $150K Schedule Lo 3.0 Hi 6.0 Tech Impact 1(L) Post Mitg Prob 3(L) Impact Score Cost 2(M) Sched 2(M) Rank=60 Mitigation Capture and refine the different requirements during the design and prototype phase. Response More effort to have one more firmware development cycle. Comments The cost for another prototype cycle 150k. Phase Effected Affects task RID3200

US ATLAS HL-LHC DOE IPR/CD-3a, July 9-11, 2019, BNL Alexander Paramonov, DAQ