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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IRM
SMA_CLKIN SMA_CLKOUT
CLOCK2_50CLOCK_50
CLOCK3_50
IRDA_RXD
VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC3P3
GPIO_VCCIOVCC3P3
VCC3P3 GPIO_VCCIO
VCC3P3
GPIO_VCCIO
VCC3P3GPIO_VCCIO
VCC3P3 GPIO_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA D
DE2-115 Main Board
B
9 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA D
DE2-115 Main Board
B
9 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & IrDA D
DE2-115 Main Board
B
9 28Tuesday, April 16, 2013
C279
0.1u
C275
0.1u
C88
0.1u
C278
0.1u
C276
0.1u
C90
47u
R83
10K C277
0.1u
IRM
U21
IRM_V538_TR1
VCC2
GND3
OUT1
CHASSIS4
VCCA VCCB
DIR GND
A B
U20
SN74AVC1T45
3 46
25
1 J15
PLL_CLKOUT
C83
0.1u
VCCA VCCB
DIR GND
A B
U14
SN74AVC1T45
3 46
25
1
C84
0.1u
J16
EXT CLOCK
R82 47
R80
1KDNI
Y4
50MHZ
VCC4
OUT3
GND2
EN1
VDD
GND
U16
PI49FCT3803
4
1
3571012
6
1415
28
911
13
16
C89
0.1u
R81
1KDNI
CLOCCLOCCLOCCLOCCLOCCLOCK2_5K2_5000K2_5K2_500000CLOCCLOCCLOCCLOCCLOCCLOCK_50K_50K_50K_50K_50K_50K_50
IRDA_RXD_RXD
VCC3P3
VCC3VCC3VCC3P3P3P3
VCC3P3VCC3
VCC3VCC3VCC3P3
C279C279C279C279C279C279C279
0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u
C278C278C278C278
0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u
C276C276C276
0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u0.1u
C90
47u
C277
0.1u
SN74
5
R82 4R82 4R82 477777R82 4
VDD
GND
U16
PI49PI49PI49PI49PI49PI49FCT3803
4
1
3571012
6
141415151515
28
911
11
11
13
16
16
a0225345Typewritten TextPMP10581
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KEYIN3
GNDGND
HSMC_VCCIOGND GND
GND
HSMC_VCCIO
GND
GND
GNDGND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GNDGND
GND
GND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GND
GND
GND
GNDHSMC_VCCIO
GNDGND
HSMC_VCCIO
GNDGND
GND
GND
HSMC_VCCIO
GND
GNDHSMC_VCCIO
GND
GND
GND
GNDHSMC_VCCIO
GNDGND
KEYIN1
GND
HSMC_VCCIOGND
GND
GND
GNDGND
HSMC_VCCIO
GND
GND
HSMC_VCCIO
SW17
GND
GND
GNDGND
HSMC_VCCIO
GNDGNDGND
SW14
GND
GND
HSMC_VCCIOSW15
GNDHSMC_VCCIO
GND
HSMC_VCCIO
SW12SW13
KEYIN2
KEYIN0 KEY0
KEY2KEY3
KEY1
SW3SW2SW1SW0
SW7SW6SW5SW4
SW11SW10SW9SW8
SW16
KEY3
KEY2
KEY1
KEY0
KEYIN3
KEYIN1KEYIN0
KEYIN2
SW[17..0]
KEY[3..0]
VCC3P3
VCC3P3
HSMC_VCCIO
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH D
DE2-115 Main Board
B
11 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH D
DE2-115 Main Board
B
11 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
BUTTON & SWITCH D
DE2-115 Main Board
B
11 28Tuesday, April 16, 2013
RN30 12012345
678
SW1
SLIDE SW
123
4
5
SW4
SLIDE SW
123
4
5
SW14
SLIDE SW
123
4
5
SW11
SLIDE SW
123
4
5
BUTTON1
6x6 SW
DNI
4 3
21
KEY1
TACT SW
4 3
21
C293
1u
R242 120
D75
BAT54S
1
23
KEY0
TACT SW
4 3
21
RN16 10K12345
678
BUTTON3
6x6 SW DNI
4 3
21
D78
BAT54S
1
23
SW10
SLIDE SW
123
4
5
SW8
SLIDE SW
123
4
5
SW3
SLIDE SW
123
4
5
C294
1u
SW17
SLIDE SW
123
4
5
KEY3
TACT SW
4 3
21
R241 120
D76
BAT54S
1
23
SW13
SLIDE SW
123
4
5
U19
74HC245
A12 A23 A34 A45 A56 A67 A78 A89
OE19
DIR1
B118B217B316B415B514B613B712B811
VCC20
GND10
SW0
SLIDE SW
123
4
5
RN33 12012345
678
RN35 12012345
678
D77
BAT54S
1
23
C292
1u
BUTTON0
6x6 SW
DNI
4 3
21
SW6
SLIDE SW
123
4
5
RN26 100K1234 5
678
SW9
SLIDE SW
123
4
5
SW5
SLIDE SW
123
4
5
BUTTON2
6x6 SW
DNI
4 3
21
SW16
SLIDE SW
123
4
5
SW2
SLIDE SW
123
4
5
KEY2
TACT SW
4 3
21
SW7
SLIDE SW
123
4
5
SW12
SLIDE SW
123
4
5
RN29 12012345
678
C295
1u
SW15
SLIDE SW
123
4
5
GND
HSMC_VCCIO_VCC
GND
GNDHSMC_VCC_VCC_VCC_VCC_VCCIOIOIOIO_VCC_VCC_VCC_VCC_VCC
GNDGNDGNDGNDGND
GND
GNDGNDGNDGND
GNDGNDGNDHSMCHSMC_VCC_VCC_VCC_VCC_VCCIO_VCC_VCC_VCC_VCC_VCC
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
HSMCHSMCHSMCHSMCHSMC_VCC_VCC_VCC_VCC_VCCIOHSMCHSMCHSMCHSMCHSMC_VCCIO
GNDGNDGNDGNDGND
GND
GNDHSMC_VCCIOIOIOIOIOIOHSMC_VCC
SW17SW17SW17SW17SW17SW17SW17SW17SW17SW17
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGND
HSMCGND
HSMCHSMCHSMCHSMCHSMCHSMCHSMCHSMCHSMCHSMC_VCC_VCC_VCC_VCC_VCC_VCC_VCC_VCC_VCC_VCCIOIOIOIOIOIOIOIOIOHSMCHSMCHSMCHSMC_VCC_VCC_VCC_VCC_VCC_VCC_VCC_VCC_VCCIOIOIOIOIO
SW3SW3SW3SW3SW3SW2SW1SW0
SW11SW10SW10SW10SW10SW10SW9SW9SW9SW9SW9SW9SW9SW9SW8SW8SW8SW8SW8SW8SW8SW8SW8
SW4SW4SW4SW4SW4SW4SW4
SLIDSLIDSLIDSLIDSLIDE SWE SWE SWE SW
11111123
4
5
SLIDSLIDSLIDSLIDSLIDSLIDE SWE SWE SWE SWE SWE SW
123
4
5555
R242 120120120120120120R242
SW13SW13SW13SW13SW13SW13SW13
12
4RN33RN33RN33RN33RN33RN33RN33RN33RN33RN33RN33RN33RN33 120
12333345
666778
SW6SW6SW6SW6SW6SW6
SLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDE SW
11122223
4
5
SW5SW5SW5SW5
SLIDSLIDSLIDSLIDE SWE SWE SWE SWE SWE SWE SW
123
4
55
SW12SW12SW12SW12SW12
SLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDSLIDE SW
122222333333
4444
555555
RN29 1201222344445
67
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Short pin1 and pin2: JTAG chain not including HSMCShort pin2 and pin3: JTAG chain including HSMC
HSMC_RX_D_n8HSMC_RX_D_p8
HSMC_RX_D_N3HSMC_RX_D_P3
HSMC_TX_D_P0HSMC_TX_D_N0
HSMC_RX_D_N4HSMC_RX_D_P4
HSMC_TX_D_P1HSMC_TX_D_N1
HSMC_RX_D_N5HSMC_RX_D_P5
HSMC_TX_D_P2HSMC_TX_D_N2
HSMC_RX_D_N6HSMC_RX_D_P6
HSMC_TX_D_P3HSMC_TX_D_N3
HSMC_RX_D_N7HSMC_RX_D_P7
HSMC_TX_D_P4HSMC_TX_D_N4
HSMC_TX_D_P5HSMC_TX_D_N5
HSMC_TX_D_P6HSMC_TX_D_N6
HSMC_TX_D_P7HSMC_TX_D_N7
HSMC_RX_D_n16HSMC_RX_D_p16
HSMC_RX_D_n9HSMC_RX_D_p9
HSMC_RX_D_n10HSMC_RX_D_p10
HSMC_RX_D_n11HSMC_RX_D_p11
HSMC_RX_D_n12HSMC_RX_D_p12
HSMC_RX_D_n13HSMC_RX_D_p13
HSMC_RX_D_n14HSMC_RX_D_p14
HSMC_RX_D_n15HSMC_RX_D_p15
HSMC_D3HSMC_D1
HSMC_PSNT_n
E_HSMC_CLKIN0E_HSMC_TDO E_HSMC_TDI
HSMC_RX_D_N0HSMC_RX_D_P0
HSMC_RX_D_N1HSMC_RX_D_P1
HSMC_D2HSMC_D0
HSMC_RX_D_N2HSMC_RX_D_P2
HSMC_TX_D_p16HSMC_TX_D_n16
HSMC_TX_D_p11HSMC_TX_D_n11
HSMC_TX_D_p12HSMC_TX_D_n12
HSMC_TX_D_p13HSMC_TX_D_n13
HSMC_TX_D_p14HSMC_TX_D_n14
HSMC_TX_D_p15HSMC_TX_D_n15
HSMC_TX_D_p8HSMC_TX_D_n8
HSMC_TX_D_p9HSMC_TX_D_n9
HSMC_TX_D_p10HSMC_TX_D_n10
HSMC_PSNT_n
E_HSMC_TMSE_HSMC_TCK
E_HSMC_TMSE_HSMC_TCKE_HSMC_TDIE_HSMC_TDO HSMC_TDO
E_HSMC_CLKIN0
EX_IO0EX_IO1EX_IO2EX_IO3
EX_IO4EX_IO5EX_IO6
HSMC_TDI
HSMC_TDO
HSMC_TMSE_HSMC_TMS
HSMC_TCKE_HSMC_TCK
HSMC_TDIE_HSMC_TDI
HSMC_TDOE_HSMC_TDO
HSMC_CLKIN_P1HSMC_CLKIN_N1
HSMC_CLKIN_P2HSMC_CLKIN_N2
HSMC_TX_D_P[16..0]HSMC_TX_D_N[16..0]HSMC_RX_D_P[16..0]HSMC_RX_D_N[16..0]
HSMC_CLKOUT_P2HSMC_CLKOUT_N2
HSMC_SDA
HSMC_TMSHSMC_TCKHSMC_TDI
HSMC_CLKIN0
HSMC_CLKOUT_N1HSMC_CLKOUT_P1
HSMC_D[3..0]
EX_IO[6..0]
JTAG_TDO
HSMC_CLKOUT0
HSMC_SCL
VCC3P3
VCC3P3
VCC12
VCC3P3VCC2P5
VCC2P5 VCC3P3
VCC2P5
HSMC_VCCIOGPIO_VCCIO GPIO_VCCIO HSMC_VCCIO
VCC3P3
VCC3P3
VCC3P3VCC12
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC D
DE2-115 Main Board
C
13 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC D
DE2-115 Main Board
C
13 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
HSMC D
DE2-115 Main Board
C
13 28Tuesday, April 16, 2013
JP3
HEADER 3
123
D40
LEDG
R158
2.2K
C171
0.1uDNI
R1592.2K
R77
120
C172
0.1uDNI
R1812.2K
R257 0
C180
10u
R1712.2K
R1702.2K
R258 0
VCCA VCCB
DIR GND
A B
U25
SN74AVC1T45
3 46
25
1
VCCA VCCB
OE GND
U22
TXS0104ERGYR
DNI
45
2 13121110
14
15
8
1
3
7
R1692.2K
C182
10u
C241
22u
R259 0
C179
0.1u
JP4
HEADER 7X2
12345678910
11121314
C181
0.1u
R160 33
R147 10K
DNI
16
11
62
16
31
64
16
81
65
16
61
67
16
91
72
17
01
71
JP8
HSMC
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
6161
6363
6565
6767
6969
7171
7373
7575
7777
7979
8181
8383
8585
8787
8989
9191
9393
9595
9797
9999
101101
103103
105105
107107
109109
111111
113113
115115
117117
119119
121121
123123
125125
127127
129129
131131
133133
135135
137137
139139
141141
143143
145145
147147
149149
151151
153153
155155
157157
159159
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
6262
6464
6666
6868
7070
7272
7474
7676
7878
8080
8282
8484
8686
8888
9090
9292
9494
9696
9898
100100
102102
104104
106106
108108
110110
112112
114114
116116
118118
120120
122122
124124
126126
128128
130130
132132
134134
136136
138138
140140
142142
144144
146146
148148
150150
152152
154154
156156
158158
160160
161161
162162
163163
164164
165165
166166
167167
168168
169169
170170
171171
172172
R1682.2K
R260 0
C184
0.1u
C183
0.1u
ShortShortShort pin1 pin1 pin1 pin1 pin1 and and and and pin2: JTAG chai chai chai chai chai chai chain notn notn notn notn notn not includingudingudingudingudingudingudingudingudingudingudinguding HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMC HSMCShort pin2 and and and and and pin3: JTAG JTAG JTAG JTAG chai chai chai chai chai chai chain incn incn incn incn including HSMg HSMg HSMg HSMg HSMg HSMg HSMg HSMg HSMg HSMg HSMg HSMCCCCC
HSMC_RX_D_n8X_D_n8X_D_n8X_D_n8X_D_n8X_D_n8HSMC_RX_D_n8X_D_n8X_D_n8X_D_n8X_D_n8X_D_n8HSMC_RHSMC_RHSMC_RHSMC_RHSMC_RX_D_p8X_D_p8X_D_p8X_D_p8X_D_p8X_D_p8HSMC_RX_D_p8X_D_p8X_D_p8X_D_p8X_D_p8X_D_p8
X_D_N6X_D_N6
HSMC_RX_D_N7HSMC_RX_D_N7X_D_P7X_D_P7
HSMC_RX_D_n9HSMC_RX_D_n9HSMC_RX_D_p9X_D_p9X_D_p9X_D_p9X_D_p9HSMC_RX_D_p9
HSMC_RX_D_n10X_D_n10HSMC_RX_D_p10HSMC_RX_D_p10
X_D_n11X_D_p11X_D_p11
SNT_nSNT_n
HSMC_THSMC_THSMC_THSMC_THSMC_TDOHSMC_THSMC_THSMC_T
HSMC_THSMC_THSMC_THSMC_THSMC_THSMC_THSMC_THSMC_TDIDIDIDIDIDIDIHSMC_THSMC_THSMC_THSMC_THSMC_THSMC_THSMC_TDI
HSMC_THSMC_THSMC_THSMC_THSMC_TDODODODODOHSMC_THSMC_THSMC_THSMC_TDODODO
HSMC_TMSHSMC_TE_HSMCE_HSMCE_HSMCE_HSMCE_HSMC_TMS_TMS_TMS_TMS_TMSE_HSMCE_HSMC_TMS_TMS_TMS_TMS_TMS
HSMC_THSMC_THSMC_THSMC_THSMC_TCKCKCKCKCKHSMC_THSMC_THSMC_THSMC_THSMC_TE_HSMCE_HSMC_TCK_TCK_TCK_TCK_TCKE_HSMCE_HSMC_TCK
HSMC_THSMC_THSMC_THSMC_THSMC_TDIDIHSMC_THSMC_THSMC_THSMC_THSMC_TDIDIE_HSMCE_HSMCE_HSMCE_HSMCE_HSMCE_HSMC_TDIE_HSMCE_HSMCE_HSMCE_HSMCE_HSMCE_HSMC_TDI
HSMC_THSMC_THSMC_THSMC_THSMC_TDODOHSMC_THSMC_THSMC_THSMC_TDOE_HSMCE_HSMCE_HSMCE_HSMCE_HSMCE_HSMC_TDO_TDO_TDO_TDO_TDO_TDOE_HSMCE_HSMCE_HSMC_TDO_TDO_TDO_TDO_TDO_TDO
HSMC_CLKIN_P1HSMC_CLKIN_P1HSMC_CLKIN_NLKIN_NLKIN_N111HSMC_CLKIN_NLKIN_NLKIN_N1HSMC_C
HSMC_THSMC_THSMC_THSMC_THSMC_TMSMSMSMSHSMC_THSMC_THSMC_THSMC_TMSHSMC_THSMC_THSMC_THSMC_TCKHSMC_THSMC_THSMC_THSMC_TCKHSMC_THSMC_THSMC_THSMC_THSMC_TDI
JTAG_TJTAG_TJTAG_TJTAG_TJTAG_TJTAG_TJTAG_TDOJTAG_TJTAG_TJTAG_TJTAG_TJTAG_TJTAG_T
VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3
VCC3P3VCC2P5VCC2P5VCC2P5
VCC3P3VCC3P3
CCIO HSMC_VCCIO
VCC12
JP3
HEADERHEADERHEADERHEADERHEADERHEADERHEADER 3 3 3 3 3
123
D40
LEDG
C171
0.1uDNI
R77R77R77R77R77R77R77R77R77R77R77R77R77R77R77
120120
C172C172C172C172C172C172
0.1u0.1u0.1uDNIDNIDNIDNIDNI R257R257R257R257R257R257R257R257R257 000
R258 0
VCCB
OE GNDOE GNDOE GND
TXS010TXS010TXS010TXS0104ERGYR4ERGYR4ERGYR4ERGYR4ERGYR4ERGYR4ERGYR4ERGYR
DNI
13121110101010
14
15
15
15TXS010TXS010TXS010
8 77
C241
22u
R259R259R259R259 0
102104106
165165
166166
167167
168168
R260R260R260R260R260R260R260R260R260R260R260 0
C184
0.1u
C183
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host
If the VBUS charge pumpcircuit is not to beused,CSWITCHA, CSWITCHB, andOTGVBUS can be leftunconnected.
SCL SDA
1
0 0
1
SCK/GPIO31 SDA/GPIO30 Boot Mode
0 0 HPI 0 1 HSS 1 0 SPI 1 1 I2C EPPROM
Default Setting: HPI mode
DP1
DM1
DP2
DM2
CS_n
INT
WR_nRD_n
ADDR1ADDR0
DM1DP1
OTG_DATA0OTG_DATA1OTG_DATA2OTG_DATA3OTG_DATA4OTG_DATA5OTG_DATA6OTG_DATA7
D8D9D10D11D12D13D14D15ADDR0ADDR1
WR_nRD_n
INT
SDASCL
CS_n
CS_n
OTG_ID
OTG_ID
DP2
OTG_DATA15OTG_DATA13OTG_DATA12OTG_DATA14OTG_DATA10OTG_DATA11OTG_DATA9OTG_DATA8
D15
D12D13
D14D10D11D9D8
DM2
SCL SDAUSB_12MHz
OTG_DATA[15..0]
OTG_WR_NOTG_RD_N
OTG_RST_N
OTG_CS_N
OTG_INT
OTG_ADDR1OTG_ADDR0
U_VCC5
U_VCC3P3
U_VCC3P3
U_VCC5
U_VCC5
U_VCC3P3
U_VCC3P3
U_VCC5
U_VCC5
U_VCC3P3
U_VCC3P3
VCC3P3
VCC5
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CY7C67200 D
DE2-115 Main Board
B
20 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CY7C67200 D
DE2-115 Main Board
B
20 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CY7C67200 D
DE2-115 Main Board
B
20 28Tuesday, April 16, 2013
R249 0
R252
10KDNI
C302
0.1u
R255 10K
C301
0.1u
TPD2E001DRLR
U29
VCC1
NC2
IO13
GND4
IO25
C298
0.1u
R251
10KDNI
C317
0.1u
C316
10u
TPD2E001DRLR
U28
VCC1
NC2
IO13
GND4
IO25
VBUS
D-
D+
GND
J17
USB A-TYPE
1234
5 6
C309
1u
R248 0
R256 10K
R25010K
C310
10u
VBUSGND
D-D+
J18
USB B-TYPE
4
32
1
5 6
R254
10K
C304
10u
U27
CY7C67200 48BGA
IRQ0/INT/GPIO_24H4
GN
DB
6V
CC
D6
VC
CH
2
GN
DA
1
XTALING3
XTALOUTG2
GN
DG
6
D1/GPIO_1A2D0/GPIO_0B2
RESERVEDA6
SCK/GPIO_31H3
BO
OS
TG
ND
E1
VSWITCHE2
BO
OS
TV
CC
F1
SDA/GPIO_30F3
CSWITCHAD1 CSWITCHBD2
OTGVBUSC1
OTGID/GPIO_29F4
DP2AD3 DM2AC2
AG
ND
B1
AV
CC
G1
DP1AE3 DM1AF2
nRESETA5
nRD/GPIO_23G4nWR/GPIO_22H5nCS/GPIO_21G5A1/GPIO_20H6A0/GPIO_19F5nSSI/D15/GPIO_15F6RTS/D14/GPIO_14E4RXD/D13/GPIO_13E5TXD/D12/GPIO_12E6MOSI/D11/GPIO_11D4SCK/D10/GPIO_10D5nSSI/D9/GPIO_9C6MISO/D8/GPIO_8C5TX/D7/GPIO_7B5RX/D6/GPIO_6B4D5/GPIO_5C4D4/GPIO_4B3D3/GPIO_3A3D2/GPIO_2C3
GN
DH
1
VC
CA
4
C300
0.1u
C299
0.1u
R247 0
C303
1u
C297
0.1u
C318
0.1u
RN37 22ohm123456789
10111213141516
RN38 22ohm123456789
10111213141516
C315
10u
R246 0
R253
10K
L16 BEAD
If OIf OIf OIf OIf OIf OIf OTGID is logi
CS_nCS_n
INT
WR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nRD_nRD_nRD_nRD_nRD_nRD_nRD_nRD_nRD_nRD_nRD_n
ADDRADDRADDRADDR1ADDRADDRADDRADDR00000
OTG_OTG_OTG_OTG_OTG_DATADATADATADATADATA00000OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_DATA1OTG_DATA1OTG_DATA2OTG_OTG_DATA3OTG_DATA3OTG_DATADATADATADATADATADATADATADATADATA444444444OTG_OTG_OTG_OTG_DATADATADATADATADATADATADATADATADATA5OTG_OTG_OTG_DATAOTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_DATADATADATA66OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_OTG_DATADATADATA7777777OTG_OTG_OTG_OTG_OTG_OTG_DATA777
D8D8D8D8D8D8D8D8D8D9D9D9D9D9D9D9D9D10D10D10D10D10D10D10D10D11D11D11D11D11D11D11D11D11D12D12D13D13D13D13D13D14D14D14D14D14D15ADDR000ADDRADDRADDRADDR1
WR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nWR_nRD_nRD_nRD_nRD_n
INT
SDASCL
CS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_n
CS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_nCS_n
OTG_OTG_OTG_OTG_OTG_OTG_OTG_IDOTG_OTG_OTG_OTG_OTG_ID
OTG_IDOTG_
OTG_OTG_OTG_OTG_OTG_DATAOTG_OTG_DATAOTG_OTG_DATA10OTG_OTG_DATA11OTG_DATAOTG_OTG_OTG_DATA9OTG_OTG_OTG_DATA9OTG_OTG_OTG_OTG_OTG_OTG_OTG_DATA8OTG_OTG_OTG_OTG_OTG_OTG_
D15
D12D12D12D12D12D12D12D12D12D12D13D13
D14D14D14D14D10D11D11D11D9D9D9D9D9D9D9D9D9D8
OTG_WR_NOTG_WR_NOTG_RD_NOTG_RD_NOTG_INTOTG_INT
OTG_ADDROTG_OTG_OTG_
R255
R256
67200 48BGA
IRQ0/INT/GPIO_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24O_24H4H4H4H4H4
GN
DB
6G
ND
GN
DG
ND
GN
DG
ND
A1
INXTALOUT
GN
DG
6G
6G
6G
6
D1/GPIO_1A2A2A2PIO_0B2
SCK/SCK/SCK/SCK/SCK/SCK/SCK/SCK/SCK/SCK/SCK/GPIOGPIOGPIO_31_31_31_31H3H3H3H3H3
BO
OS
TG
ND
TG
ND
TG
ND
TG
ND
E1
SDA/SDA/GPIOGPIOGPIOGPIO_30_30F3F3F3F3F3F3OTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGIOTGID/GPD/GPD/GPD/GPD/GPD/GPD/GPD/GPD/GPD/GPD/GPD/GPIO_2IO_29999F4F4F4F4F4
AG
ND
AG
ND
AG
ND
AG
ND
AG
ND
B1
nRD/GPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIO_23_23_23G4G4G4G4nWR/GPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIO_22_22H5H5H5H5H5H5nCS/GPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIO_21_21_21_21_21G5G5G5G5G5G5G5A1/GPIO_PIO_PIO_PIO_PIO_PIO_PIO_PIO_PIO_20202020H6H6H6H6H6H6A0/GPIO_1919191919191919F5F5F5nSSI/D15/GPIO_15F6RTS/D14/GPIO_14E4E4E4E4E4RXD/RXD/RXD/RXD/D13/GPIO_13E5E5E5E5E5TXD/TXD/TXD/TXD/D12/GPIO_12E6E6E6E6MOSIMOSIMOSIMOSIMOSI/D11/D11/D11/D11/GPIO_11D4D4D4D4D4SCK/SCK/SCK/SCK/D10/D10/D10/D10/GPIO_10D5nSSInSSInSSInSSI/D9//D9//D9//D9/GPIOGPIO_9C6MISOMISOMISOMISO/D8//D8//D8//D8//D8/GPIOGPIOGPIOGPIO_8C5TX/DTX/DTX/DTX/D7/GP7/GP7/GP7/GP7/GPIO_7IO_7IO_7IO_7B5RX/D6/GP6/GP6/GP6/GPIO_6IO_6IO_6IO_6B4D5/GD5/GPIO_PIO_PIO_PIO_5555C4C4D4/GPIO_PIO_PIO_PIO_4B3B3B3B3D3/GPIO_PIO_PIO_PIO_3333A3D2/GPIO_2C3C3C3C3
GN
DH
1H
1H
1H
1
RN37RN37RN37RN37RN37 22ohm1234455555677777888888999
10101011121314151515151515161616
RN38RN38RN38RN38RN38RN38RN38RN38RN38 22oh22oh22oh22oh22oh22oh22oh22oh22oh22oh22oh22oh22ohmmmmmmmmmm1222234566777789
1010101010101010101010101010111111111111111111111213131313131313141414141414151515151516
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2V/5A
3.3V/6A
POWER
VCC12
VCC1P2
VCC12
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V D
DE2-115 Main Board
B
27 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V D
DE2-115 Main Board
B
27 28Tuesday, April 16, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.2V & 3.3V D
DE2-115 Main Board
B
27 28Tuesday, April 16, 2013
R244
68.1K
D1
LEDB
C53
0.1u
C203
0.1u
C54
2.2u
C48
0.1u
REG3
LM3150MH
VIN2
RON7
SS6
EN3
SGND5
SGND9
FB
4
PG
ND
14
LG13
ILIM8
SW10
BST12
VCC1
HG11
EP
15
C202
390p
R146
10K
C191
0.47u
R157
1.78K
1V2
D9 SM340A
D8 SM340A
D11 SM340A
J8 DC_12V123
Q2
IRF7455PbF
5 6 7 8
123
4
R191
4.87K
L1 3.3uH
C60
22u
C61
15n
C30
10n
R145
9.53K
R39
34K
R180
2.4K
R118
120
R48
52.3K
C50
22u
R190
22K
Q3
IRF7455PbF
5 6 7 8
123
4
C29
330u
C74
2.2u
Q1
IRF7455PbF
5 6 7 8
123
4
C73
3.3nC72
330u
R245
75K
D10 SM340A
C49
2.2u
C51
15n
SW18
POWER SW
51
6
24
3
3V3
Q4
IRF7455PbF
5 6 7 8
123
4
C32
0.1u
REG2
LM3150MH
VIN2
RON7
SS6
EN3
SGND5
SGND9
FB
4
PG
ND
14
LG13
ILIM8
SW10
BST12
VCC1
HG11
EP
15
C170
1.2n
C175
0.47u
C31
47n
L3 3.3uH
68.1
C54C54C54C54C54C54C54C54C54C54C54C54C54C54
2.2u2.2u2.2u2.2u2.2u2.2u2.2u2.2u2.2u2.2u2.2u2.2u
REG3REG3REG3REG3REG3
LM31LM31LM31LM31LM31LM31LM31LM31LM31LM31LM31LM31LM31LM31LM3150MH50MH50MH50MH50MH
VIN222
RON7
SS6
ENENENENENENENENEN3
SGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGND5
SGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGNDSGND999
FB
FB
FB
444444
PG
ND
14
LGLGLGLGLGLG13
ILIM8888
SW101010
BST12121212
VCCVCCVCCVCCVCC111111
HGHGHGHGHGHGHGHGHG11111111111111
EP
15
15
15
C191C191C191C191C191C191C191C191C191C191
0.47u
R157
1.781.781.781.781.781.781.781.781.781.78KKKKKKKKKKK
C61
15n
R180R180R180R180R180R180R180R180R180R180R180R180
2.4K
R48
52.352.352.3KKKKKK
Q1Q1Q1Q1Q1
IRF7IRF7IRF7IRF7IRF7455P455P455P455P455PbF
5555 66 77 8
1222233333
44
C49C49C49C49C49
2.2u2.2u2.2u2.2u2.2u2.2u
Q4
IRF7
55 6 777777 8
4
LM31LM31LM31LM31LM31LM3150MH
FB
444
14
LGLGLGLG13
ILIM888
SW10
EP
15
C175C175C175C175C175C175
0.470.470.470.470.470.47u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ADJ/1A for Bank 4 I/O Voltage/1A
ADJ/1A for Bank 5 & 6 I/O Voltage/1A
1.8V/1A
2.5V/1A
JP6:1-2 : 1.5V3-4 : 1.8V5-6 : 2.5V7-8 : 3.3V
JP7:1-2 : 1.5V3-4 : 1.8V5-6 : 2.5V7-8 : 3.3V
5V/3A
VCC12
VCC3P3
VCC3P3
GPIO_VCCIO
HSMC_VCCIO
VCC3P3 VCC1P8
VCC3P3 VCC2P5
VCC3P3
GPIO_VCCIO
VCC3P3
HSMC_VCCIO
VCC5
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V D
DE2-115 Main Board
B
28 28Wednesday, April 17, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V D
DE2-115 Main Board
B
28 28Wednesday, April 17, 2013
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
POWER 1.8V & 2.5V & 5V D
DE2-115 Main Board
B
28 28Wednesday, April 17, 2013
R17910K
HSMC_VCCIO
FID8
MH8
C76
10u
GND2
R49
4.99K
MH6
GPIO_VCCIO
C69
0.1u
MH3
REG7
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
C75
10u
REG4
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
C77
10u
C68
10u
FID2
R17710K
R51
2.2K
FID3
MH7
GND3
C78
10u
MH2
1V8
C66
10u
R17810K
PH
R153 1K
FID7
R504.99K
R152 2.2K
FID6
JP7
HEADER 2X4
1 23 45 67 8
GND1
C67
0.1u
REG6
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
FID1
2V5
C65
0.1u
FID9
R41 10KDNI
MH5
C64
10u
R17610K
C63
0.1u
MH1
R534.99K
R151 4.99K
5V
MH4
FID10
C62
10u
REG1
TPS84620RUQR
VIN42
PVIN139
PVIN240
PVIN341
INH/UVLO18
INH/UVLO29
SS/TR6
RT/CLK35
VADJ43
ST
SE
L7
AG
ND
11
AG
ND
22
AG
ND
334
AG
ND
445
PG
ND
136
PG
ND
237
PG
ND
338
PWRGD33
SENSE+44
VOUT121
VOUT224
VOUT325
VOUT426
VOUT527
VOUT628
VOUT729
VOUT847
DNC13
DNC24
DNC35
DNC415
DNC516
DNC618
DN
C7
19
DN
C8
20
DN
C9
22
DN
C10
23
DN
C11
30
DN
C12
31
DN
C13
32
PH110
PH211
PH312
PH413
PH514
PH617
PH746
C55
100u
R42267
JP6
HEADER 2X4
1 23 45 67 8
R544.99K
R155 2.2K
FID5
R154 4.99K
R524.99K
R156 1K
REG5
LP38692MP-ADJ
VIN4
GN
D5
VEN1
VOUT3
ADJ2
C52
100u
FID4
R43165K
ADADADADADADADJ/1A1A1A1A f f f f forororor B B B Bank 5 & 6 I/O
1.8V/1A
2.5V/1A
7-8
VCC3P3
VCC1VCC1VCC1VCC1VCC1P8P8P8P8P8
VCC2P5P5P5
VCC3
GND2
R49
4.99K
REG7REG7REG7REG7
LP38692M692M692M692M692M692M692M692M692M692M692M692MP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADP-ADJ
VINVINVINVINVIN4
GN
DG
ND
GN
DG
ND
GN
D555
VEN1
VOUT33
ADJADJADJADJADJ2
P-ADJ
R17710K10K10K10K10K
C78
10u10u10u10u10u10u10u10u10u
1V8
R504.99K
JP7
13
GND1
REG6
LP38LP38LP38LP38LP38692M692M692M692M692MP-ADJ
VIN4
GN
DG
ND
GN
DG
ND
GN
D5
VENVENVEN1
VOUT
ADJ2
2V5
C65
R176R176R176R176R17610K10K10K
C63
0.1u
R534.99K
C62C62C62C62C62C62
10u
a0225345Typewritten Text*Replaced by LMZ31506H (Exact Equivalent)
a0225345Typewritten Text
a0225345Typewritten Text
IMPORTANT NOTICE FOR TI REFERENCE DESIGNS
Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems thatincorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remainsresponsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.TI reference designs have been created using standard laboratory conditions and engineering practices. TI has not conducted anytesting other than that specifically described in the published documentation for a particular reference design. TI may makecorrections, enhancements, improvements and other changes to its reference designs.Buyers are authorized to use TI reference designs with the TI component(s) identified in each particular reference design and to modify thereference design in the development of their end products. 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Testing and other quality control techniques for TI components are used to the extent TIdeems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is notnecessarily performed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.Reproduction of significant portions of TI information in TI data books, data sheets or reference designs is permissible only if reproduction iswithout alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable forsuch altered documentation. Information of third parties may be subject to additional restrictions.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards thatanticipate dangerous failures, monitor failures and their consequences, lessen the likelihood of dangerous failures and take appropriateremedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components inBuyer’s safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed an agreement specifically governing such use.Only those TI components that TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components thathave not been so designated is solely at Buyer's risk, and Buyer is solely responsible for compliance with all legal and regulatoryrequirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.IMPORTANT NOTICE
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