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DCVS Logic With Pass Gate (DCVSPG)VDD VDD
Q Q’
B’
B
A A’ AA’
0
1 2
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VDD-VT VDD
- Full Swing- Area, power reduction- Differential noise immunity
- Limited logical depth- Body effect
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Swing-Restored Pass Gate Logic (SRPL)
B’
B
A A’ AA’
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4
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VDD VDD
Q Q’
- Low stand-by power- High design margin, process tolerance- Less delay via sense-amp action
Push-Pull Pass Transistor Logic (PPL)
B’
B
A B A’B’
3
4
5
6
VDD1 2
OUT’ OUT
1 0
VDD-VTN VDD
+VTP 0
- Push-Pull action, no need for re-buffering- Low power- PFET drive dependence
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Double Pass-Transistor Logic (DPL)
VDD VDD GND GND
Q’ Q
A
A’
B
B’
B’ BA A’
- High Speed- Avoids buffer- Avoids VT drop- Redundant device structure
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Pulsed Static Logic (PS-CMOS)
VDD VDD
CLK
CLKCLK’
DATA ININPUT 1 RESET HIGH
INPUT2RESET HIGH
INPUT3RESET LOW
INPUT 4RESET LOW
RESET HIGH
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- High performance, skew transitions in a particular direction- Good dynamic noise immunity- Static circuit testability- Cumbersome monotonic stage operation- Complex clocking
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Multiple Output Domino (MODL)
A
B
C D
Pre-charge CLK
Q1 = A.B.(C+D)
Q2 = B.(C+D)
Q3 = (C+D)
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Clock Delayed Domino (CD Domino)
CLK
AQ
B
Delayed clock output
- Capability of inverting functions- Reduced chip clock overhead
- Extreme process sensitivity- Timing complexity- Additional clk propagated
with logic
Self Resetting Domino (SR CMOS)
A B DL L L
H
H
H
QL
Returns to resetting state
- Own appropriate clocking - Very high speed- Reduced clock over-head
- Low noise immunity - High process sensitivity - Additional device count- Difficult to time
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Dual Rail Domino
Differential
- Complete logic family
Q Q’
B B’
A A’
AND
PC
Cross-Coupled Domino
B B’
A A’
- Logically complete- Enhanced noise immunity- High performance
- Higher device count- Higher clock load- Higher power
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Latched Domino Structure
- Merging of a latch with the load devices of a dynamic logic element
- Result is fully latched- Need for O/P buffer eliminated - Tree does not need to complete its transition- Sense amplification and additional noise immunity
adds design reliability
Sample-Set Differential Logic (SSDL)
CLKCLK
VDD
CLK
Differential Evaluate Tree
CLK’
O/PO/P’
CLK = 0 : SampleCLK = 1 : Differential discharge arrested
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Enable/Disable CMOS Differential Logic (ECDL)
CLK
VDD
CLK
NFET Differential Evaluate Tree
CLK
Q’ Q
CKT disabled until clk transitions low
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