DC/DC LLC Reference Design Using the dsPIC DSCww1.microchip.com/downloads/cn/AppNotes/cn549772.pdf · 2010. 8. 2. · Series Resonant Converter • The series resonant converter can

AN1336DC/DC LLC Reference Design Using the dsPIC® DSC

Of the many DC/DC converter topologies availabletoday, a designer usually selects one of them as atrade-off between a number of contrasting needs. Mostoften, the important features that are pursued in thedesign process are efficiency, power density (i.e., sizeof the converter), and cost.

As presented in this application note, resonant convert-ers – LLC resonant converters in particular – have allof the features mentioned above, resulting in a com-pact and highly efficient design. Their ability to keep theoutput voltage regulated, over a very wide input voltagerange, contributes to reducing the overall system cost.

The relatively simple architecture of these parts permitsthe implementation of control and supervision/manage-ment tasks with a small pin count dsPIC DSC fromMicrochip. Sophisticated control is possible, using theDSP capabilities of dsPIC DSC devices.

RESONANT CONVERTERSResonant converters are included in a wide range ofconverters. The strategy of using one is to design ahighly efficient converter while eliminating a commondisadvantage of traditional implementations based onPulse-Width Modulation (PWM) – high switchinglosses. Many different solutions have been suggested,implemented, and tested in recent years, and many ofthem are now widely used in commercial products.

Resonant Converter TheoryThe basic idea behind a resonant converter is tooperate the MOSFETs with either a sinusoidal voltageor by running a sinusoidal current through it. Theswitching instant must be selected in proximity to thezero crossing of the sinusoidal voltage or current. Thedissipated power will then be very small.

An approach that can be used in most converters is todesign a “resonant-switch” converter. In this case,reactive elements (caps and inductors) are addedaround the switch in order to generate the mentionedsinusoidal voltage or current. Almost any topology cantake advantage of this approach; however, the resultingnetwork requires more components and the overallimprovements do not match the increased complexity.

RESONANT TOPOLOGIESThere are three main classes of resonant converters:

• Series converter (the load is connected in series with the tank)

• Parallel converter (the load is connected in parallel to the tank)

• Series-parallel converter (the tank circuit is a combination of the series and parallel classes of converters)

From a high-level perspective, the architecture of anysuch converter can be described, as shown in Figure 1.According to the selected type, the resonant tank boxwill contain one of the circuits shown in Figure 2.

FIGURE 1: HIGH-LEVEL RESONANT CONVERTER BLOCK DIAGRAM

Authors: Antonio Bersani, Alex Dumais and Sagar KhareMicrochip Technology Inc.

+_

SwitchingNetwork

ResonantTank RlVd Rectifier

2010 Microchip Technology Inc. DS01336A-page 1

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FIGURE 2: RESONANT TANK TYPES
MOSFET LossesBefore discussing the resonant converter categoriesin greater detail, the process that generates lossesduring MOSFET switching will be reviewed, usingthe simple circuit of Figure 3, where a half-bridge legis represented. Each switching element is alsorepresented with the anti-parallel diode, which couldbe an external diode or the component body diode.An input voltage (Vd) is applied and an output current(I0) is considered. The lower MOSFET is initiallyclosed and it is opened at time t0. The MOSFET isclosed again at time t1. The idealized waveforms forboth voltage and current are shown in Figure 4.Please note that the shaded areas consist of thepower losses that are repeated at each PWM cycle,which is termed “hard-switching”.

FIGURE 3: HALF-BRIDGE CIRCUIT

FIGURE 4: MOSFET SWITCHING LOSSES

Series Resonant Tank Parallel Resonant Tank LLC Resonant Tank

+

Vd

_

+Vt

-

itIo

t

Vt

it

Switching Power Losses

t0 t1

OFF transition ON transition

DS01336A-page 2 2010 Microchip Technology Inc.

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An additional problem related to high voltages andcurrent being switched in a short period of time is the(over)stress that MOSFETs have to withstand duringcommutation. Overvoltages and/or overcurrents caneasily be a by-product of fast commutation.
Figure 5 shows the voltage and current trajectories fora MOSFET; the axes are the voltage on the MOSFETand the current flowing through it. During the turn-ontransition, the voltage remains almost constant to itsmaximum value while the current is increasing; only atthe very end does the voltage drop to zero. Similar andreversed behavior can be observed at the turn-offtransition (see Figure 4). A first solution to thiscomponent overstressing has traditionally been theuse of Snubbers, which are circuits made up of R, C, Land diodes. Snubbers work well for component stress,but since they usually are dissipative, they do not helpin the attempt to preserve energy. Figure 6 shows thetrajectories using Snubbers.

Ultimately, the best solution is to try to design a switchcircuit, or operate the system in such a way that duringthe switching time, the MOSFET voltage and/or currentis as close to zero as possible. This constraint wouldmake the switching power losses (dissipated power)very small. Figure 7 shows the correspondingtrajectories.

FIGURE 5: MOSFET TRANSITION TRAJECTORIES

FIGURE 6: MOSFET TRANSITION TRAJECTORIES USING SNUBBERS

FIGURE 7: MOSFET TRANSITION TRAJECTORIES WITH SOFT-SWITCHING

SOATurn ON

Turn OFF

Vd Vt

it

Io

Vd Vt

it

Io

SOA

Turn ONTurn OFF

SOA

Vd Vt

it

Io


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LLC CONVERTERSA more attractive approach (in terms of circuit simplicityand overall efficiency), is the design of “load-resonant”converters. A typical circuit consists of a half-bridge orfull-bridge converter followed by a tank circuit to whichthe load can be connected (either in series or inparallel). The tank will force the voltage/current to besinusoidal so that, again, it is possible to synchronizethe switch operation to the zero crossing of the voltageor current. Switching losses are therefore “naturally”reduced.

A high-level description of how such converters work isas follows. The switching network, whose MOSFETsare driven by PWM signals, generates a square wavefor the resonant tank circuit. However, because of thepresence of the tank circuit, only fundamentalsinusoidal waveforms can be supported by the circuit.The output rectifier, in one of its multiple possibletopologies, is then used to rectify the sinusoidalwaveform and get the desired DC output voltage. Theresonant topology can then incorporate a transformeras the parallel inductance, permitting operation in agalvanically-isolated environment.

These converters are characterized by two operatingfrequencies:

1. the switching frequency, as imposed by the con-trol electronics (the frequency at which theMOSFETs are operated)

2. the natural resonant frequency of the tank

While the resonant frequency is fixed; as soonas the circuit components (capacitors, inductorsand/or transformers) are selected, the switchingfrequency can be dynamically changed.

This is how the power transfer is managed and theoutput voltage is controlled, versus load and inputvoltage changes. The relationship between theswitching and resonant frequency translates into avoltage gain, which is demonstrated in subsequentsections.

While the three resonant converters, discussedpreviously, share the same fundamental workingmethodology, there are some advantages anddisadvantages in using each of them.

One of the main things to consider when comparing thetopologies is how they behave during no loadconditions. One key characteristic of these convertersis that some current may be flowing in the convertereven at no load; this is due to the resonant nature of thecircuit. This current is normally called a “tank circulatingcurrent” and does not play an active role in the powertransfer from the input to the output. Therefore, onedesign goal will be to keep it as small as possible. Thiscurrent is also responsible for general low-efficiency atlow load, since they do not, or at least only weakly,depend on output load currents.

There are some differences in the three resonantconverter topologies: series, parallel, and series-parallel. The differences are apparent when theefficiencies and deficiencies are highlighted.

Series Resonant Converter• The series resonant converter can sustain an output

short circuit if the switching frequency is far away, either above or below the resonant frequency. This is because, at resonance, the circuit impedance is extremely low, which gives rise to a very high cur-rent, which can be so high that it could destroy the MOSFETS.

• One benefit is the ability of the series resonant converter to work at no load, since no current will be flowing in the resonant circuit, but it cannot regulate the output voltage.

• The efficiency of the series resonant converter is higher at partial load than at full load.

Parallel Resonant Converter• The parallel resonant converter is self-protected

against output short-circuit.• The parallel resonant converter can be destroyed

when operating in an open circuit, at a switching fre-quency that is close to the resonant frequency.

• The parallel resonant converter has a decreasing efficiency when the load resistance increases.


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LLC CONVERTER APPLICATIONSApplications in which the LLC converter is used cantake advantage of these two main features:

1. very low switching losses (high efficiency)2. the capability to control the output voltage at all

load and line conditions

In telecom applications, the LLC converter is widelyused as the DC/DC converter following a PFC in anAC-DC system. The typical PFC output voltage isapproximately 400V, and can be directly fed into theLLC converter.

One typical requirement of such systems is toguarantee the output voltage with the rated power for apredetermined amount of time (called holdup time,typically 20 ms) after the AC voltage is removed. Thereason for this is that the telecom equipment requiressome time to perform housekeeping functions beforeshutting down.

A typical situation is shown in Figure 8, where Vpfc, thePFC output voltage, is fed into the LLC converter andits output (Vo) is powering the system equipment. Intraditional systems, a big capacitor in the DC link isrequired to keep the voltage at the rated output duringthe holdup time. This directly impacts the system sizeand cost. The resonant converter with the ability ofregulating the output voltage versus a very wide inputvoltage range (80-100V is a reasonable range) willallow the big bulk capacitor to be replaced with asmaller one.

Another typical application of such converters is wheresmall size and reduced height are a premium. Here themain requirements are to have small units with a veryhigh efficiency, which again allows for removal of fansand a reduction or omission of heat sinks, therebyenabling the unit to fit into small space constraints. Forexample, flat panel televisions.

FIGURE 8: PFC OUTPUT VOLTAGE AND REQUESTED OUTPUT VOLTAGE FROM DC/DC CONVERTER

Vpfc 400 V

Vo

Holdup time

(20 ms)

Note: The system must keep the nominal output voltage for at least the hold-time.


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LLC REFERENCE DESIGNFigure 9 shows a high-level block diagram ofMicrochip’s LLC Resonant Converter ReferenceDesign. The design specifications are summarized inTable 1.

The switching circuit is implemented with a half-bridgetopology, so that the output voltage will swing between0V and Vd = 400 Vdc nominal. A full-bridge circuit wouldalso have been possible, but the half-bridge has beenselected for its simplicity and reduced number ofcomponents.

The resonant tank circuit is made up of a capacitor, aninductor, and the isolating transformer. The second“missing” inductor is implemented via the transformermagnetizing inductance. Note that sometimes even thefirst inductor may be “lumped” into the transformer. Thisconfiguration would reduce converter size, cost, andcomplexity. At the secondary side, a synchronousrectifier has been implemented to improve the overallsystem efficiency.

The selection of a switching frequency of 200 kHz isprimarily dictated by the requirement of using smallpassive components (including the transformer). Thecontrol loop implementation, although sophisticated,still leaves enough bandwidth to the dsPIC DSC toperform auxiliary tasks like fault monitoring,temperature monitoring, and communication.

The system is completely digital. The loop (voltageloop) is closed through the implementation of a PIDwithin the dsPIC DSC, which completely takes care ofall the system operations (including fault andtemperature monitoring).

The system requires two low voltage supplies: +12 Vfor the MOSFET drivers and a 3.3V for the dsPIC DSCand analog components. The auxiliary power supplycircuit is used at start-up (and when normal operationis restored after faults), deriving a 12V output from thehigh-voltage input rail. A high-efficiency buck converteris then used to derive from 12V the 3.3V required topower the controller. During normal operation, whenthe primary LLC converter is running, the 12V supplyfor the drivers is directly derived from the converteroutput voltage, which is also the input to the buckconverter. The auxiliary power supply circuit can beswitched ON and OFF. A series diode is used todecouple the two 12V supplies. Since one of the maindesign targets is high efficiency, specific care has beenused in the implementation of the auxiliary powersupply circuit to make its power consumption as low aspossible.

FIGURE 9: REFERENCE DESIGN HIGH-LEVEL BLOCK DIAGRAM

Input Filter Half-BridgeDC-AC Converter

Resonant Tank Secondary

Control Loop dsPIC® DSCAuxiliary Power

and Transformer Synchronous

Supply

Rectifier


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Table 1 provides the reference design specifications.
TABLE 1: MICROCHIP REFERENCE DESIGN SPECIFICATIONS

Table 2 lists the dsPIC resources used in the design.

TABLE 2: dsPIC RESOURCE USED (dsPIC33FJ16GS502)

Spec Value

Input Voltage Range 350 Vdc – 420 Vdc400 Vdc,nom

Output Voltage 12 VdcPower Rating 200WNominal Resonant Frequency

210 kHz

Nominal Switching Frequency

205 kHz

Efficiency 95% (target)

Resource Value

Program Memory 3.5 KbData Memory 650 bytesPWM 2 channelsADC 4 channelsComparators 1 channel


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LLC CIRCUIT ANALYSIS AND MODELFigure 10 shows the basic LLC model that will be usedto derive the equations describing the system behavior.Starting from the left side of the drawing, the followingstages can be observed:

1. DC Input

The voltage generator represents the inputvoltage, which normally is approximately 400 Vdc.

2. Switch Circuit

The switch network has been implemented as ahalf-bridge; note that the body (or external) anti-parallel diodes and the parasitic outputcapacitances of the MOSFETs are explicitlyshown, since they play an important role in the cir-cuit operation and performance and cannot beneglected.

3. Resonant Tank

This circuit is made of three components: a reso-nating capacitance (Cr), a resonating inductance(Lr) and the transformer magnetizing inductance(Lm). Cr, Lr, Lm are the three components that char-acterize the LLC converter. Note that in this topol-ogy the magnetizing inductance plays an activerole and is in fact a design parameter. The pres-ence of these reactive components generate tworesonating frequencies in the network, as will beexplained later.

4. Ideal Transformer

Since the magnetizing inductance is clearlyshown, we can replace the transformer with itsideal model. Note that this is not completely cor-rect, since we should also show the primary andsecondary leakage inductances. While this is trueand these inductance play an important role in thetransformer specs definition, they are currently notfundamental to determine the overall systembehavior and are therefore removed from themodel.

5. Rectifier

In the drawing a diode-based, full-wave rectifier isshown. A number of different topologies can beused: single diode rectifier, full wave, bridge recti-fier or even synchronous rectifier. The latter is thesolution used in the reference design. However, atthis point we are not interested in the implementa-tion details, so a full-wave rectifier is more thanadequate for computations.

6. Low-Pass Filter

This filter is implemented with a single capacitor(Co).

7. Load

The resistor Ro represents the output load.

FIGURE 10: LLC CIRCUIT COMPONENTS AND SECTIONS

+_Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

Co Ro

DC Input Switch Circuit Resonant Tank IdealTrans-

Rectifier Low-PassFilter

Load

Vin Vsw(t) Vrect(t) Vo

Q2 D2 C2

1 2 3 5 6 7

V2 +

Vo

_

4

former


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Looking at the different stages in the circuit, it is clearthat at interface 1 a DC voltage is present, at interface2 a (nominally) square waveform, at interface 3 asinusoidal waveform, and finally at interface 6 arectified sinusoidal waveform, which will give a DCvoltage. The circuit operation is quite complex and it isnot possible to directly obtain the system transferfunction using classical linear system analyticalmethods. The approach taken is to pay attention to thetank circuit. The transfer function of a tank circuit is bellshaped around the resonant frequency. As aconsequence, only a sinusoidal signal at that frequencywill be transferred, while all other frequencies(harmonics) will be attenuated.
The system was designed and the tank componentswere selected so that, nominally, the switchingfrequency of the MOSFETs equals the tank resonantfrequency. Therefore, if the tank circuit is “good”, it willonly allow sinusoidal waveforms to be “transferred” tothe output.

The two MOSFETS, Q1 and Q2, operate inComplimentary mode, with a fixed dead-time (to avoidshoot-through) with a (nominally fixed) 50% dutycycle. Voltage V2 will then equal Vdc when MOSFETQ1 is closed, and equals 0V when Q2 is closed.Therefore, the output of the switch circuit (vsw(t)) is asquare wave (50% ON time), in the range 0-VdcV.

In the following paragraphs, a system model equationset will be developed, allowing an easy relationshipbetween input and output voltages to be derived. Assuch, the development is based on the considerationthat only the voltage and currents at the fundamentalfrequency should be taken into consideration due to thepresence of the tank circuit.

In the computations that follow, some basicmathematics results are used. Essentially, the Fourierseries is widely used to analytically describe squarewaves. The reason for this is that it allows the analyticalform of any periodic signal to be written as the sum ofan infinite number of sine and/or cosine waveforms,whose frequencies equal the fundamental (frequencyof the square wave) and its harmonics (integermultiples).

We are only interested in square wave signals sincethis is what we get from the input switching circuit.Equation 1 shows the Fourier series of a squarewaveform of amplitude A.

EQUATION 1:

Switch Network ModelConsidering the conventions used in Figure 10, thevoltage at the output of the switch circuit is a squarewave, which is express by Equation 2.

EQUATION 2:

This voltage is the sum of a DC level (Vdc/2), which isblocked by the tank capacitor (Cr), and an infinitenumber of sinusoidal waves, whose fundamental iscomputed from Equation 2, with k = 1, as shown inEquation 3.

EQUATION 3:

The peak, average and rms values of this sinusoidalvoltage are shown in Equation 4.

EQUATION 4:

As mentioned earlier, the resonant tank, if correctlytuned to the switching frequency, will present a finiteimpedance to the fundamental frequency and aninfinite (in reality, very large) impedance to all otherharmonics. The result is that the tank circuit willexperience a sinusoidal current. Because of thereactive elements, there will be a phase shift betweenvoltage and current as shown in Figure 11.

)2sin(122

)(,...5,3,1

kftk

AAtsk

)2sin(122 ,...5,3,1

tkfk

VVtv swk

dcdc

sw

where,fsw is the switching frequency of the MOSFETs

)2sin(2)(1, tfVtv swdc

sw

dc

pkswVV 2

,1,

0,1, aveswV

dc

rmsswVV 2

,1,

where,sw = voltage at the output of the switching circuit1 = consideration of the fundamental term onlypk = peak square valueave = average square valuerms = root mean square value


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FIGURE 11: TANK CIRCUIT CURRENT
LAGGING VOLTAGE

Therefore, the resonant tank current can be expressedby Equation 5.

EQUATION 5:

The DC current drawn from the input voltage generator,when MOSFET Q1 is closed, can be computed as theaverage value, over one period, of the tank current.The results are shown in Equation 6.

EQUATION 6:

Equation 3, Equation 5 and Equation 6 allow us toreplace the “real” input circuit with the model ofFigure 12. The circuit at the left represents the input:the voltage is imposed from the generator (Vdc); thecurrent drawn from the source is, as seen, the average(DC) value of the tank current.

The section on the right represents the equivalentcircuit that drives the resonant tank, where onlysinusoidal signals at the fundamental frequency are ofinterest.

We can now also determine the average input power,as shown in Equation 7:

EQUATION 7:

FIGURE 12: INPUT SWITCHING CIRCUIT MODEL

Vsw,1

Isw,1

)2sin(,1,1, tfIi swpkttwhere,t = resonant tank1 = fundamental valuepk = peak value = phase delay between voltage and current

cos2cos1,1,,1, rmstpktdc III

cos2

2,1,, rmstdcavedc IVP

+

Vdc

_

it 1 It 1 pk 2fswt – sin=

vsw,1 t 2VDC

-------------- 2fsw t sin=

IDC2

-------It,1,rms cos=


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Resonant TankThe real transformer is replaced by its model, wherethe magnetizing inductance (Lm) is clearly expressed.Leakage inductance at the primary and secondary areinstead neglected (non-essential to this discussion). Inthe hypothesis previously explained of focusing only onsinusoidal waveforms at the fundamental frequency, itis possible to find the transfer function (H(s)) of theresonant tank circuit in Figure 13, where the outputcircuit has been replaced by an equivalent resistor (Re),whose value will be computed in the following section.
Considering Figure 14, the input impedance, Zin(s), canbe computed, as shown in Equation 8.

EQUATION 8:

The circuit transfer function can be easily computed ifwe realize that the circuit components can be lumpedinto a series impedance (Zs: Cr and Lr) and a parallelimpedance (Zp: Lm, transformer, output load). Thesedetailed computations are shown in Equation 9 throughEquation 11.

Respectively, Zs(s) and Zp(s) are the impedances of theseries and parallel branches, which are expanded inEquation 9 and Equation 10, which results in thecalculation shown in Equation 11.

EQUATION 9:

EQUATION 10:

EQUATION 11:

FIGURE 13: RESONANT TANK CIRCUIT AND ITS TRANSFER FUNCTION

Zin s Zs s Zp s +=

Zs s 1sCr-------- sLr+=

Zp s n2Re sLm=

merr

psin sLRnsLsC

sZsZsZ )(1)()()( 2

where, n2 is the transformer turns ratio, as shown inFigure 15.

CrLr

LmRe

Ideal Transformer

n : 1

Vsw,1 Vrect,1

TransferFunction


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FIGURE 14: RESONANT TANK WITH INPUT IMPEDANCE COMPUTATION
FIGURE 15: RESONANT TANK CIRCUIT AND ITS EQUIVALENT CIRCUIT

CrLr

Lm

Zin(s)Re

Ideal Transformer

n : 1

CrLr

Lm

Zin(s)

n2Re


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The circuit of Figure 13 can now be redrawn as inFigure 16.
FIGURE 16: RESONANT TANK CIRCUIT USED TO COMPUTE THE TRANSFER FUNCTION

Since, in the tank circuit, only the fundamentalsinusoidal waveform is of relevant amplitude (all othersare attenuated by the tank transfer function), it ispossible to define the transfer function at thefundamental frequency, as shown in Equation 12.

EQUATION 12:

In both cases, the subscript “1” refers to the fact thatonly the fundamental frequency component isconsidered. The factor (1/n) is due to the secondaryover primary voltage ratio, which is expressed inEquation 13.

EQUATION 13:

Rectifier ModelOnce again, at the transformer secondary, because ofthe tank circuit, we will have a sinusoidal current(irect(t)) flowing through the transformer itself. Suchcurrent will flow alternatively in the two diodes D3 andD4 according to its sign, as shown in Figure 17 andFigure 18.

When examining the circuit, it is clear that this currentis responsible for the voltage values at the transformersecondary. In fact, from Figure 17 and Figure 18, thefollowing can be observed:

If current is positive, D3 is conducting and vrect(t) = Vo

If current is negative, D4 is conducting and vrect(t) = -Vo

Zp

Zs

Vsw,1 Vrect,1

in

me

ps

p

rmssw

rmsrect

ZsLRn

nZZZ

VV

sH)(1)(

2

,1,

,1,

where,Vrect,1,rms = the rms value of the transformer

secondary side voltage.Vsw1,rms = the rms value of the voltage at the

input of the tank.

primaryondary vn

v 1sec


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FIGURE 17: SECONDARY CIRCUIT WHEN ir(t) > 0
FIGURE 18: SECONDARY CIRCUIT WHEN ir(t) < 0

Considering the Fourier series of this square wave,centered around 0V, its analytical equation can bewritten (at the rectifier input), as shown in Equation 14.

EQUATION 14:

The fundamental component is shown in Equation 15.

EQUATION 15:

The average and rms values of this voltage are shownin Equation 16.

EQUATION 16:

D3

D4

Co Ro

+

Vo

_

+

Vo,sw

_

+

Vrect

_

ir(t) > 0

ir(t)

D3

D4

Co Ro

+

Vo

_

_

Vo,sw

+

+

Vrect

_

ir(t) < 0

ir(t)

)2sin(14)(,..5,3,1

tkfk

Vtv swk

orect

Where,

(vsw(t)). is the phase lag relative to the input voltage,

)2sin(4)(1,

tfVtv sworect

o

pkrectVV 4

,1,

0,1, averectV

ormsrect VV

22,1,


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As shown in Figure 19, the sinusoidal current irect,1(t) atthe transformer output is rectified by the diodes, so thatits value after the diodes is that of equation17.
FIGURE 19: CURRENT AT THE RECTIFIER INPUT

EQUATION 17:

The rectifier input current can be expressed as shownin Equation 18 (only the fundamental frequency).

EQUATION 18:

While the rectifier output current is shown inEquation 19, the average value of such current isshown in Equation 20.

EQUATION 19:

EQUATION 20:

t

t

D3

D4

Co Ro

+

Vo

_

irect,1(t)

| irect,1(t) |

irect(t) = | irect,1(t) |irect(t)

)()( 1,,1, titi rectoutrect

)2sin()( ,1,1, tfIti swpkrectrect

)2sin(,1,,1, tfIi swpkrectoutrect

pkrectoaveoutrect III ,1,,,1,2

where,

Io is the average (DC) current flowing into the load(resistor Ro, as shown in Figure 20)


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Summarizing: at the secondary, a square voltage,whose fundamental term is in Equation 15, and asinusoidal current (Equation 18 through Equation 20)are present. The important point here is that these twosignals are in phase to each other, meaning they havethe same relationship between voltage and current in aresistor. Based on this, it is possible to replace therectifier operation with a resistor of proper value.
The equivalent resistor value can be computed fromEquation 16 and Equation 20 solved against Irect,1,pk,as shown in Equation 21.

EQUATION 21:

The rectifier model is shown in Figure 20.

FIGURE 20: RECTIFIER MODEL

Revrect ,1 t irect,1 t ---------------------

4Vo

--------- 2Io--------

82-----Ro== =

+

_

Re

+

Vo

_

Ro

irect ,1 t irect,1,pk 2fswt – sin= Io2---Irect,1 ,pk=

vrect,1 t 4---Vo 2fswt – sin=


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Converter ModelAt this point, all sections of the converter model ofFigure 10 have been identified and their transferfunction computed so that it is possible to determinethe overall converter transfer function.
The overall model, obtained by joining together theblock diagrams of Figure 12, Figure 13, Figure 14,Figure 15 and Figure 20, is illustrated in Figure 21.Since the circuit elements have been definedconsidering only fundamental frequency signals are ofimportance, the model is normally referred to as FirstHarmonic Approximation (FHA).

The overall I/O relationship, that is the output-to-inputvoltage ratio (these two voltages are DC values), canbe determined by Equation 22 and referring toFigure 21.

Equation 23 introduces the definition of the “voltageconversion ratio”. The results are shown inEquation 24.

As we will analyze in the section “Voltage ConversionRatio”, M(fsw) depends on a number of differentparameters.

FIGURE 21: OVERALL LLC CONVERTER MODEL

The overall I/O relationship, that is the output-to-inputvoltage ratio (these two voltages are DC values), canbe determined by Equation 22 and referring toFigure 21.

Equation 23 introduces the definition of the “voltageconversion ratio”. The results are shown inEquation 24.

As we will analyze in the section “Voltage ConversionRatio”, M(fsw) depends on a number of differentparameters.

EQUATION 22:

EQUATION 23: EQUATION 24:

Re

+

Vo

_

+

Vdc

_

Cr Lr

Lm

n : 1

H(s)

)(21

2

)(22

,1,

,1,

,1,

,1,sH

V

V

sHV

VV

VVV

VV

VV

dc

dc

o

o

dc

rmssw

rmssw

rmsrect

rmsrect

o

dc

o

)()( sHnfM sw nfM

VV sw

dc

o

2)(


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VOLTAGE CONVERSION RATIOBefore proceeding, a few relationships that will be usedgoing forward must be defined. The LLC circuit has tworesonant frequencies, one (fr) due to the presence of Lrand Cr (see Equation 25) and the second one (seeEquation 26) due to the additional presence of Lm.However, when speaking of resonant frequency, fr willalways be referred to from this point forward.

EQUATION 25:

The second resonant frequency is shown inEquation 26.

EQUATION 26:

It is useful to define a normalized frequency that is theratio of the current frequency (f) over the resonancefrequency (fr), which is shown in Equation 27.

EQUATION 27:

Going forward, all frequency values are considered tobe normalized frequencies.

In addition, it is convenient to define the following:Inductance ratio (see Equation 28), characteristicimpedance (see Equation 29), and the quality factor(see Equation 30).

EQUATION 28:

EQUATION 29:

EQUATION 30:

Using Equation 12 and Equation 23 it is possible tocompute the analytical expression of the voltagetransfer ratio. The results are shown in Equation 31.

EQUATION 31:

In other words, the transfer ratio is a complex functionof the normalized frequency and the tank componentvalues. Also, it is not possible to draw the M(fsw)function for the specific design until all of theparameters have been computed. However, it ispossible to consider the families of M curves that aregenerated when considering as single parameters and Q.

Figure 22 represents one such curve. In this plot, the frresonant frequency is clearly shown. The otherresonant frequency (fr2) is responsible for the highpeak that is present at the left side (low frequencies).Figure 23 plots the family of curves obtained withQ = 0.2 (fixed) and varying from 0.1 to 0.9 in 0.1steps. Figure 24 plots the curves for a fixed value of = 0.2 and varying the quality factor Q from 0.1 to 0.9;again, in steps of 0.1.

rrr CL

f2

1

rmrr CLL

f

2

12

rn f

ff

m

r

LL

rrr

ro CfC

LZ2

1

out

outo

e

o

VnIZ

RZQ 2

2

8

),()( , QfffM nsw


AN1336
FIGURE 22: VOLTAGE CONVERSION RATIO M(f)
FIGURE 23: VOLTAGE CONVERSION RATIO M(f) WITH AS A PARAMETER

0

0,5

1

1,5

2

2,5

3

3,5

1,00

E-0

1

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+00

1,26

E+00

1,59

E+00

2,00

E+00

2,52

E+00

3,17

E+00

3,99

E+00

5,02

E+00

6,32

E+00

7,96

E+00

Resonant Frequency

0

2

4

6

8

10

12

14

1,00

E-01

1,26

E-01

1,59

E-01

2,00

E-01

2,52

E-01

3,17

E-01

3,99

E-01

5,02

E-01

6,32

E-01

7,96

E-01

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

M @ L=0,1

M @ L=0,2

M @ L=0,3

M @ L=0,4

M @ L=0,5

M @ L=0,6

M @ L=0,7

M @ L=0,8

M @ L=0,9


AN1336
FIGURE 24: VOLTAGE CONVERSION RATIO M(f) WITH Q AS A PARAMETER
A couple of comments on these plots. It appears that as increases, the curves become more and more sharp,while increasing Q, the curves tend to flatten out.

The converter is designed so that it will operate atresonant frequency at the nominal input voltage.According to Equation 24, it maintains that ofEquation 32, which when solved, is shown inEquation 33.

EQUATION 32:

EQUATION 33:

Observing the curves in Figure 23 and Figure 24, afundamental property appears: in any case all curvesalways cross each other at the same pointcorresponding at fn = fr, that is at resonance; thevoltage conversion ratio at this point is 1 (with thesuggested turn ratio). This means that such a selection

of n will guarantee that at nominal conditions, thecorrect output voltage will be generated, independentlyon the specific M curve the system is currently on.

Figure 25 plots the circuit input impedance (Zin definedin Equation 11). In this figure, a portion of the plane hasbeen highlighted; it is the portion of the frequency axis(for f fn) where the input impedance presents apositive slope. Remembering that the transfer functionof an inductor has the same kind of behavior, we candetermine that the LLC circuit is seen by the inputcircuit and the sinusoidal input voltage waveform as aninductor. This is extremely important to enable theconverter to achieve very small (turn-on) switchinglosses, as shown in subsequent sections. On thecontrary, the slope of Zin to the far left of the figure isnegative, which means the system has a capacitivebehavior. This also means that a point exists, on the Zcurve, that defines the border between capacitive andinductive equivalent behavior.

It can be shown that the input impedance Zin, if acomplex function, results in Equation 34.

EQUATION 34:

0

0,5

1

1,5

2

2,5

3

3,51,

00E

-01

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

Qz@0,1Qz@0,2Qz@0,3Qz@0,4Qz@0,5Qz@0,6Qz@0,7Qz@0,8Qz@0,9

12)(,

, nomin

nomor V

VnfM

nomo

nomin

VV

n,

,

2

),,( QffZ nin


AN1336
FIGURE 25: INPUT IMPEDANCE
As for the voltage gain, it is thus possible to draw afamily of curves using and/or Q as parameters. Foreach curve, it is possible to determine a point where thebehavior of the converter changes from capacitive toinductive as described previously. All of these pointsmake up a locus, which is represented in Figure 26 bythe blue line. In the frequency range below theresonant frequency, that is for f < fn, the area to the rightof this curve (shaded regions in Figure 26) is where theconverter has inductive behavior. Obviously theoperating point must be in this area, for frequencieslower than the resonant frequency.

A second limit of the available operating area in the Mplane can be determined reasoning that having anegative Q has no meaning. Thus the lowest value thatQ can have is Q = 0. Again, a curve of the gain can bedrawn in such a situation. The available area is thenshown in Figure 27.

The intersection of the two possible areas is shown inFigure 28.

Two additional limits that can be determined, whichdepend on the minimum and maximum input voltage.Using Equation 31 with the two extreme voltages, thetwo following relationships are derived, as shown inEquation 35 and Equation 36, which are plotted inFigure 29.

EQUATION 35:

EQUATION 36:

Considering all of the limitations defined previously, thearea (for f < fn) highlighted in Figure 30 is available forthe converter operation.

|Zn|

1

10

100

1,00

E-01

1,26

E-01

1,59

E-01

2,00

E-01

2,52

E-01

3,17

E-01

3,99

E-01

5,02

E-01

6,32

E-01

7,96

E-01

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

max,min 2)(

in

o

VVnfM

min,max 2)(

in

o

VVnfM


AN1336
FIGURE 26: LIMIT BETWEEN THE CAPACITIVE AND INDUCTIVE REGIONS AND THE
ACCEPTABLE AREA BELOW RESONANCE

FIGURE 27: ACCEPTABLE AREA BELOW RESONANCE DELIMITED BY Q 0

0

0,5

1

1,5

2

2,5

3

3,5

1,00

E-0

1

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

0

0,5

1

1,5

2

2,5

3

3,5

1,00

E-0

1

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0


AN1336
FIGURE 28: AVAILABLE M PLANE AREA WHERE BEHAVIOR IS INDUCTIVE AND Q > 0
FIGURE 29: MINIMUM AND MAXIMUM ACCEPTABLE GAINS

0

0,5

1

1,5

2

2,5

3

3,51,

00E

-01

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

0

0,5

1

1,5

2

2,5

3

3,5

1,00

E-0

1

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

Mmax

Mmin


AN1336
FIGURE 30: OVERALL M PLANE ACCEPTABLE AREA
0

0,5

1

1,5

2

2,5

3

3,5

1,00

E-0

1

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

Mmax

Mmin


AN1336

OPERATION OF THE LLC CONVERTER

Zero Losses at MOSFET Turn-onBefore going into greater detail regarding the operationof the converter at, below, and above resonance, it isuseful to consider what happens to the tank circuitwhen a square voltage waveform is applied. Asexplained previously, this results in a sinusoidal currentwaveform. In general terms, there are two possiblesituations of the relative position in time of the currentversus the voltage waveform. If the current leads thevoltage the behavior corresponds to that of a capacitor.However, this is of no interest.

Instead, as stated above, we operate the system in anarea of its voltage conversion ratio M(f) such that itappears to be inductive to the tank input current: that is,the current lags the voltage. Figure 31 shows the circuitthat will be considered in this section, which is only theswitching section of the half-bridge. The tank current isdefined as positive if it exits the tank (midpoint betweenthe two capacitors). Again D1 and D2, C1 and C2 arethe equivalent lumped components of the system.

FIGURE 31: CIRCUIT USED TO INVESTIGATE MOSFET TURN-ON BEHAVIOR

Figure 32 shows the MOSFET gate waveforms and thetank current.

At time t0 the current is negative, and it enters thecircuit as shown in Figure 33. Suppose for a while thatthe switch has not yet been turned on. The incomingcurrent follows the indicated path through the upperdiode D1. This means that the voltage across theswitch is very close to zero. The switch can beoperated with very small losses. As a consequence,the switch can be operated at any instant in time withinthe interval t0 to t1: the losses will always be very small.

During the interval t1 to t2, switch Q1 is closed and thecurrent flows through it (Figure 34).

At time t2, Q1 is opened. The current is positive and caneasily flow through the lower diode D2 (providing thatthe lower switch is not immediately operated)(Figure 35). Again, the voltage across the lowerMOSFET will be close to zero and losslesscommutation is possible. In fact, as for Q1, the lowerswitch can be turned on at any time during this interval.the ideal turn-on of the MOSFET is when there is zerovoltage across the drain to the source of the MOSFET.

Then, in interval t3 to t4, the lower MOSFET isconducting, as shown in Figure 36.

+_Vdc

Q1 D1 C1

Q2 D2 C2


AN1336
FIGURE 32: VOLTAGE AND CURRENT WAVEFORMS
t0 t1 t2 t3 t4 t

Q1

Q2

Tank Current


AN1336
FIGURE 33: TIME INTERVAL t0 TO t1:
TANK CURRENT CAN FLOW THROUGH DIODE

FIGURE 34: TIME INTERVAL t1 TO t2: TANK CURRENT FLOWS THROUGH UPPER SWITCH

FIGURE 35: TIME INTERVAL t2 TO t3: TANK CURRENT CAN FLOW THROUGH DIODE

FIGURE 36: TIMER INTERVAL t3 TO t4: TANK CURRENT FLOWS THROUGH LOWER SWITCH

+_Vdc

Q1 D1 C1

Q2 D2 C2

it

+_Vdc

Q1 D1 C1

Q2 D2 C2

Vdc

+_Vdc

Q1 D1 C1

Q2 D2 C2

it

+_Vdc

Q1 C1

Q2 D2 C2

Vdc

D1


AN1336
Circuit Operation at ResonanceThis section describes the operation of the LLCconverter at resonance, which is when the MOSFETsare operated at the same frequency as the resonantfrequency, as set by the selected components. Refer tothe circuit diagrams in Figure 37 through Figure 42 andto the plot of the most important waveforms inFigure 43. Note that, for each MOSFET, the anti-parallel diode (body diode or external diode) and theparasitic C1 and C2 capacitances have been added.This is because they take an active part in the systembehavior. Also note that C1 (and C2) lump theMOSFET drain to source capacitance and any otherstray capacitance in the circuit. A last note concerns thesecondary side. In this discussion diodes are going tobe used as a rectifying circuit (while the referencedesign implements a synchronous rectifier) becausethis will clarify the circuit operation and will help indetermining the requirements to the secondarysynchronous MOSFET switching time.
In the following sections analysis will be extended toboth above resonance and below resonance.

Figure 43 shows the following signals:

• A: gate signal for upper MOSFET Q1• B: gate signal for lower MOSFET Q2• C: currents flowing in the primary side; there are

two components: the magnetizing current (dashed, red) and the tank current (solid line, black)

• D: drain to source voltage on upper MOSFET Q1; note that this is also the voltage across cap C1

• E: drain to source voltage on lower MOSFET Q2; note that this is also the voltage across cap C2

• F: secondary side current in diode D3• G: secondary side current in diode D4

Circuit operation is analyzed in adjacent time intervals.

In general terms the primary current is made up of twocomponents: the magnetizing current (im(t)) whichdoes not contribute to power transfer to the converteroutput and the tank current (it(t)) that is responsible forthe power transfer (Figure 37).

t < t0: (Figure 38) Q1 off; Q2 on; D3 off; D4 on

This is the starting condition for the analysis. Q2 isclosed and will be switched opened right at time t0. Thevoltage drop on the upper cap C1 is Vdc.

t0 < t < t1: (Figure 39) Q1 off; Q2 off (dead time);D3 off; D4 off

Since both switches are open, no energy is supplied byVdc to the circuit. The only current flowing into theprimary is the magnetizing current, which remainsconstant (im(t)) during this time interval. This currentsplits between the two MOSFET caps, discharging C1and charging C2. One key point here is that themagnetizing current must be big enough to completethe caps charge/discharge operations before the end ofthe dead time. The designer must select thecomponents and dead time duration to fulfill thisrequirement. At t1, the voltage on C2 will be slightlybigger than Vdc and the voltage on C1 will be slightlynegative, which will allow D1 to start conducting.

At the secondary both diodes D3 and D4 are open, andthe output cap Co supplies energy to the output tomaintain the voltage Vo.

t1 < t < t2 (Figure 40) Q1 offon; Q2 off;D3 offon; D4 off

As anticipated above, diode D1 starts conducting. Thevoltage drop on it is very close to zero. MOSFET Q1can be closed at any time during this interval: thevoltage drop on it is almost zero, so that the turn-onlosses are pretty close to zero. Zero Voltage Switching(ZVS) is obtained. While only D1 only is conducting, theprimary current is again the magnetizing current, whichdoes not participate in energy transfer. But as soon asQ1 is closed, the input generator Vdc supplies thepower to be transferred to the output. Note that duringthis time interval, the tank current is negative, meaningit flows into Vdc.

t2 < t < t3 (Figure 41) Q1 on; Q2 off; D3 on; D4 off

This is the first half period during which power transfertakes place. As can be seen from the waveform plots,both components of the primary current aresignificative. The magnetizing current is generated bythe secondary voltage (Vo) reflected back to theprimary. This voltage is directly across Lm, so that themagnetizing current is calculated, as shown inEquation 37, which shows a linear behavior.

EQUATION 37:

I in Figure 43 (waveform C), clarifies the amount ofcurrent that is effectively available for energy transfer.

The tank current is expressed by Equation 38.

EQUATION 38:

tLnVtiti

m

omm )()( 1

)2sin(2)( , tfIti rrmsPt


AN1336
Note that at resonance, at time t3, the tank currentexactly equals the magnetizing current. This, then, isthe current flowing into Q1 when it opens. This currentshould be as small as possible to have low turn offswitching losses. Unfortunately two conflictingrequirements on the magnetizing current are involved.The first one (see the interval t0 to t1 description)requires it to be large enough to charge/discharge theparasitic capacitances within the dead time duration.Because of Equation 37, this means having a smallvalue of Lm. The second one is to have im(t3) as smallas possible to reduce losses (which means a largevalue of Lm). Some kind of trade-off must be performedby the designer. One possible approach is to select arather large value of Lm giving preference to thefulfillment of the ZVS requirement.
t3 < t < t4: (Figure 42) Q1 off; Q2 off (dead time);D3 off; D4 off

The circuit behavior is complementary to the previousdead time interval. Again, the only current flowing intothe primary is the magnetizing current, which remainsessentially constant. This current splits to charge C1and at the same time discharge C2. During this period,the voltage vds1(t) grows to slightly above Vdc and at thesame time the voltage on C2 falls to slightly less than0V. In a symmetrical way compared to the previousdead time interval, this will enable D2 to startconducting.

The circuit operation from t4 to t7 is the reverse of thefirst half cycle.

A final note on Figure 43. Signals F and G representthe secondary current; its amplitude is showngraphically with the vertical blue lines.

FIGURE 37: LLC CIRCUIT WITH MAGNETIZING AND TANK CURRENTS SHOWN

+_Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

Co RoQ2 D2 C2

+

Vo

_

it

im

+

Vp

_

+

Vs1

_

+

Vs2

_


AN1336
FIGURE 38: LLC CIRCUIT AT TIME INTERVAL t < t0
FIGURE 39: LLC CIRCUIT AT TIME INTERVAL t0 TO t1

+_

Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

Co RoQ2 D2 C2

+

Vo

_

+

_

+

Vs2

_

+Vds1_

Vp

+_

Vdc

Q1 D1 C1

Cr Lr

D3

D4

RoQ2 D2 C2

+

Vo

_

+

Vp

_

+

Vs1

_

+

Vs2

_

+Vds1_

CoLm


AN1336

+_

Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

Co RoQ2 D2 C2

+

Vo

_

+

_

+

_

+

Vs2

_

Vs1

Vp

+_

Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

Co RoQ2 D2 C2

+

Vo

_

+

_

+

_

+

Vs2

_

+Vds2_

Vp

Vs1


AN1336
FIGURE 43: RELEVANT LLC WAVEFORMS

+_

Vdc

Q1 D1 C1

Cr Lr

Lm

D3

D4

RoQ2 D2 C2

+

Vo

_

+

Vp

_

+

Vs1

_

+

Vs2

_

+Vds1_

Co

Vdc

Vdc

t

t

t

t

t

t

t

A

B

C

D

E

F

G

I

Q1: Gate Drive

Q2: Gate Drive

it(t), im(t)

Vds1(t)

Vds2(t)

id3(t)

id4(t)

t0 t1 t2 t3 t4 t5 t6 t7


AN1336
Circuit Operation Below ResonanceCircuit operation below resonance is calculated byEquation 39.
EQUATION 39:

Essentially, the circuit behavior is similar to that atresonance. However, there are some significativedifferences that directly influence the secondary sideswitching behavior. Figure 44 shows the relevantwaveforms and should be compared to Figure 43.

Since the tank fundamental sine wave has a shorterperiod compared to the switching period, the tankcurrent will equal the magnetizing current before thehalf period ends. This is highlighted in Figure 44. Fromthat point on, the current flowing in the primary is themagnetizing current only.

It is important to note that when using diodes at thesecondary, they will stop conducting at the right time(as soon as the current goes to zero). However, in asynchronous implementation, diodes are replaced byMOSFETs and their gate must be driven correctly. Thedesigner must find a strategy to determine the exacttime when the secondary MOSFETs are to be turnedoff. A number of different techniques have been

developed, usually requiring some kind of indirectcurrent sensing (that is, for example, measuring thevoltage drop across the MOSFETs themselves).

Circuit Operation Above ResonanceCircuit operation above resonance is calculated byEquation 40.

EQUATION 40:

The circuit behavior is somehow reversed compared tothe operation below resonance. Refer to Figure 45.Since the resonant period is longer that the switchingperiod, at the end of the switching half period, the tankcurrent is higher than the magnetizing current. Duringthe dead time the tank current falls rapidly to the valuethat the magnetizing current has, so that a new halfcycle can start.It should be clear that above resonance thesynchronous switches can be turned on and off at thesame time as the primary switches. This makes theircontrol very easy.From the preceding discussion is should be clear thatthe secondary MOSFET’s control depends on therelative value of the switching and resonantfrequencies. The firmware manages this issue.

FIGURE 44: CIRCUIT BEHAVIOR BELOW RESONANCE

rswrsw TTff

rswrsw TTff

Q1: Gate Drive

Q2: Gate Drive

Vdc

t

t

t

t

t

A

B

C

D

E

t0 t1 t2 t3 t4 t5 t6

it(t), im(t)

id3(t)

id4(t)


AN1336
FIGURE 45: CIRCUIT BEHAVIOR ABOVE RESONANCE
Q1: Gate Drive

Q2: Gate Drive

t

t

t

t

t

A

B

C

D

E

Vdc

it(t), im(t)

id3(t)

id4(t)

t0 t1 t2 t3 t4 t5 t6


AN1336

SYNCHRONOUS RECTIFICATIONAs previously discussed, the secondary side has beendesigned using a synchronous rectifier, instead ofusing diodes. The reason for this choice has been toreduce conduction losses at the secondary. The powerdissipated on a diode has two contributions: the lossesdue to the forward resistance (Rf) and the losses due tothe diode forward voltage. Therefore, the total diodeloss can be computed, as shown in Equation 41.

EQUATION 41:

If the diode is replaced by a MOSFET acting as aswitch, the losses are depicted by Equation 42.

EQUATION 42:

The interesting thing is that in the LLC converter, thesecondary switches are always operated while thecurrent flowing through them is zero. Refer to Figure 43for curves G and H, and Figure 44 and Figure 45 forcurves D and E. As already stated previously, only at aswitching frequency below resonance could the optionexist to turn off the secondary switches with a non-zerocurrent. It is the responsibility of the designer to find thecorrect strategy to guarantee that such an event doesnot occur.

As far as the possible topology, the designer canchoose between some very common topologies:

• Full wave rectifier, diode bridge• Full wave rectifier, center tapped

The solution used in the reference design is the latter.Usually the center tap is connected to the secondaryground; however, in the reference design it has beenconnected to the positive output. The reason for this isthat, as can be seen in the schematic, such a topologyallows the sources of both MOSFETs to be connected

to ground. This makes the driver circuit much easier,since it is not required to have any kind of bootstrapcircuit. The traditional approach would have required abootstrap circuit since the n-channel MOSFET needs agate voltage higher than the source voltage to operate.However, when conducting, the source and drainvoltages would essentially be the same. Since in sucha situation the gate to source voltage (Vgs) cannot begreater than the threshold voltage (Vth), as theMOSFET would never operate properly.

The full-wave diode bridge is common in applicationsthat have a high output voltage and a low output current

REFERENCE DESIGN HARDWARE OVERVIEWThe LLC reference design can be logically divided intotwo sections: the converter itself and the auxiliarypower supply. The converter is then split into a primarysection and a secondary section; the isolation betweenthe two sections is obtained through the resonanttransformer. The dsPIC DSC, controlling all powertransfer and supervision operations, is located on thesecondary side. This enables easy implementation ofpower management communication and eases supplyand grounding connections. The nominal switchingfrequency (and thus resonant frequency) has beenselected at 200 kHz, to be a reasonable trade-offbetween high speed and small passive componentsfrom one side and the possibility to implementsophisticated control loops and auxiliary functions onthe other.

Figure 46 presents the high level block diagram of theLLC converter.

Figure 47 shows a high level representation of thecomplete circuit, where:

• high voltage connections are highlighted with black bold line

• the 12V tracks to supply power to the components are drawn in blue

• the 3.3 V track is drawn in green

A Schottky diode separates the 12V generated by theflyback circuit from the 12V generated by the LLCconverter.

2,,, rmsDFaveDFdiodeloss IRIVP

Where,

Vf is the diode forward voltage

Id,ave and Id,rms are respectively the average and rmsforward diode currents

Rf is the diode forward resistance (usually in therange of a few tens of mOhms)

switchingconductionMOSFETloss PPP ,

Where,Pconduction are the conduction losses, or in otherterms:

onDSrmsMOSFETconduction RIP ,,2

and Pswitching are the switching losses.


AN

1336

DS

01336A-page 36

©2010 M

icrochip Technology Inc.

Low-Pass Filter

Load

dsPIC33FJ16GS502

Driver

Temperature

I2C™

V output from the Auxiliary poweris only used during start-up. After-

he output voltage will supply the 12Vate drivers and the buck switcher.

Communication

FIGURE 46: HIGH-LEVEL LLC CONVERTER BLOCK DIAGRAM

DC Input(350 – 420V)

Half-Bridge ConverterLLC Resonant Tank

Secondary Synchronous Rectification

High-Voltage Isolation

Driver TX

Auxiliary PWR TX

Gate

Gate Driver

12V LM2651 Buck Switch

TX

Cr

Lr

Lm

3.3VNCP1012

Driver TX

CT

Op amp

Opto-

The 12supply ward, tto the g

coupler

© 2010 M

icrochip Technology Inc.D

S01336A

-page 37

AN

1336

FIG

® DSC

tchingulator

D

URE 47: HIGH-LEVEL LLC CONVERTER BLOCK DIAGRAM (D: MOSFET DRIVER; A: AMPLIFIER)

dsPIC

Tank

SynchMOSFET

SynchMOSFET

MOSFET

MOSFET

SwiReg

Flyback Converter(Auto-shutoff)

D

D

DA

AN1336
Half-Bridge MOSFETsThe operation of the two MOSFETs is designed toalternatively connect the tank circuit input to theinput high rail (400 Vdc nominal) and to ground.Positive dead time is inserted on each commutationedge to prevent shoot-through. With this operation,the half-bridge MOSFETs are not subjected to anyparticular turn-on stress. Since the maximum inputvoltage is defined as 450 Vdc, a safe selection ofthese parts would be choosing MOSFETs with abreakdown voltage in the range of 600-700 Vdc.
A gate to source resistor of 10 k is added to bothMOSFETs to prevent accidental MOSFET turn-on dueto noise. Series resistors are added to control the rateat which the MOSFETs turn ON or OFF.

As explained in previous sections, the current flowinginto the MOSFETs is the magnetizing current and thetank current. A rough evaluation of the tank current isdescribed in the following paragraphs.

The output power is 200W. Considering a converterefficiency of 95%, the resulting input power is shown inEquation 43.

EQUATION 43:

The maximum average input power is shown inEquation 44.

EQUATION 44:

Equation 45 shows the input current.

EQUATION 45:

Taking some margins we can set Ipk = 2 A.

Input capacitance CISS (or better total gate capacitance)is an important parameter for the definition of the driver:the larger the capacitance the more drive currentrequired to charge/discharge this capacitance. Seeadditional details in the “Hardware Drivers” section.

Output capacitance is of interest also, because asexplained earlier, this capacitance must be charged toVin or discharged to zero during dead time to achievezero voltage switching. Output capacitance is listed in

the MOSFETs data sheet as COSS; however this valueshould be increased to take care of the straycapacitance that should be lumped into it.

TABLE 3: INPUT MOSFET SUMMARY

Tank CircuitThree elements must be determined in the design ofthe tank circuit: Lm, Lr, Cr. There are a number ofequations that relate these values (refer to Equation 25to Equation 30) to each other and to the desiredconverter performances. Usually, the system has morevariables or parameters than equations, so thedesigner is forced to take some decisions based onexperience or common sense. This is the reason whya wide number of different techniques can be used inthe selection of the components.

One of them is to examine the plots of the voltage ratioM(fsw), consider the limitations and available areas inits plane that have been identified previously, andselect a suitable value of the and Q parameters.

EQUATION 46:

EQUATION 47:

EQUATION 48:

See Figure 48 for the two values (Mmin and Mmax)that have just been determined

WPP outin 21095./20095.0/

2max,

min,pk

inrmsrmsinI

VIVP

AV

WV

PIin

inpk 85.0

35021022

min,max,

Parameter Value

Breakdown voltage 650 V

Continuous current 9A @ 25°C

RDSon, max 385 mOhm

Input capacitance (CISS) 790 pF typical

Output capacitance (COSS) 38 pF typical

Total Gate Charge (Qg) 17 nC typical

667.16122

400

n

889.045012667.1622)(

max,min

in

o

VVnfM

143.135012667.1622)(

min,max

in

o

VVnfM


AN1336
FIGURE 48: VOLTAGE CONVERSION RATIO (M(f)) AND GAIN LIMITS IMPLEMENTED IN THE
REFERENCE DESIGN

In the implementation of the reference design, the and Q parameters have been selected as: = 0.25 andQ = 0.5.

The rationale behind the choice of such values is thatthe corresponding voltage gain plot supports therequired max gain also permitting some margin(around 10%).

Using equations Equation 29 and Equation 30, Cr canbe computed as:

EQUATION 49:

EQUATION 50:

EQUATION 51:

From the analysis of the plot in Figure 48, someadditional information can be derived. First, theminimum operating switching frequency is determinedby the intersection of the M(f) plot and the Mmax plot.The resulting value is 155 kHz.

Similarly, the maximum switching frequency isdetermined as the intersection of the M(f) plot and theMmin plot. The resulting value is 220 kHz.

Some additional notes on the implementation of Lm andLr. As already stated, they are both realized by thetransformer. In a real transformer the total magnetizinginductance is given by the sum of Lm and Lr. This canbe easily proved with two experimental tests. The firsttest consists of measuring the primary inductance withthe secondary open: in this case, the measure givesthe Lm + Lr value. The second test consists, again, ofmeasuring the primary inductance – this time with thesecondary short-circuited. The measured value is nowthe leakage inductance.

0

0,2

0,4

0,6

0,8

1

1,2

1,41,

00E

-01

1,26

E-0

1

1,59

E-0

1

2,00

E-0

1

2,52

E-0

1

3,17

E-0

1

3,99

E-0

1

5,02

E-0

1

6,32

E-0

1

7,96

E-0

1

1,00

E+0

0

1,26

E+0

0

1,59

E+0

0

2,00

E+0

0

2,52

E+0

0

3,17

E+0

0

3,99

E+0

0

5,02

E+0

0

6,32

E+0

0

7,96

E+0

0

Mmax

Mmin

CrIout

16frQn2Vout

------------------------------- 10nF= =

*For the reference design, a value of 9.4nF was selected.

*

Lr1

42fr2Cr

-------------------- 67H= =

LmLr----- 270H= =


AN1336
Figure 49 shows the model of a transformer, taking intoaccount the leakage inductance at the primary andsecondary, the winding resistance and the equivalentcore resistance; these two terms are useful indetermining the transformer losses. All secondaryrelated terms have been moved to the primary todetermine the relationship between these inductancevalues and the Lm and Lr inductance as needed by theresonant converter. In Figure 50, all inductances havebeen lumped together to simplify the model. The modelin Figure 53 is preferred, since Lr and Lm aremeasurable parameters.
• R1: primary winding resistance• Lli: primary winding leakage inductance• Lm: magnetizing inductance• Rm: resistance modeling core losses (equals vm

2/Rm)• L’l2: secondary winding leakage inductance

reflected to the primary. L’l2 = n2Ll2, with Ll2 being the secondary winding leakage inductance

• R’2: secondary winding resistance reflected to the primary, R’2 = n2 R2, with R2 being the secondary winding resistance

FIGURE 49: TRANSFORMER MODEL TAKING INTO ACCOUNT LEAKAGE INDUCTANCES AND RESISTANCES

FIGURE 50: TRANSFORMER MODEL TAKING INTO ACCOUNT INDUCTANCES ONLY

R1 Li1 R'2 L'i2

Lm vm Rm

n : 1

Lr

Lm

n : 1


AN1336
According to Figure 49, the total leakage inductance atthe primary terminals is calculated in Equation 52.
EQUATION 52:

Lpri can be easily determined, measuring the primaryinductance with the secondary windings open. Theresults are shown in Equation 53.

EQUATION 53:

The resonant inductance as shown in Equation 53 iscalculated in Equation 54.

EQUATION 54:

The results of these two calculations are shown inEquation 55.

EQUATION 55:

It is possible to define a gain of the transformer, asshown in Equation 56.

EQUATION 56:

Equation 57 shows the transformer winding ratio.

EQUATION 57:

The resulting transformer will then have 56 turns at theprimary and three at each secondary.

The transformer bobbin is ETD34 and the core materialis 3C90. The expected losses are approximately 2W.As the turns ratio is 18.667, there are three turns on thesecondary and 56 turns on the primary. Litz wire hasbeen used on the secondary (three parallel wires of 40gauge, 175 strands) as well as the primary (two parallelwires of 40 gauge 10 strands). The gap isapproximately 2 mm.

With this transformer an external inductor to boost theleakage inductance of the transformer may be needed.

In summary, the components values and parameterslimits are shown in Table 4.

TABLE 4: TANK CIRCUIT SUMMARY

Hardware DriversDrivers are required for the main switches because ofthe high voltage involved and the requiredcommutation speed.

A driver is selected according to its current sourcingcapability. The reason is that the gate of a MOSFETpresents a high capacitance value. This capacitancehas to be charged/discharged in a time that isessentially dependent on the rise and fall times of theMOSFET itself. Designers have to find a driver that iscapable of supplying all the required current to allowthe MOSFET to have a fast transition. However, whilea fast rise and fall time enables reducing switchinglosses, it will at the same time increase EMI and mayintroduce high frequency ringing due to lead and circuitinductances.

As soon as the rise/fall time have been defined, therequired peak current can be computed from the basicequation of a capacitor, as shown in Equation 58.

EQUATION 58:

22

1 lmlmrmpri LnLLLLLL

Lpri(measured) 330H=

Lr(measured) 62H=

Lm Lpri Lr 330H 62H 268H=–=–=

GtransformerLm Lr+

Lm------------------ 330H

268H----------------- 1.11= = =

n 16.667 1.11 18.5==

Parameter Value

Cr 9.4 nF

Lr 62 µH

Lm 268 µH

Q 0.42

Resonant Frequency 210 kHz

ICVTorT fallrise )(

Where,

V is the gate voltage

C is the gate capacitance


AN1336
The value of C is determined by the gate to sourcecapacitance (CGS) plus the gate to drain capacitance(CGD) due to Miller effect. So it is not correct to evaluateC as the CISS parameter that can be found in MOSFETdata sheet. Instead the value of C can be computedlooking at the total gate charge (Qg) which is anotherparameter in MOSFET data sheets and applying thesimple relation between charge and capacitance, asshown in Equation 59.
EQUATION 59:

This is the value of C that must be used in the previousequation.

The value of Qg is not a constant, obviously. It shouldnot be a surprise that Qg depends on the Vgs voltage.The MOSFET data sheet should have a graph likeFigure 51, where the effective Qg at the correct Vgs andVds value can be determined.

Two different resistors have been used at the driver’soutput to enable different paths for the current duringthe rising and falling edges. This changes the rise/falltimes of MOSFET.

The driver’s output signals are conveyed to the primaryside MOSFET through a couple of signal transformers.DC blocking capacitors are added to prevent saturationof the drive transformers. The capacitors remove theDC off set and at a 50% duty cycle produce a gatevoltage of ~6V.

Current TransformerA current transformer is used to acquire the currentflowing into the primary side. The knowledge of thisvalue, as explained, enables knowledge of thesecondary side current also. The selection of the CThas been challenging because of the requirement of4000V isolation. The turn ratio is 1:50.

Primary Voltage MeasurementThe primary side voltage is detected at the commonpoint of the two switches. A high voltage cap is used tocross the galvanic isolation barrier; at the secondaryside, a resistor voltage divider reduces the voltageamplitude within the dsPIC DSC analog voltage inputrange.

FIGURE 51: TYPICAL MOSFET TOTAL GATE CHARGE VS. Vgs

GS

gV

QC


AN1336
Synchronous RectifierThe output of the transformer is a sinusoidal waveform.A synchronous rectifier circuit is added to rectify thesinusoidal waveform to create a DC voltage. Thesynchronous rectifier is implemented with MOSFETswitches. As explained in a previous section, thecorrect choice of the instant in time when to turn-offthese MOSFETs enables (very) low switching losses.Conduction losses then remain as the main source ofpower consumption. This leads to the selection of verylow RDS,on MOSFETs.
The turn-on time is not an issue since the MOSFETsfollow the primary switched turn-on timing.

TABLE 5: SYNCH RECTIFIER MOSFETs

Output FilterThe inductor is 4.7 µH with a DCR of 1.5 mOhms. Thecapacitor is 330 µF.

Current AmplifierA non-inverting op amp with a gain of 2 is used to bufferand amplify the primary current signal acquired by thecurrent transformer. Diodes on the input create a fullwave rectifier circuit; diodes are also added on theoutput to protect the circuit and following stages fromhigh voltage transients.

Auxiliary Power Supply - FlybackDuring the normal system operation, the controller,analog parts and drivers derive their supply from themain converter output; a stand-alone high efficiencysynchronous switching regulator chip is used to derivethe 3.3V from the converter 12V nominal output.

There are, however, two situations where the 12Voutput voltage is not available, that is at start-up and ifany faults occur, with the consequence of a fast PWMshutdown operated by the dsPIC DSC to preventserious damages. The auxiliary power supply mustcope with these problems.

An additional fundamental requirement is to minimizethe power consumption of the flyback converter. Thishad two consequences:

• Selection of the high efficiency 3.3V regulator• Implementation of a circuit that is capable of auto-

shut off when the main converter is up and running

Figure 52 shows details of the flyback circuit. Thedescription in the sections that follow refer to this figure.

Parameter Value

Breakdown voltage 30V

Continuous current 85A

RDSon, max 5.8 mOhm

Input capacitance (CISS) 2150 pF

Output capacitance (COSS) 480 pF

Total Gate Charge (Qg) 15 nC typical


AN

1336

DS

01336A-page 44

©2010 M

icrochip Technology Inc.

D22+12V

L2

22uH

K

R

100uF/16VC32

6V

+12V

FIGURE 52: FLYBACK CIRCUIT

C2447uF/16V

TP1

D23

D18

GND_DIG

330KR23

3.3nFC41 R53

100K/0.5W

HSR312

U9

TX3

GND_DIG

D17

AUX

C2347uF/16V

TP2

2.2KR26

49.9RR25

GND_DIG GND_DIG

330KR24

3

2

1

4

NDT3055Q7

2

1

3

4U7

SFH617A_DIP8

TP3

470uF/16VC25

R454.7

R54180

3 GND 2GND

1 VCC

4 FB

8GND

5DRAIN

U10

NCP1012-DIP7

470uF/1C26

Automatic Shut-off

Controller

Snubber

FlybackTransformer

Feedback Network

Output Filters

GND_HV

GND_HV

GND_HV

GND_HV

GND_HV

GND_HV

GND_HV

VIN+

AN1336
CONTROLLERAn NCP1012 device from ON Semiconductor® hasbeen selected for the following reasons:
• Monolithic chip (almost everything needed is embedded in it)

• Can withstand high input voltages (up to 700 Vdc)• Can derive its own power supply from this high

voltage rail• Fixed frequency controller (100 kHz has been

selected), implementing current-mode control• Permits an easy implementation of the control

loop, through the connection of its feedback input pin to an optocoupler, driven by the output voltage

• Can be easily switched OFF• Implements internal protection strategies

(short-circuit protection)

FLYBACK TRANSFORMERThe transformer design specifications derive from thepower rating and the controller requirements.

The turns ratio is computed considering the flybackbehavior at the instant in time when the flybackMOSFET opens. Applying Kirchoff’s voltage law at theflyback primary side, the voltage on the switch can becomputed as the sum of the input voltage (Vin), theoutput voltage (nVo) reflected back to the primary andsome additional headroom (Vx) which takes inconsideration the voltage overshoot that appears attransients. This overshoot voltage, if not taken care of,is destructive. To control it a snubber circuit is added.The total voltage on the switch, as explained previouslyis shown in Equation 60.

EQUATION 60:

To prevent problems, this voltage must of course beless than the component rated breakdown voltage(700V). Solving this relationship on (n), the turn ratio isdetermined to be n = 15.

The transformer inductance value is selected in orderto keep the system in discontinuous mode operation;this is required by the chip. According to the ONSemiconductor device data sheet, the inductance canbe computed as shown in Equation 61.

EQUATION 61:

For the transformer design, a number of considerationsmust be met:

• Core material: essentially depends on the switching frequency. Manufacturers provide plots that relate the material performances and fre-quency. These plots allow the selection of the cor-rect material. Manufacturers very often also provide some additional guidance on the best fit-ting material, according to the kind of application the transformer is intended for. The material used in the flyback transformer is N87 (from the EPCOS Ferrites and Accessories catalog).

• Core size: essentially depends on the core losses and core temperature increase the designer can accept, in relation to the overall design economy. A standard core (E20/16/6 from EPCOS) has been chosen.

• Number of turns: Although very often the mag-netics in a flyback converter is called an “induc-tor”, in reality it is manufactured as a transformer. This means that the data we currently have (inductance value and turn ratio) are not enough to fully define the component.To proceed further, a core with a standard center gap has been selected in order to use an off-the-shelf part. Manufacturer can produce customer specific gaps, but of course this increases the cost and lead time of transformers. The introduction of a gap changes the transformer characteristics. In order to make things easy, manufacturers supply a parameter (AL) that tells how many nanoHenrys are obtained on the specific core plus gap for a one turn winding. In this design, based on the particular device available from the manufacturer, AL is close to 100 nH, so that the primary number of turns is computed as 272. From this value, and the turn ratio computed above, we also have the num-ber of secondary turns (19).

xoinsw kVnVVV

Where, k is some value greater than 1

uHIfVDL

sw

in 6.7max

minmax

Where,

Dmax = 0.5 is the max allowable duty cycleVinmin is the minimum input voltage (340V) fsw is the chip switching frequencyImax is max peak current that is requested from thechip (using some guard band, this has been set at225 mA).


AN1336
• Wire size: Having selected the core size and the
gap value (from the EPCOS data sheet, 5 10-2 cm), the maximum magnetic flux B in the core can be computed as a function of the primary turn ratio and max allowable current, resulting in Bmax = 70 mT. The transformer manufacturer allows then, usually with a diagram, to determine the core losses corresponding to such a flux intensity.The selection of the wires is based on the assump-tion that the specific (per volume unit) core losses equal the specific losses in wires. This is a com-promise that usually allows to keep the trans-former temperature increase within reasonable values. Since the wire specific losses are function of the wire size, it should be clear that this allows to determine the AWG for both primary (AWG = 33) and secondary wires (AWG = 20).

SNUBBERAs already introduced previously, the snubber at theprimary is needed to control (limit) the voltageovershoots that appear during switching, in such a wayto guarantee that the total voltage on the MOSFET isalways below its breakdown value. Here a maxtolerable overshoot (on top of the input voltage plusoutput voltage reflected back to the primary) of about60V has been computed (with some additionalheadroom). The additional voltage is due to theleakage inductance in series with the transformerprimary.

Knowledge (or at least estimation) of the transformerleakage inductance allows to proceed withcomputations. The snubber operates in such a way thatwhen the voltage increases too much, getting close tothe switch breakdown voltage, the energy stored in theleakage inductance (that generates the voltageincrease) is dissipated, through the diode, into thesnubber resistors

FEEDBACK NETWORKThe flyback output needs to be regulated at 12V. Azener diode with Vz = 11V does not allow any current toflow in the feedback path until the output grows above11V. From that point on, the zener current is set with thetwo resistors to be around 300 µA. Using Kirchoff’scurrent and voltage laws and the selected optocouplerinput characteristic, it is possible to determine the tworesistor values (R1 = 4.7 kOhm, R2 = 280 Ohm).

The optocoupler output can be considered a currentgenerator whose value is proportional to the converteroutput voltage. This current develops a voltage drop ona resistor internal to the ON Semiconductor; thisvoltage feedback is finally detected and used internallyto the On Semiconductor chip, to control the peakcurrent value flowing into the flyback primary winding.

AUTO SHUT-OFF CIRCUITAs already stated, one of the main design targets of theauxiliary power circuit is to reduce its power when noteffectively needed, that is when the main (LLC)converter is up and running. The power consumed bythe auxiliary circuit during this time is completelywasted and can be a relatively important percentage ofthe overall power. In this case, it would beapproximately 1 to 1.5% of the rated system power.

To solve this problem, the aux power supply circuit hasbeen designed in such a way that, after a preset timefrom when the system is powered-up, it turns off,shorting the ON chip feedback input to ground. Thedelay time (during which the flyback circuit is running)may be set via the two resistors (R23 and R24). Thenominal value of this delay, with the selected resistors,is approximately two seconds.

While this solves the problem of shutting off the flybackconverter during normal converter operation, it poses aserious problem in the event of a fault. In this case, thedsPIC DSC shuts down the PWM controlling the LLCconverter, the output voltage drops to zero and,consequently, the dsPIC DSC is not powered anymore. The system shuts down (completely) but wouldnot be capable to start again.

To solve this problem some kind of feedback from thedsPIC DSC device is needed. The dsPIC DSC mustessentially “communicate” to the auxiliary powersupply circuit that it is going to shut down the LLCconverter. The AUX signal is used for this. In the eventof a fault, while managing the fault itself, the dsPICDSC drives high the AUX pin. This signal, crossing theisolation barrier via an optocoupler, restarts the flybackcontroller operation, discharging capacitor C24.

As a result, the dsPIC DSC is powered and active evenif the LLC converter, for any reason, cannot be startedagain. One important possible advantage from this isthat the dsPIC DSC can, for example, communicate thefault condition and the impossibility of restoring theconverter functionality to the outside world.


AN1336
Auxiliary Power Supply – Synchronous Buck ConverterReferring to Figure 53, this circuit is intended to supplythe dsPIC DSC with a 3.3V DC voltage, derived fromthe 12V input (either from the flyback or the main LLCconverter). The LM2651 device from NationalSemiconductor™ has been selected because of itshigh efficiency. The measured efficiency isapproximately 89% at 75% of the nominal current. Theswitching frequency is 300 kHz, which allows the use ofsmall passive components. The circuit design is prettystraight forward, since only a few components must beadded.
Some attention must be paid to the design of thecompensation circuit. In fact, the chip presents an openloop transfer function having two poles: one (fp1) at low

frequency, the second one (fp2) at a high frequency andone zero (fz) in between. The compensation network,consisting in R21, C17 and C18, connected to theCOMP pin of the chip, adds two poles (fcp1, fcp2) andone zero (fcz) so that:

• the first compensation pole (fcp1) is at very low fre-quency, about 1/10 of the low frequency chip pole (fcp2)

• the compensation zero has the same frequency of the first chip pole (fp1)

• the second compensation pole (fcp2) is at the same frequency of the chip zero (fz).

The overall result is a loop transfer function witha -20 dB per decade from very low to very highfrequencies. Such a function guarantees a stablecircuit.

FIGURE 53: AUXILIARY HIGH-EFFICIENCY BUCK REGULATOR

4.7nFC16

0.1uFC15

TP4

R4110K

GND_DIG

C2033uF

+3.3V_DIG

68uFC37

GND_DIG

47nFC18

GND_DIGL1

150uH

9.31KR21

22uFC14

GND_DIG

GND_ANA

0RR46

D21

16.5KR22

+3.3V_ANA0.1uFC19

GND_DIG GND_DIG

GND_DIG

1000pFC17

L3

10uH0.1uFC38

3VI

N15

PGN

D

12AG

ND

10 COMP

6VCB8 SD(SS)

11 NC 1SW2SW

5VI

N

7AV

IN

16PG

ND 9FB

13AG

ND

4VI

N14

PGN

D

U4

LM2651-3.3

+12V

+ +

+


AN1336

REFERENCE DESIGN FIRMWARE OVERVIEWFigure 54 introduces the fundamental firmware blockdiagram of the LLC Converter Reference Design.

FIGURE 54: HIGH-LEVEL FIRMWARE BLOCK DIAGRAM

Initialization

System Clock IO Ports

PWMAnalog-to-Digital Converter

Comparators

Soft Start Routine

Fault Active?Main Loop

(Fault Check) Fault Loop

InterruptRoutines

Yes

No


AN1336
InitializationIn this section of the code, all of the main systemoperations and peripherals are initialized.
Since the LLC half-bridge converter is frequencycontrolled, an external oscillator is used to provide theclock to the system in order to obtain a small toleranceover the entire operating temperature range. Theexternal 7.37 MHz crystal is supplied to the internaloscillator circuit; from this the system PLL and theauxiliary PLL clocks are derived for the system and thePWM and ADC peripherals respectively. The auxiliaryclock has an internal 16x PLL, which produces a clockfrequency of 118 MHz for the PWM and ADCPeripherals. The system clock PLL provides a clockfrequency of 40 MHz.

The LLC Reference Design uses two PWM channels.One channel drives the primary half-bridge MOSFETs,and the other channel the secondary synchronousrectifier MOSFETs.

The Table 6 summarizes the initial modes of operationof the two PWM channels.

TABLE 6: INITIAL PWM MODES

The ADC channels are used as summarized byTable 7.

TABLE 7: ADC CHANNELS

Comparator 1 shares the same input pin as ADCchannel 0. This means that the output current is alsomonitored with the comparator to determineovercurrent events.

Before starting the system operation, a check isperformed on the input voltage to check that its value iswithin the specified range.

Soft-Start RoutineThe unit, when powered up, operates at a at very highfrequency (around 300 kHz). The duty cycle is manu-ally controlled to ramp-up the converter’s output volt-age from 0V to approximately 10V, depending on theinput voltage. From this point on, the duty is fixed at50% minus dead time and the frequency is insteadreduced down to the nominal value (205 kHz @ 400Vinput).

Operating Mode

Primary PWMPush-pull

Secondary PWMPush-pull

Dead Time Disabled (included into the duty cycle value)

Disabled (included into the duty cycle value)

Duty 1/2 the period – dead time value

1/2 the period – dead time value

ADC Trigger

Generated every fourth PWM period

Generated every fourth PWM period

ADC Channel Signal Comment

AN0 IOUT_FB The current transformer outputs, connected in series to the main trans-former, are filtered and amplified by U2.

AN1 VOUT_FB A resistor divider network is used to sense the output voltage.

AN2 VIN_FB It is measured at the sec-ondary, using a high volt-age capacitor to cross the isolation barrier.

AN3 TEMP_FB Temperature is detected using the MCHP9700 (U8) temperature sensor. The sensor is located close to the output synch MOSFETs.


AN1336
Interrupts ManagementA number of interrupts are serviced:
• ADC Pair 0 interrupt

The output voltage is acquired and is passed to theroutine that implements the PI control. The outputof the PI processing is the new frequency value, or,more precisely, is the value of the PTPER register.During normal operation the updated frequencyvalue is checked to be within specified limits.The output synchronous rectifier PWM channel isalso updated, keeping into consideration the factthat the operating frequency is higher or lower thanthe resonant frequency.During soft start, the system is operated at fixedfrequency, and the PI compensator is disabled;however, the output voltage is still monitored bythe ADC. The tank current will also be measured inthis ADC interrupt.

• ADC Pair 1 interrupt

This interrupt is used to acquire the input voltageand for temperature sensing.

• Timer 1 interrupt

This interrupt is used to compute delays. The timerinterrupt occurs every 100 µs.

• Comparator 1 interrupt

This interrupt is used to detect overcurrent events(faults).

Fault ManagementA number of different signals originating faults areconsidered. One of the main problems in managingfaults is to avoid stopping the operation of the unitimmediately, as soon as a fault signal is received. Thereason for this is to avoid having a fast response topossible glitches and noise.

Fault condition is continuously tested in the main loop.In effect, this is the only operation which is performed(in background) by the main code.

Each fault signal is tested a number of times, a counteris incremented at each cycle if the fault is alwayspresent and only when the counter has reached somespecific value, the firmware considers that a real faultcondition has occurred. See Table 8 for details. Assoon as the system enters a fault status, the fault LEDwill be switched on and off a number of times thatcorresponds to the fault status; this provides visualrepresentation of which fault occurred.

TABLE 8: FAULT STATUS

Fault EventCounter Value to Start Fault

Status

LED Number of ON/OFF

Cycles

Input Undervoltage

250 1

Input Overvoltage

250 1

Overcurrent (Comparator)

— 2

Overcurrent (ADC)

250 2

Output Overvoltage

250 3

Output Undervoltage

250 4

Temperature 250 5Soft-start — 6


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APPENDIX A: SOURCE CODE

All of the software covered in this application note isavailable as a single WinZip® archive file. The archivemay be downloaded from the Microchip corporate website at: www.microchip.com

Software License AgreementThe software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, theCompany’s customer, for use solely and exclusively with products manufactured by the Company.The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civilliability for the breach of the terms and conditions of this license.THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATU-TORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU-LAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FORSPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.


http://www.microchip.com

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APPENDIX B: ELECTRICAL TEST RESULTS AND OPERATIONAL WAVEFORMS

This appendix provides information on the test resultsfor the 200W LLC Resonant Converter ReferenceDesign, as well as a few operational waveforms.

The following equipment was used to test the LLCResonant Converter:

• DC source > 450V, 3A• Electronic DC load > 12V, 20A• Four-channel oscilloscope (100 MHz or higher)• High-bandwidth current probes and differential

probes• 6 half digit multimeters• Efficiency boards (only for measuring efficiency)

B.1 SOFT-START AND OVERSHOOTThe LLC Resonant Converter implements a duty cycle/frequency controlled soft-start routine to ramp the out-put voltage up to 12V, thereby eliminating in-rush cur-rent and output voltage overshoot at start-up.

At start-up, the switching frequency is set to 300 kHz toprovide minimal gain from the resonant tank. The dutycycle is manually controlled to bring the output voltageup to approximately 10V depending on the input volt-age. Afterward, the switching frequency is reduced untilthe output voltage is close to the desired reference volt-age (12V). From this point on, the frequency is con-trolled using a PI compensator; however, in order toeliminate any overshoot the integral error is calculatedproviding history to the control loop.

Figure B-1 and Figure B-2 demonstrate the converter’ssoft-start with and without load.

FIGURE B-1: NO LOAD SOFT-START, INPUT VOLTAGE: ~400 VDC


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FIGURE B-2: FULL LOAD SOFT-START, INPUT VOLTAGE: ~400 VDC

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B.2 DYNAMIC LOAD RESPONSEWhen measuring the dynamic load response theundershoot/overshoot voltage and settling time of theoutput voltage are captured when a load step changeis performed on the output.
Figure B-3 and Figure B-4 demonstrate the dynamicload response of the system with a load step change of25%-75% and 75%-25% with a slew rate of 1A/µs.

FIGURE B-3: TRANSIENT RESPONSE 25%-75% (4A-12A), INPUT VOLTAGE: ~400 VDC

Legend:Green = Output voltage

Yellow = Output load current


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FIGURE B-4: TRANSIENT RESPONSE 75%-25% (12A-4A), INPUT VOLTAGE: ~400 VDC
Legend:Green = Output voltage

Yellow = Output load current


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B.3 OUTPUT VOLTAGE RIPPLEOutput voltage ripple is measured across the outputcapacitors with the shortest possible probe groundlead. Figure B-5 and Figure B-6 show the output volt-age ripple of the LLC Resonant Converter.
FIGURE B-5: OUTPUT VOLTAGE RIPPLE, IOUT: 17A, INPUT VOLTAGE: ~400 VDC


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FIGURE B-6: OUTPUT VOLTAGE RIPPLE, IOUT: 17A, INPUT VOLTAGE: ~400 VDC

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B.4 Phase and Gain MarginFigure B-7 shows the closed loop performance of theLLC Resonant Converter at nominal input voltage(400Vdc) and half load.
FIGURE B-7: PHASE AND GAIN MARGIN (VIN: 400 VDC, IOUT: 8.5A)

B.5 EFFICIENCY

FIGURE B-8: LLC EFFICIENCY @ 380 VDC AND 400 VDC

LLC Efficiency

757779

81838587

89919395

97

1 3 5 7 9 11 13 15 17

Output Load Current

Per

cent

(%)

380V400V


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B.6 Zero Voltage SwitchingDue to the phase shift between the resonant tank cur-rent and voltage the half-bridge MOSFETs are able toswitch without any turn on losses. Figure B-9 andFigure B-10 demonstrate zero voltage switching on thelow-side MOSFET.
FIGURE B-9: ZVS, IOUT: 8.5A INPUT VOLTAGE: ~400 VDC

Legend:Green = MOSFET gate-to-source

Violet = MOSFET drain-to-source

Yellow = Resonant tank current


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FIGURE B-10: ZVS, IOUT: 8.5A, INPUT VOLTAGE: ~400 VDC


Yellow = Resonant tank current


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B.7 Zero Current SwitchingFigure B-11 demonstrates zero current switching onthe secondary rectifier. As the MOSFET currentbecomes zero the MOSFETs Drain-to-Source Voltagebegins to rise. This eliminates any turn-off loses.
FIGURE B-11: ZCS, IOUT: 8.5A, INPUT VOLTAGE: ~400 VDC



Yellow = MOSFET current


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B.8 Resonant Tank CurrentFigure B-12 and Figure B-13 show the resonant tankcurrent at no load as well as full load near the resonantfrequency.
FIGURE B-12: RESONANT TANK CURRENT: NO LOAD


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FIGURE B-13: RESONANT TANK CURRENT IOUT: 17A

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B.9 Secondary CurrentsFigure B-14 shows the secondary MOSFET current atfull load.
FIGURE B-14: SECONDARY MOSFET CURRENT IOUT: 17A


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B.10 MOSFET Gate Signals
FIGURE B-15: PWM GATE DRIVE WAVEFORMS

Legend:Green and Red = Synchronous MOSFETs

Violet and Yellow = Half-bridge MOSFETs


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FIGURE B-16: PWM GATE DRIVE WAVEFORMS BELOW RESONANCE
Legend:Red = Synchronous MOSFET

Violet = Half-bridge MOSFET


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APPENDIX C: LLC RESONANT CONVERTER CONTROL SYSTEM DESIGN

C.1 System ModelingIt is desirable to model and simulate any powerconverter in order to optimize its performance inadvance. This approach is useful in achieving thedesired performance before testing the design onactual hardware.

System modeling involves the following process:

• Control loop coefficients are generated in MATLAB®, based on key system parameters and using an .m file.

• A graphical model of the system hardware and the control system is created using a Simulink® model (.mdl) file. The coefficients generated from the .m file are used in this Simulink model file.

• The model of the hardware and control system is then simulated at various operating points to ensure that the desired performance is achieved.

• The model of the control system is then imple-mented in software on the dsPIC DSC and the performance is verified on real hardware.

C.2 Principle of Operation of Half-Bridge LLC Resonant Converter

The LLC resonant converter operates on a fixed dutycycle, variable switching frequency to maintain aconstant output voltage for varying load and lineconditions.

The equivalent circuit of the LLC resonant converteris shown in Figure C-1. The operation of theconverter is based on a potential divider impedancenetwork. The output voltage is controlled by varyingthe voltage applied across the magnetizinginductance. This is achieved by changing the relativeimpedance of the LLC network elements usingvariable switching frequency. The output voltage cantherefore be controlled using the switching frequencyof the half-bridge.

FIGURE C-1: EQUIVALENT CIRCUIT OF LLC CONVERTER

LrCr

Lm Rpri

DC

Q2

Q1

Vpri

+

-

T


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C.3 AnalysisThe LLC resonant converter is a highly nonlinear sys-tem and difficult to analyze using an analytical formula.Since it is a DC/DC converter, operating point analysiscan be performed.
In a DC/DC converter, if the input and output voltagesare nearly constant quantities under changing loads,properties of the system do not change significantly.Therefore, small signal analysis and linearization canbe performed on the system.

A small change in input voltage, reference or load onlycauses a linearly dependent or proportional change inthe switching period. Mathematically we approximateall nonlinear terms with a 1-term Taylor SeriesApproximation about an operating point.

Consider the following example: If x is an input(independent variable) and y is an output (dependentvariable) with the following relationship:

y = x^2

The Taylor Series Approximation about the nominaloperating point (x0, y0) will be:

dy = 2x0 .dx

The relation dy/dx is the dynamic slope and can beused to study the system behavior. This method can begeneralized to any number of variables with the use ofpartial derivatives.

The goal is to generate correct voltage (Vx) at the out-put of the rectifier and input to the LC filter, by varyingthe switching period (T) of the half-bridge. For an LLCResonant Converter, the relation between Vx and T isnonlinear and therefore, the operating point approachis used.

The desired voltage Vx is obtained by varying theimpedances of the various elements in the circuitshown in Figure C-1. The impedances are given by Xc,Xr and Xm and are functions of the half-bridge switchingfrequency. The voltage that gets applied to the magne-tizing inductance is given in Equation C-1.

EQUATION C-1:

Vx appears across the output of the LC filter aftergetting scaled by the turns ratio, as shown inEquation C-2.

EQUATION C-2:

The voltage Vpri is determined by the gain of the LLCcircuit. This gain is shown in Equation C-3.

EQUATION C-3:

By modifying the switching frequency fS, the gain of theLLC circuit is changed and therefore the output voltagecan be controlled with varying load and input voltage.

The LLC circuit can be operated at any of the threeoperating regions:

• At resonance (Gp = 1)• Below resonance (Gp > 1)• Above resonance (Gp < 1)

For modeling of the system, we need to determine arelationship between the gain of the LLC circuit and theswitching frequency. Due to the nonlinear nature of thegain equation, we perform operating point analysisabout the nominal operating point, i.e. the resonant fre-quency. In order to perform operating point analysis,we define a new variable p at the resonant frequency fras shown in Equation C-4.

EQUATION C-4:VpriXm

Xm Xr Xc–+ ------------------------------------ Vin=

where, Vin is the input voltage

VxVpri

Turnsratio----------------------------=

GpVpriVin----------=

XmXm Xr Xc+ +

------------------------------------=

Where:

Gp = Gain of the LLC circuit.

Xm = j2fsLm = impedance of the magnetizinginductance.

Xr = j2fsLr = impedance of the magnetizinginductance.

Xc = 1j2fsCr------------------- = impedance of the series capacitor.

p 1Gp------=

Xm Xr Xc+ + Xm

------------------------------------=

1LrLm------ 1

42fS2CrLm

--------------------------------

–+=

VpriVinp-------=


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As a result of the calculations in Equation C-4, Vpri isnow expressed as shown in Equation C-5.
EQUATION C-5:

Differentiating both sides with respect to frequency,results in that of Equation C-6.

EQUATION C-6:

Vpri is the change in Vpri observed for a small changein frequency. Frequency is represented as a function ofthe switching period, as shown in Equation C-7.

EQUATION C-7:

Substituting the results of Equation C-7 intoEquation C-6 is expressed in Equation C-8.

EQUATION C-8:

As the change in frequency is assumed to be small, wecan replace fS in Equation C-8 to the nominal operatingfrequency (i.e., the resonant frequency fr). Theequation then changes to that of Equation C-9.

EQUATION C-9:

Now, the final period output is defined, as shown inEquation C-10.

EQUATION C-10:

In Equation C-10, the term, (p022frCrLm), is a con-

stant, because the change in period is assumed to besmall for the range of operation of the LLC converter.Therefore, we can replace this term with the constant,voltagetotimefactor, which is defined in Equation C-11.

EQUATION C-11:

Also, Vpri is the change in the Vpri for a correspondingchange in period T. Using Equation C-2, we can rep-resent the change in voltage with respect to the outputvoltage, as shown in Equation C-12.

EQUATION C-12:

Substituting Equation C-11 and Equation C-12 inEquation C-10, we obtain the final expression for thedesired switching period, as shown in Equation C-13.

EQUATION C-13:

VpriVin

1LrLm------ 1

42fS2CrLm

--------------------------------–+ ------------------------------------------------------------=

VpriVin

p2-------– 122fS

3CrLm --------------------------------

fS =

Where,represents a small change in the variable.

fS1

TS-----=

fS1–

TS2-------- TS=

fS 2 TS=

VpriVin

p222 fSCrLm

---------------------------------

TS =

VpriVin

p0222frCrLm

-------------------------------------

TS =

where, p0 is the inverse gain calculated at the resonant frequency

TS Tnom TS+=

TnomVpriVin

------------- p0

222frCrLm +=

voltagetotimefactor p0222frCrLm=

Vpri Vpri Vpri_nom–=

Vx Vx_nom– turnsratio=

TS Tnom voltagetotimefactor Vx Vx_nom– turnsratioVin

--------------------------- +=


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Tnom is known from the converter design, andvoltagetotimefactor is a constant defined previously. Thevoltage Vx is the control voltage required to produce thedesired output voltage. This voltage Vx is generated bythe digital compensator for the LLC Converter.Therefore, Equation C-14 will produce the desiredswitching period based on the measured output voltageand input voltage.
A Proportional + Integral (PI) compensator is chosenfor the LLC resonant converter. Use of a Derivativeterm is ruled out because the series parasiticresistance of the system acts as a natural dampingfactor, and swamps any effect of the derivative term.

Figure C-2 shows the block diagram of a generalizedcontrol system. In the LLC Converter, the output LCfilter forms the plant for the system. The output LC filter,in combination with the PI compensator provides thecharacteristic equation for the closed loop system,shown in Equation C-14.

EQUATION C-14:

The roots of the characteristic equation are chosento be -1400 Hz and -900 Hz at the nominal operat-ing point (Vin = 400V). The characteristic equation isthen solved for the unknowns Kp and Ki to determinethe compensator gains.

The compensator gains obtained by solving the char-acteristic equation are then used to generate an analogtransfer function of the compensator. The compensatortransfer function is then converted to a discrete form byusing the bilinear transform. The result of the bilineartransform generates the final difference equation of adigital PI compensator.

FIGURE C-2: HIGH-LEVEL BLOCK DIAGRAM OF CONTROL SYSTEM SHOWING PLANT AND CONTROLLER

s2LC sRC KpKis----- 0=+ + +

Where:

L = output inductor

C = output capacitor

R = parasitic (lumped) series resistance of the circuit

Kp = proportional gain of the compensator

Ki = Integral gain of the compensator

PlantModulationController

-

+

Reference OutputError


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C.4 Digital Control System
Implementation:Figure C-3 shows the top level block diagram of theLLC Converter model. The model consists of twoseparate implementations as follows.

• Analog LLC Converter model• Digital LLC Converter model

The analog model provides most of the informationneeded for the compensator design. The digital systemincludes the effect of various phenomena like quantiza-tion errors, errors due to finite precision, effect of sam-pling and saturation limits. As a result, both analog anddigital systems must be modeled to accurately modelthe real system. For simplicity, factors like scaling andADC feedback gain are not included in the analogmodel.

FIGURE C-3: TOP LEVEL DIAGRAM OF SIMULINK MODEL OF LLC CONVERTER

Vo*1

12

Vo*

12

Vin1

200

Vin

200

Total Digital System 1

Vref/Vo*

Vin

Iload

Vo

IL

Total Analog System

Vref/Vo*

Vin

Iload

Vo

IL

Scope1

Scope

Load Generation 2

Total Load

Load Generation 1

Total Load


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Figure C-4 shows the contents of the total analogsystem. All values are in real physical and standardunits. It contains three main sub-systems:
• Output LC Filter / Plant• Control System Block• Modulation Block

FIGURE C-4: LLC CONVERTER ANALOG SYSTEM MODEL

The Output LC Filter/Plant block shown in Figure C-5,models the output inductor and capacitor withparasitics like the capacitor ESR and inductor DCR.The input to this block is the controlling voltage Vx andload current Iload, while the output of the block is theoutput voltage of the system.

FIGURE C-5: OUTPUT LC FILTER/PLANT

IL2

Vo 1

turnsratio-K-

Modulation

VinIloadTS

Out1

Control System

VoVinVo*

TS

Transfer Fcn

150e-6s+1

Scope 2

L-C Circuit/Plant1

L_C Vx1

Iload

Vo1

IL

Iload3

Vin2

Vref/Vo*1

IL

2

Vo11

turnsratio-K-

L

Vx

Vo

IL

C

Ic Out1

Iload2

L_C Vx11


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Figure C-6 shows the modulation block of the LLCConverter model. This block implements the gain equa-tion of the LLC circuit, as given by Equation C-1. Theinput to the modulation block is the switching periodvalue calculated by the control system block. Theperiod value is converted into the transformer primaryvoltage Vpri, which is then converted to the controllingvoltage Vx by using Equation C-2. In essence, the mod-ulation block implements the operation of the LLCcircuit. Due to the reactive nature of the LLC circuit, thecurrent flowing through it may not be in phase with thevoltage. The output voltage is only a function of themagnitude of the Vpri voltage. As a result, themodulation block calculates the magnitude of Vpri toobtain Vx.
FIGURE C-6: MODULATION BLOCK

The control system block shown in Figure C-7 imple-ments the digital PI compensator and an inverse mod-ulation block. The inputs to the control system block arethe voltage reference and measured output voltage,while the output is the desired switching period.

The PI compensator is designed for real units, andtherefore the output of the PI block is in volts. Themodulation inverse block converts the output of the PIcompensator to the desired switching period and alsofactors in the effect of any changes in Vin.

FIGURE C-7: ANALOG CONTROL SYSTEM BLOCK

Out11

Impedances

In1

Xm

Xs

Xc

Subsystem

Xm

Xs

Xc

1+Z/Xm

Z

RProduct 3 Product 2

Product 1

Product

MathFunction Divide

TS

3

Iload2

Vin1

turnsratio-K-

Scope1

PI

0.47s+1.6e3

den(s)

Modulation inverse

Vx

Constant

12

Vo*3

Vin2

Vo1


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We use a method called digital by emulation. In thismethod, an analog control system model is created andthen converted into a discrete control system. Toaccount for discretization, Zero order hold, 16-bit finiteprecision, 10-bit ADC resolution (quantization) andcomputational delays must be incorporated in the digi-tal control system model. These factors are imple-mented in the digital control system block, shown inFigure C-8.
All voltage quantities are scaled to a base voltage andall time quantities are scaled to base time quantity. Thebase voltage is the output voltage that will produce afull scale ADC reading. The base time quantity is themaximum allowable switching period in the system.

As a result, all voltage quantities used in the controlsystem are represented as a fraction of the basevoltage. Similarly, all time quantities are represented asa fraction of the base period. The actual implementa-tion of the control system is therefore done using theQ15 fractional format.

Due to the conversion to Q15 on all inputs of the controlsystem, the inverse conversion back to real units mustbe performed at the output of the control system.Therefore the final output is multiplied with the baseperiod to generate the new period value.

The Q15 format limits all numbers in the range -1 to +1.Sometimes the coefficients generated after solving thecharacteristic equation and converting to discretequantities may exceed this maximum range. In thiscase, the coefficients are divided using a prescaler inorder to enable Q15 operations. The output is thenpost-multiplied to produce the correct result.

Ultimately, the equations to be implemented are asshown in Equation C-15.

FIGURE C-8: DIGITAL CONTROL SYSTEM BLOCK

EQUATION C-15:

TS1

turnsratio-K-Output Voltage

1

Scope 1

PID

FilteredIout

Pout

Modulation

Vx

Vinsecondary

Constant12

Vo*3

Vin2

Vo1

Error

Decoupling

Inverse/DutyGeneration

TS

TSQ15 TnomQ15 modifier voltagetotimefactor VxQ15 VoQ15 VxnomQ15–+ turnsratioVinmin

--------------------------- +=

Where:

VxQ15 = output of the digital PI compensator

VoQ15 = output voltage decouple term

VxnomQ15 = Output voltage reference

modifierVinmin

Vin---------------=

voltagetotimefactor p0222 frCrLm=


AN1336
We then define another constant, multiplier, as shownin Equation C-16.
EQUATION C-16:

We can then replace the constants in Equation C-16with the constant multiplier and obtain the finalexpression for the switching period as shown inEquation C-17.

EQUATION C-17:

multiplier voltagetotimefactor turnsratioVinmin

---------------------------=

TSQ15 TnomQ15 modifier multiplier PIoutputQ15 VxnomQ15 VoQ15+– +=TS TSQ15 Tmax=


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C.5 Simulation Results
FIGURE C-9: LOOP GAIN PLOT (ANALOG AND DIGITAL)

FIGURE C-10: CLOSED LOOP PLOT (ANALOG AND DIGITAL)

-150

-100

-50

0

50

Mag

nitu

de (d

B)

101 102 103 104 105 106-450

-360

-270

-180

-90

Pha

se (d

eg)

Frequency (Hz)

Blue = DigitalRed = Analog

Legend:

-30

-25

-20

-15

-10

-5

0

5

10

Mag

nitu

de (d

B)

101 102 103 104-270

-225

-180

-135

-90

-45

0

Pha

se (d

eg)

Frequency (Hz)

Blue = DigitalRed = Analog

Legend:


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FIGURE C-11: DISTURBANCE REJECTION (ANALOG ONLY)
0

10

20

30

40

50

Mag

nitu

de (d

B)

101

102

103

104

-90

-45

0

45

90

Pha

se (d

eg)

Frequency (Hz)


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FIGURE C-12: TRANSIENT RESPONSE SIMULATION

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APPENDIX D: DESIGN PACKAGEA complete design package for this reference design isavailable as a single WinZip® archive file. This archivecan be downloaded from the Microchip corporate Website at: www.microchip.com

D.1 Design Package ContentsThe design package contains the following items:

• Reference design schematics• Fabrication drawings• Bill of materials• Assembly drawings• Hardware design Gerber files


http://www.microchip.com

AN1336
NOTES:

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ISBN: 978-1-60932-417-9

DS01336A-page 81

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DC/DC LLC Reference Design Using the dsPIC DSCww1.microchip.com/downloads/cn/AppNotes/cn549772.pdf · 2010. 8. 2. · Series Resonant Converter • The series resonant converter can