1dc2100bfa

DEMO MANUAL DC2100B

Description

Bidirectional Cell Balancer Using the LTC3300-1 and the LTC6804-2

Demonstration Circuit DC2100B is a Bidirectional Cell Balancer using two LTC®3300-1 ICs to achieve active bal-ancing of up to 12 Li-Ion cells. The board uses a single LTC6804-2 Multi-Cell Addressable Battery Stack Monitor IC to measure cell voltages and two LTC3300-1 ICs to provide active cell balancing. The DC2100B-C contains a PIC18F47J53 microcontroller to communicate with the LTC3300-1 and LTC6804-2 ICs, as well as an LTC6820 isoSPI Interface IC for communication with DC2100B-D boards. Up to seven DC2100B-D boards can be connected to a DC2100B-C to build a stacked system of eight total boards.** Note: The voltage rating of T15 limits the system to a total of 8 boards.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and QuikEval is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective owners.

performance summary

Demo BoarD Description

A graphical user interface (GUI) uses a USB interface to communicate with the DC2100B-C. The GUI controls the LTC3300-1 ICs allowing manual control of the charging/discharging of cells and reporting the voltage of each cell. Cell balancing is achieved through the LTC3300-1 ICs by transferring charge from one or more cells per LTC3300-1 to the stack or from the stack to one or more cells per LTC3300-1.

Design files for this circuit board are available at http://www.linear.com/demo/DC2100B

Source code and documentation for PIC18 and GUI are available at http://www.linear.com/docs/45563

Specifications are at TA = 25°C

Cell Voltage Range 3.2V to 4.5V (2.5V to 4.5V)*

Stack Voltage 60V Max

Average Battery Balancing Charge Current (12 Cells) 4.0A (Typ)

Average Battery Balancing Discharge Current (12 Cells) 4.3A (Typ)

Average Battery Balancing Charge Current (6 Cells) 3.4A (Typ)

Average Battery Balancing Discharge Current (6 Cells) 4.0A (Typ)

Balancing Efficiency 90% (Typ)

DC2100B-C 12-Cell 4A Active Cell Balancer Controller Board

DC2100B-D 12-Cell 4A Active Cell Balancer Stacked Board

*The Cell Voltage Range may be expanded to 2.5V to 4.5V by changing the resistors RTONS to 30.9kΩ and resistors RTONP to 47.5kΩ

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DEMO MANUAL DC2100B

Quick start proceDure

Discharge Efficiency Charge Efficiency

Figure 1. Cell Balancer Efficiency vs Cell Voltage

Figure 2. Thermal Image All Cells Active Balancing

The conditions for the Thermal Plot are:Cell Voltages at 3.6V, Odd Numbered Cells Discharging, Even Numbered Cells Charging

CELL VOLTAGE2.6

75.0

EFFI

CIEN

CY (%

)

95.0

90.0

85.0

80.0

100.0

3.2 3.4 3.6 3.8 4.02.8 3.0

12 CELLS6 CELLS

dc2100b F02aCELL VOLTAGE

2.675.0

EFFI

CIEN

CY (%

)

95.0

90.0

85.0

80.0

100.0

3.2 3.4 3.6 3.8 4.02.8 3.0

12 CELLS6 CELLS

dc2100b F01b

dc2100b G03

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 3. DC2100B-C Demo Board Photo

Figure 4. DC2100B-C Demo Board Size Equals 5.5" × 12.8"

dc2100b G04

dc2100b F04

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DEMO MANUAL DC2100B

operating principleThe DC2100B has a five window GUI, pictured in Figure 38. The Control Panel is the primary window which displays information about the ICs in the stacked system, the state of the cells on each DC2100B board, and allows manual control of the balancing mode of the LTC3300-1. The Control Panel can spawn three more windows: a Calibra-tion Data window to calibrate cell and balancer charac-teristics, an Error Log window to display logged errors, and a Graph View window to graphically display char-acteristics of the stacked system over time. The Graph View window also spawns a Graph View Option window that controls the settings of the Graph View window. The LTC3300-1 Active Balancer is a power stage control IC. The LTC3300-1 does not have a balancer algorithm built into it. The determination of the balancing times and direc-tions are performed at a system level and conveyed to the LTC3300-1 through its SPI interface. The LTC3300-1 only accepts cell charge or discharge commands. Charge

is transferred to/from a cell from/to the stack, a series connection of adjacent cells, through a flyback converter that is operating in boundary mode. During discharge of a cell, the current in the primary of a coupled inductor transformer with a turns ratio of 1:2, ramps up to 10A at which point the primary switch turns off. The energy in the inductor primary winding is transferred to the inductor secondary winding which is connected across the 12-cell sub-stack. This sub-stack current then passes through the series connected cells thus distributing the charge equally across each cell. When charging a cell, the current in the secondary of the coupled inductor transformer ramps up to 5.0A at which point the secondary switch turns off. The energy in the inductor secondary winding is transferred to the inductor primary winding which is connected across the cell. The secondary current is drawn from the series connected cells thus removing charge equally across each cell. The efficiency through the flyback converter is 90%.

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DEMO MANUAL DC2100B

Quick start proceDureThe demonstration circuit is set up per Figure 44 to evalu-ate the performance of the DC2100B-C Bidirectional Cell Balancer using the LTC3300-1.

Using short twisted pair leads for any power connections, refer to Figure 44 for the proper measurement and equip-ment setup. The DC2100B will support a system of 4 to 12 cells (see Figure 44 and Figure 47 to Figure 54).

The thermistor board is packaged separately, and may be inserted in J17. See Figure 37. The thermistor board includes fixed resistors which simulate the resistance val-ues over a very wide range of temperatures.

Connection of DC2100B to a Battery Emulator or Battery Stack

Depending on the impedance of the power source and connecting wires, connection of the DC2100B to a power source can cause electrical overstress on the LTC3300 C1-C6 pins and destruction of the part. In the case of a battery emulator, there is typically sufficient impedance in the power source to allow direct connection of the DC2100B. In the case of a stack of low-impedance cells, precharging the input terminals on the DC2100B or actively controlling the inrush current is required. These cases are described below.

Whether the DC2100B is being connected to a battery emulator or a battery stack, the recommended cell connection sequence is to connect the V– connection first followed by connecting cells 1 through cell 12. Disconnection of the cells should follow this sequence in the reverse order with the V– connection being removed last.

Battery Emulator Power Source

For experimentation and evaluation, the DC2100B may be connected directly to a stack of battery emulators. A battery emulator is a standard power supply with a preload to absorb cell-charging currents. The power supplies must have enough current capability to source cell-discharging currents plus the current required for the resistive preload. See Figure 5.

Figure 5. Battery Emulator Concept. Resistors Are Sized to Sink Up to 4.3A at 3.2V

dc2100b F05

+–

PS120V to 4.5V10A

750mΩ

+–

PS110V to 4.5V10A

750mΩ

+–

PS100V to 4.5V10A

750mΩ

+–

PS90V to 4.5V10A

750mΩ

+–

PS80V to 4.5V10A

750mΩ

+–

PS70V to 4.5V10A

750mΩ

+–

PS60V to 4.5V10A

750mΩ

+–

PS50V to 4.5V10A

750mΩ

+–

PS40V to 4.5V10A

750mΩ

+–

PS30V to 4.5V10A

750mΩ

+–

PS20V to 4.5V10A

750mΩ

+–

PS10V to 4.5V10A

750mΩ

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

V–

DC2100B

Lab experience has shown that hot plugging the battery emulator to the DC2100B with the lowest-imedance interconnect can be performed repeatedly without exposing the LTC3300-1 controllers to excessive voltage on the C1-C6 pins. Two sets of experiments were performed to estimate the source impedance of the battery emulator used in the laboratory. See Figure 6 for a picture of the setup.

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DEMO MANUAL DC2100B

Figure 6. Lab Set Up for Hot-Plug Inrush-Current Measurement Showing Low-Impedance Connections to Battery Emulator and Placement of Oscilloscope Voltage Probes Near LTC3300-1

Quick start proceDure

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DEMO MANUAL DC2100B

The first technique to estimate battery-emulator source impedance was to initiate a charge operation on a particular cell while monitoring the charging current and corresponding voltage disturbance across the DC2100B input terminals for that particular cell, then calculating the implied resistance. This experiment was performed on each input with results ranging from 150mΩ to 185mΩ with an average of 170mΩ.

A second technique employed was to monitor the voltage differential between the C(n+1) and C(n) pins of the LTC3300-1 while hot plugging the corresponding C(n) input to the battery emulator and monitoring its current. Figure 7 shows the result while hot plugging C10. Peak C10 current is observed as the C10-to-C9 capacitance charges through 1V. The remaining 3V drives a peak current of 20.8A into the DC2100B. The corresponding resistance is estimated to be 150mΩ. The C10-to-C9 voltage overshoots to 5.1V, safely within the 6V absolute maximum voltage rating of the part.

These experiments provide guidelines to the DC2100B user concerning whether or not special precautions are required when connecting the DC2100B to a power source/sink. The preceding test results demonstrate that the DC2100B can be hot plugged into a battery emulator or battery stack with source impedances in the 150mΩ range or greater. A peak inrush current of 20A during hot plug does not cause problems.

Battery Stack Power Source

When hot-plugging a battery stack to the DC2100B the low source impedance coupled with inductance in the connecting wires and the input capacitance at the DC2100B inputs can generate voltage transients exceeding the 6V absolute maximum rating of the LTC3300. To prevent the LTC3300 from voltage overstress, precharge the cell inputs through a moderate resistance (ca. 25Ω) before connecting the low-impedance power source. The following sections describe different methods of controlling the inrush current experienced when the DC2100B is initially connected to a large (i.e., low-impedance) battery stack by pre-charging the inputs.

Manual Precharge

Manually precharging the DC2100B inputs is a straightforward way to eliminate harmful inrush currents and subsequent voltage-overshoot events.

• First connect the bottom of the battery stack to the DC2100B V– terminal.

• Then, precharge the C1 input by initially charging the C1 terminal to the positive end of the first (i.e., bottom-of-stack) cell through a 25Ω resistor.

• Finally, immediately make the final connection of the C1 terminal without the series resistance.

• Repeat precharge and final connection operations sequentially up the battery stack for the C2 – C12 ter-minals.

Quick start proceDure

Figure 7. Waveforms of Inrush Current and Voltages at LTC3300-1 When Hot Plugging C10 to a Battery Emulator

dc2100b F07

V (U2 PIN C4)

C10 CURRENT

V (U2 PIN V–)

V (U1 PIN V–)

100µs/DIV

2V/DIV

2V/DIV

5A/DIV

2V/DIV

A variation to the hot-plugging tests was to add a 1.9μH inductor in series with the interconnect wire used to hot plug C10. The inductor was designed to be non-saturable with extremely low DC resistance. The results of this test were similar to those with no series inductance with lower peak current. There was no excessive voltage overshoot at the LTC3300-1.

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DEMO MANUAL DC2100B

Simultaneous Precharge

Two techniques to precharge the DC2100B input capacitance without manually precharging each input are presented. The techniques employ a reuseable precharge circuit. One technique (thirteen-wire pre-charge connection) can be applied without modifying the DC2100B. The second technique (two-wire pre-charge connection) requires the addition of voltage-limiting diodes to the DC2100B inputs.

Simultaneous Precharge with a Thirteen-Wire Connection

A simultaneous pre-charge scheme that can be used with the DC2100B without modification is shown in Figure 8. This technique requires an external precharge circuit which is connected to the DC2100B as part of the process of connecting the DC2100B to the battery stack. The procedure for precharging is as follows.

• Apply power to Precharge Circuit using Connector 1.

• Apply precharge voltage to DC2100B using Connector 2.

• Attach Battery Pack to DC2100B using Connector 3.

• Disengage Precharge Circuit by unplugging Connector 1 and Connector 2.

Simultaneous Precharge with a Two-Wire Connection

It is also possible to precharge the DC2100B inputs by applying the full stack voltage between the V– and C12 terminals. See Figure 9. When the pre-charge voltage is first applied to the DC2100B, the voltages on the capacitors will be determined by the relative values of capacitance between the DC2100B inputs. These input-capacitance values1 are chosen to distribute the applied voltage equally among the inputs. After the pre-charge circuit is first connected to the DC2100B, the voltages on the input capacitors will drift in different directions over a period of seconds as on-board leakage currents move

charge from one input to the other. A stack of voltage-limiting diodes is added across the DC2100B inputs for the 12 cells to limit the voltage excursion. These diodes can be added between the input turrets, or on top of or in place of D1E-D12E. (See Input Protection Diodes for a discussion of protection offered by D1E-D12E.) The procedure for precharging is as follows.

• (Ensure voltage-regulating diodes are in place on the DC2100B)

• Apply power to Precharge Circuit using Connector 1.

• Apply precharge voltage to DC2100B using Connector 2, then immediately

• Attach Battery Pack to DC2100B using Connector 3.

• Disengage Precharge Circuit by unplugging Connector 1 and Connector 2.

The voltage-limiting diodes should be chosen with reverse-leakage current in mind. Higher leakage current will reduce the rate at which the input voltages drift from their initial pre-charge value, but they will also present a drain on the battery pack. The 1N4733A is inexpensive, but has significant reverse-leakage current at lithium-ion-cell voltages2. The STM SMA6TY is in a larger package, and has much lower reverse-leakage current3.

Recall that hot-plugging a cell into a significantly different precharge voltage can induce overshoot and board failure. The voltage-limiting diodes restrict extreme voltage excursions on the DC2100B inputs, but they cannot maintain the pre-charge voltage on the inputs. This fact drives the system designer towards minimizing the time between pre-charging the input capacitance of the DC2100B (when Connector 2 is engaged) and attaching the battery stack (when Connector 3 is engaged).

Quick start proceDure

1 These capacitances are C1A-C12A, C1B-C12B, C1K-C12K, C9-C18, C20, C23-C24.

2 Reverse leakage current for the 1N4733 at typical cell voltages is not specified. Seven parts from a lab drawer averaged 165μA leakage at a reverse voltage of 4.0V at room temperature.

3 Reverse leakage is specified at 5V as 20μA maximum at 25°C.

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DEMO MANUAL DC2100B

Figure 8. Scheme 1 for Simultaneous Precharge with a 13-Wire Connection

Quick start proceDure

• Apply power to precharge circuit using Connector 1• Apply precharge voltage to DC2100B using Connector 2.• Attach battery pack to DC2100B using Connector 3• Disengage precharge circuit by unplugging Connector 1

and Connector 2.

dc2100b F08

PRECHARGECIRCUIT

25Ω

12×

5.1V

, 1W

+ 1

2×10

kΩ

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

V–

DC2100B

CONNECTOR2

CONNECTOR1

CONNECTOR3

13

13

BATTERYSTACK

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 9. Scheme 2 for Simultaneous Precharge with a 2-Wire Connection

dc2100b F09

25Ω

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

V–

DC2100B

PRECHARGE CIRCUIT

CONNECTOR2

CONNECTOR1

CONNECTOR3

13

2

BATTERYSTACK

• Ensure voltage-regulating diodes are in place on the DC2100B• Apply power to precharge circuit using Connector 1• Apply precharge voltage to DC2100B using Connector 2• Attach battery pack to DC2100B using Connector 3• Disengage precharge circuit by unplugging Connector 1 and Connector 2

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DEMO MANUAL DC2100B

Quick start proceDureBoard ID

A 4-bit board ID code set by the A0 through A3 jumpers on the DC2100B-C must be set to 0000. The jumpers on the DC2100B-D boards must be set to unique values between 0001 and 1111.

Driver Installation

To use the DC2100B, the PC must first have the proper driver and software installed. To do this, download the QuikEval™ software from Linear Technology, at www.linear.com:

http://www.linear.com/designtools/software/quik_eval.jsp

1) Install the QuikEval software by running the execut-able ltcqev.exe. Follow the instructions to connect the DC2100B.

If you fail to unplug the DC2100B, the DC2100B driver will not install!

2) When installation of QuikEval is complete, close the QuikEval program.

3) Reopen QuikEval. If properly installed, QuikEval will show the following message until the DC2100B is con-nected:

If not properly installed, QuikEval will be unable to connect to the DC2100B. Please retry the software installation, with the DC2100B disconnected.

4) Now connect the DC2100B. The QuikEval software will recognize when the DC2100B demo board has been found, and will offer to download and install the module from the LTC website:

At this point, select OK.

5) The QuikEval software will now download and open the software for the DC2100B.

6) Close QuikEval Software, as it is no longer needed for the DC2100B.

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DEMO MANUAL DC2100B

Figure 11. Turning Off Cell 1 on Board 3

Figure 12. VOV and VUV Text Boxes

The green LED flashes quickly when a board is connected but its cells are not powered, and slowly when a board is connected with powered cells. The amber LED turns on when the GUI is communicating with a board via USB.

When the DC2100B is used with fewer than 12 cells, the board must be configured in the GUI so that the unpopu-lated cells are not interpreted as an undervoltage condi-tion. When a cell is red in the System Tree View, it has been specified as unpopulated. To configure a DC2100B for fewer than 12 cells, right click the board in the System Tree View and select the number of populated cells. For this to work properly, the board must be configured for fewer cells according to one of the setup diagrams in Figure 47 to Figure 54.

The DC2100B GUI periodically checks for OV and UV mea-sured on the cells when balancing. To avoid the program from suspending balancing from a OV and UV measure-ment during normal operation, the Max Cell Voltage and UV values must be entered in the VOV and Min Cell Volt-ages text boxes tab shown in Figure 12.

Quick start proceDureUse of the GUI

When the DC2100B-C is connected to the PC, the PIC18 will become powered. The powered status will be indi-cated through green LED D15 flashing with a 1 second period. When the GUI is launched, it will begin communi-cating with the PIC18 via USB. Proper USB communica-tion will be indicated through orange LED D16 lighting during each USB transaction.

When the GUI connects to the DC2100B system, it will display the boards attached in the Control Panel System Tree View. The DC2100B GUI Control Panel is able to dis-play the data and controls for one board at a time. When a board is selected in the System Tree View, all of the Windows will begin to display the data and controls for that board. The Selected Board Indicator in each window will indicate which board is selected. The Board Status LEDs indicate the state of the boards similarly to the LEDs on the DC2100B-C.

Figure 10. Board Selection in System Tree View

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 13. Voltage Display Controls

The cell voltages in the Control Panel can be configured to stop updating automatically, and only be updated when the Read Voltages button is clicked (as shown in Figure 13). This provides the ability to freeze the data for a board at any instant in time.

Figure 14. Balance Mode Select Boxes

Several controls are available on the Control Panel Cell Tab for issuing balancing commands to the selected board. In the Balance Mode Select Boxes, you can manually select which cells are to be discharged by clicking the cell’s DIS-CHARGE button, which cells are to be charged by clicking the cell’s CHARGE button.

An alternative method of viewing the data is available by pressing the Graph Data button, to open the Graph View Window. The Graph View Window is detailed in Figure 43, and allows data for each board and the stacked system to be graphed over time. The graph data can be saved and are reloaded later, and the View Options control allows configuration of the Graph Display. The Stack Summary provides graphed data for the entire system, where the Board Summary, Cell Voltages, and Temperatures allow data to be graphed for boards selected in the Tree View. Up to 15 values may be graphed at one time, and the graph is limited to 500 seconds of data.

The Global Channel Monitor tab switches the Control Panel to a grid view in which all of the cell voltages can be viewed at the same time. Disabled cells will be color coded as grey, and cells selected in the System Tree View will be highlighted in blue. Details of the Global Channel Monitor View are provided in Figure 40.

Figure 15. Manual Balance Control

Note that if a cell is disabled, the balance mode select box will not be selected and the cell pictured will be grey. Balancing and overvoltage conditions are also indicated by color, according to the Cell State Color Key.

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DEMO MANUAL DC2100B

Quick start proceDurethrough its SPI communications port. In order to perform a timed balance, the TIMED BALANCE check shown in Figure 17 must be selected to have access to the timed balance controls as shown in the Balance Mode Select Boxes.

To use the Timed Balance method of balance control, select the DISCHARGE, CHARGE, or NONE button for each cell and then enter the time in seconds into the cells “BAL-ANCE TIME” text box. Press the Write button to write the balance commands and times into the selected board. Select another board from the System Tree View and repeat until the balance settings have been loaded into each DC2100B board. Press the Start button to begin the timed balance for all of the boards in the stacked system. The balance times will then begin to count down as the balancing is performed, and the LTC3300-1 Register Dis-play will be continuously updated. The NEXT STOP TIME field will display the earliest time that one of the cells will complete balancing, and the board on which that cell resides. When the NEXT STOP TIME arrives, the balance mode for that cell will change to NONE and a new cell will display for the NEXT STOP TIME. The TIME REMAINING will display the total time remaining in the timed balanc-ing, after which all of the cells will have NONE for their balancing mode.

Once the balance modes are selected, they are not imme-diately written to the LTC3300-1 ICs. Two methods are available for writing the balance modes: Manual and Timed Balance Control. When the Manual Balance method is selected, the Write Command button will cause the GUI to write the balance modes to the selected board.

Once the balance mode commands are written to the LTC3300-1 ICs, balancing will not begin until the Execute button has been pressed to command the balancing to begin. The Execute button will cause all of the attached boards to begin balancing. This allows each board to have its balancing commands set up when selected in the Sys-tem Tree View, and to then have all of the balancers turned on together. To disable any cell from balancing, the cell’s NONE button must be clicked in the Balance Mode Select Box followed by clicking the Write Command button and finally the Execute button. Each time the Execute button is pressed, the Read Command and Read Status registers will be updated for the selected board (see Figure 16).

When the Timed Balance method of balance control is selected, the GUI allows the user to program the balancer to charge or discharge each cell for a specific amount of time. The LTC3300-1 is a power stage control IC. The determination of the balancing times and directions are done at the System level and conveyed to the LTC3300-1

Figure 16. LTC3300-1 Register Display

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 18. Timed Balancing

While balancing is active, the Start button (see Figure 18)will change to Stop, in case the user wishes to pause the balancing operation. Selecting the Reset button will reset all of the balance timers to 0 and all of the cell balance modes to NONE.

In addition to the Graph View of the data, the DC2100B system can be monitored over a long period of time with the results written to a CSV file. The logging interval and length can be configured, but note that the size of the data files can grow quite large for stacked systems with many boards. The projected memory size will be displayed before the user begins logging by pressing the Start Data Log button. Once the button is pressed, the user will be prompted to enter a data file name and location, and the logging will begin.

Figure 19. Board Configuration Control

Although each DC2100B will balance with currents similar to those listed in Table 1, each board was tested upon manufacture and its actual balancing currents are stored within the DC2100B. These currents can be accessed by pressing the Calibration Data button on the Control Panel, which will then launch the Calibration Data window (see Figure 41). In this window the user has the ability to enter new calibration current values, or reset the currents to the values from the Performance Summary table. It is not recommended to change these, however, from the factory measured settings. The capacity of each cell can also be stored in the DC2100B.

The DC2100B GUI installed with the QuikEval software, will always contain the most up-to-date version of firm-ware for the DC2100B. In order to update the firmware, press the Update Firmware button in the Control Panel.

Figure 20. Data Log Control

Figure 21. Update Firmware Button

Figure 17. Timed Balance Control

The user can load and store several timed balance profiles in the Board Configuration control (see Figure 19). The Imbalance Cells button in this control will load a pattern of charging and discharging cells. The user can then manu-ally configure the Timed Balance controls to correct for the imbalance created by this button. The user can save their Timed Balance configuration and reload it later. The configuration will also save the over and undervoltage settings, as well as the disabled cell configuration.

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DEMO MANUAL DC2100B

Quick start proceDureAfter confirming that the firmware should be updated, a command line window will be launched in which the PIC18 on the DC2100B is first erased, and then repro-grammed. Do not remove power from the DC2100B while the firmware is being updated.

Cell Balancer Efficiency Measurements

Figure 45 shows the proper connections for measuring the efficiency of a cell balancer. The secondary of the cell balancer connects to the top of stack. This connec-tion needs to be to an isolated power source through a current-sensing resistor (0.10Ω). Cells 1 through 6 are connected to the BOT6_TS turret with its return path the V– turret while Cells 7 through 12 are connected to the TOP6_TS turret with its return path the C6 turret. These isolated power sources simulate a stack of cells from 3 to 12 cells. The primary side connection of the cell balancers are connected to a string of power sources that simulate the battery stack. Cell 1 power source is a two wire con-nection that connects the positive node, through a current sensing resistor (0.01Ω), to the C1 turret, and the nega-tive node to the V– turret. Remote sense connections for power sources with remote sensing capabilities should be connected to the C1 and V– respectively. All other connec-tions of the simulated string of cells connect their posi-tive node, through a current sensing resistor (0.01Ω), to respective turrets. Cell voltage measurements should be made across the C(x) and C(x-1) turrets of the respec-tive cells. Stack voltage measurements should be made at the BOT6_TS and TOP6_TS turrets and their return path turret.

Figure 22. Firmware Update Window

To calculate cell balancer efficiency use the expressions below:

Cells 1-6

Charge Mode

Efficiency1=

Vm1• Vm2 •10Vm3 • Vm4

•100%

Discharge Mode

Efficiency1=

Vm3 • Vm4Vm1• Vm2 •10

•100%

Cells 7-12

Charge Mode

Efficiency11=

Vm5 • Vm6 •10Vm7 • Vm8

•100%

Discharge Mode

Efficiency11=

Vm7 • Vm8Vm5 • Vm6 •10

•100%

Cell Balancer Performance Measurements

Table 2 through Table 5 present the typical operational data for a 12-cell and 6-cell balancer in both Discharge and Charge modes. The cell voltages were 3.6V and mea-surements of Cell Current, Stack Current, Operating Fre-quency were taken and transfer Efficiency was calculated from the data. Figure 23 through Figure 26 are actual in-circuit waveforms taken on Cell 1 and Cell 7 while oper-ating in both modes. The waveforms present voltage on the primary side and secondary side MOSFET’s drain to source voltage and the primary side and secondary side current sense inputs to the LTC3300-1.

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 23. 12 Cells Discharge Waveforms

Figure 24. 12 Cells Charge Waveforms

Figure 25. 6 Cells Discharge Waveforms

Table 2. Typical 12-Cell Discharge Data

Cell I (A)Stack I

(A)Frequency

(kHz) Efficiency

4.250 0.311 95.7 87.9%

Table 3. Typical 12-Cell Charge Data

Cell I (A)Stack I

(A)Frequency

(kHz) Efficiency

3.960 0.367 106.6 89.7%

Table 4. Typical 6-Cell Discharge Data

Cell I (A)Stack I

(A)Frequency

(kHz) Efficiency

4.000 0.577 88.6 88.4%

Table 5. Typical 6-Cell Charge Data

Cell I (A)Stack I

(A)Frequency

(kHz) Efficiency

3.430 0.619 91.2 91.8%

Figure 26. 6 Cells Charge Waveforms

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DEMO MANUAL DC2100B

Quick start proceDure

Figure 27. Cell Discharge Current

Figure 28. Stack Discharge Current

Figure 29. Cell Charge Current

Figure 30. Stack Charge Current

Figure 27 through Figure 30 are cell and stack currents taken over a range of cell voltages from 2.6V to 4.0V. The RTONP and RTONS resistors were set for 2.6V cell voltage operation. All cells were set to the cell voltage under test.

CELL VOLTAGE2.6

2.000

CELL

CUR

RENT

4.500

4.500

3.500

3.000

2.500

5.000

3.2 3.4 3.6 3.8 4.02.8

dc2100b F27

3.0

6 CELLS12 CELLS

CELL VOLTAGE2.6

0.100

STAC

K CU

RREN

T

0.900

0.800

0.700

0.600

0.500

0.400

0.300

0.200

1.000

3.2 3.4 3.6 3.8 4.02.8

dc2100b F28

3.0

6 CELLS12 CELLS

CELL VOLTAGE2.6

2.000

CELL

CUR

RENT

4.500

4.000

3.500

3.000

2.500

5.000

3.2 3.4 3.6 3.8 4.02.8

dc2100b F29

3.0

6 CELLS12 CELLS

CELL VOLTAGE2.6

0.100

STAC

K CU

RREN

T

0.900

0.800

0.700

0.600

0.500

0.400

0.300

0.200

1.000

3.2 3.4 3.6 3.8 4.02.8

dc2100b F30

3.0

6 CELLS12 CELLS

The slight negative slope in current at higher voltages is due to the increased operating frequency and the circuit delays and dead time becoming a higher percentage of the operating period.

19dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 31. Connection of Multiple DC2100B to Support a Larger Battery Stack

Two or More Board Setup and Operation

When connecting two or more DC2100B boards together, the interface cables must be connected as shown in Figure 31 to avoid large inrush currents. When con-necting more than one DC2100B’s into a system con-taining more than 12 batteries, DC2100B-D are used in locations 2 through 8. The PC USB port is connected to the bottom DC2100B-C (J19) board first and then the

next DC2100B-D (J18) may be connected to the bottom DC2100B-C (J1) with a CAT-5 cable. CAT-5 cables are used for communication connects between all DC2100B demo boards in the system. J1 is the output port while J18 is the input port. The Top DC2100B-D must have the JP6 in position 1. All other DC2100B will have JP6 in position 0.

dc2100b F31

LTC3300-1U2

LTC3300-1U1

DC2100B-D

I2C TO U6, U7 (LTC1380)AND U4 (24AA64)

LTC3300DAISY-CHAIN

BUS

2 23

3

2

SPI

LTC6804-2U3 isoSPI

isoSPI

T13

RJ45J1

RJ45J18

LTC3300-1U2

LTC3300-1U1

DC2100B-D

I2C TO U6, U7 (LTC1380)AND U4 (24AA64)

LTC3300DAISY-CHAIN

BUS

2 23

3

2

SPI

LTC6804-2U3 isoSPI isoSPI Termination

Settings – JP6

CAT-5CAT-5

isoSPI

T13

RJ45J1

RJ45J18

LTC3300-1U2

LTC3300-1U1

DC2100B-C

I2C TO U6, U7 (LTC1380)AND U4 (24AA64)

LTC3300DAISY-CHAIN

BUS

2 23

3

2

SPI

LTC6804-2U3

isoSPI

isoSPI

T13

RJ45J1

LTC2884U8

USBJ19

µPU10

THIS SECTION POPULATED IN DC2100B-C ONLY

2 24

SPI

4

USB

4

USB

LTC6820U5

isoSPI

T15

GALVANIC ISOLATION

20dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 32. Connection of Two DC2100Bs to Support a 24-Cell Battery Stack

Figure 32 shows how two DC2100B balancers might con-nect to a 24-cell battery stack. The BOT6_TS secondary terminal of the lower DC2100B-C is tied to the top of the sub-stack composed of cells 1-12 as it would be in the case of a single DC2100B. However, the TOP6_TS termi-nal is tied to the positive side of cell 18. For this case, the TOP6_TS terminal is tied to the sub-stack composed of cells 7-18 (12 cells total). Changing the TOP6_TS con-nection from 6 to 12 cells requires a modification to the DC2100B-C as discussed in the following paragraph.

Changing the TOP6_TS connection from 6 to 12 cells will reduce the secondary on time of the top six converters in the DC2100B-C. Additionally, the stack overvoltage pro-tection threshold will need to change from a setting that supports 6 series cells to one that will support 12 series

J1 J18 J19

TOP6_TS

BOT6_TS

C12 CELL 24

CELL 18

CELL 13

CELL 12

CELL 6

CELL 1

CAT 5

C1

V–

DC2100B-D

J1 J18 J19

TOP6_TS

BOT6_TS

C12

C1

V–

DC2100B-C

CAT 5 USB

PC

dc2100b F32

Table 6. Connection of Multiple DC2100Bs to Support a Larger Battery Stack

NUMBER OF CELLS WITHIN

SUBSTACK CONNECTED TO TOP6_TS

R23 0Ω JUMPER

RTONS NET RESISTANCE

SECONDARY ON-TIME

HARD LIMIT

TOP6_TS SECONDARY

OVP (RISING)

6Not

populated (as shipped)

47.4kΩ 3.79μs 33.6V

12 Populated 23.7kΩ 1.90μs 65.7V

cells. Changing the value of the resistance connected to the RTONS pin of the top LTC3300-1 (U2) is necessary. This can be done by inserting R23 (0Ω jumper), thereby reduc-ing the resistance at the RTONS pin. Refer to sheet 3 of the schematic. Table 6 summarizes the effect of changing the resistance at RTONS to support 12 cells. Choosing a value for the resistance at the RTONS pin is discussed in the data sheet in the sections, Max On-Time Volt-Sec Clamps and Secondary Winding OVP Function (via WDT pin).

In the example illustrated in Figure 32 two balancers are stacked, and the secondaries interleaved. If this stacking and interleaving is extended beyond the 24 cells, chang-ing the resistance at RTONS will be required for any case where the sub-stack connected to TOP6_TS consists of twelve cells.

21dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDureBalancer Setup for Fewer than Twelve Cells

When balancing fewer than twelve cells, one of the set-up configurations shown in Figure 47 through Figure 54 must be employed to ensure an absent cell location is not interpreted as an undervoltage fault by the GUI. For cases with more than seven cells, but fewer than twelve cells, there is a bias towards placing more (or the same num-ber of) cells on the top LTC3300-1 than on the bottom LTC3300-1. To understand this allocation scheme, con-sider the case of a 12-cell balancer in Figure 33. During balancing, charge is exchanged between individual cells through the primary of a flyback converter to a stack of the same cells through the converter secondary. Within a group of six converters controlled by a single LTC3300, the secondary of the converters are all in parallel. For the lower six converters, the secondary is connected between the bottom of the stack and positive end of cell 12. Thus, during balancing, charge is exchanged between one (or more) of cells 1-6 and the entire stack of 12 cells. How-ever, for the upper six converters the secondary return is connected to C6. Consequently, for the top six cells, bal-ancing exchanges charge between one or more of the top cells and a stack composed of only the top six cells. This constraint drives the system designer towards putting as many cells as possible on the top LTC3300 to maximize the stack size seen by the upper converters. At the same time, the LTC3300 requires at least 9V between C6 and V– for proper operation. Practically speaking, this sets a three-cell minimum for each LTC3300.

Additional Circuitry

Additional circuitry has been added to increase the robust-ness of the design for fault insertions.

Input Protection Diodes

A 10A 200V Schottky diode has been added for a high current path when the connection between battery cells is broken when a battery stack load is present. The 200V reverse voltage rating of the diode was selected to mini-mize the reverse leakage current with cell voltage of 4V. The 10A current rating was selected for its low forward voltage drop which will minimize the current in the parallel diode within the LTC3300-1 as well as surviving the fus-ing current of the 12A cell fuses on the DC2100B.

Figure 33. Connection of a DC2100B to a Twelve-Cell Battery Stack

dc2100b F33

TOP6_TS

C11

C12

PRI SEC

C10

CELLS 7-12

CELLS 1-6

C9

C8

C7

LTC3300U2

V–

BOT6_TS

C5

C6

PRI SEC

C4

C3

C2

C1

C0

LTC3300U1

V–

22dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDureCell-6 Input Disconnection

Two overvoltage-detection circuits have been added to the design that will sense an overvoltage condition on cell 6 or cell 7 and ensure that balancing on both LTC3300-1’s is terminated. This is important in the event of an open fault on the wire connecting the C6 input of the balancer to the battery-stack connection between cell 6 (positive) and cell 7 (negative). See Figure 34. Note in the figure that the voltage between the C5 pin of U1 and the C1 pin of U2 is clamped by the sum of the voltages on cell 6 and cell 7. If cell 6 is being discharged by the DC2100B while the connection between the battery stack and the C6 input of the DC2100B, the voltage across C6A, C6B, the primary input of converter 6, will collapse, causing the voltage of

Figure 34. Fault Scenario Leading to Overvoltage Condition on One LTC3300-1 While Balancing with the Other LTC3300-1

cells 6 plus 7 to appear between the C1 and V– pins of U2, the top LTC3300-1. U2 will sense this overvoltage and stop any balancing operations on U2, but the discharge operation of converter 6 (controlled by U1) will continue. The circuit composed of R56, D8, Q4 and D10 (see the DC2100B schematic) will sense the overvoltage between C1 and V– of the top LTC3300-1 and stop balancing on U1.

Likewise, if cell 7 is discharging in the presence of the aforementioned open fault, the voltage across the primary input of converter 7 will collapse, causing the voltage of cells 6 plus 7 to appear between the C5 and C6 pins of U1. U1 will sense the overvoltage condition and cease

dc2100b F34

LTC3300-1U2

LTC3300-1U1

CONVERTER

TOP6_TS

DC2100B

CELL 8

BOT6_TS

C1C7

C6

C5

V–

8

CONVERTER

5

CONVERTER

C7AC7B

7

CONVERTER

C6AC6B

6

CELL 7

CELL 6

CELL 5

C6X

C5

23dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDurebalancing on U1, but U2 will continue to discharge cell 7. The circuit composed of Q6, D12, R58, Q5, D13 in the DC2100B schematic will sense the overvoltage between C5 and C6 of U1 and stop balancing on U2.

These OVP circuits also protect against analogous fault scenarios when cell 6 or cell 7 is being charged.

Cell Bypass Capacitors

The DC2100B contains bypass capacitors from the cell connections and the stack connections. These capaci-tors have a dual function of smoothing the large triangle current waveforms before the current travels down the interconnecting wires to the cells and they also help bal-ance the voltage between cells when hot-plugging cells in a random order. The RMS current rating of these capaci-tors is a critical parameter for these bypass capacitors as well as their physical size. These large triangle cur-rent waveforms have an RMS content that causes inter-nal heating in the capacitors. Larger-physical-size MLCC capacitors have higher RMS current rating due to their greater surface area to dissipate internal heating. The capacitance of MLCC capacitors decreases with applied voltage and this must be taken into account when select-ing the capacitance value. If a connection is lost during balancing, the differential voltage seen by the LTC3300-1 power circuit on each side of the break may increase or decrease depending on whether the power stage is charg-ing or discharging and where the break occurred. The worst-case scenario is when the balancers on each side of the break are active and balancing in opposite directions. Here the differential voltage will increase rapidly on one side and decrease rapidly on the other. The LTC3300-1 contains an overvoltage protection comparator which monitors the cell voltage and will shut down all balanc-ers before the differential voltage on any cell input reaches the absolute-maximum voltage rating (6V).

Each cell node must have an equivalent capacitance across it to prevent an overvoltage condition when ran-domly connecting cells to the LTC3300-1 battery balancer circuit. In addition to the smoothing capacitors across each balancer power circuit, there are capacitors across the Cx pins of the LTC3300-1 to reduce high frequency noise on these pins, and capacitors across adjacent cells to act as a reservoir of charge for the cell’s MOSFET gate circuit. These reservoir capacitors must also be of equal value to maintain the balancing of voltage, and a capacitor of 2× the value of the reservoir capacitors must be con-nected between C1 and V– of the lowest LTC3300-1 and from the top cell to the cell below it to ensure an equal voltage across all cells when the battery stack is initially connected. Figure 35 and Figure 36 detail these capacitor connections and their values. The reservoir capacitors must be large compared to the capacitors across the Cx pins to force the MOSFET gate driver charging current to flow through the reservoir capacitors. An effective 10:1 ratio between these cell capacitors was selected when considering that a capacitor across two cells would result in a 5:1 ratio.

Temperature Monitor

The DC2100B has the ability to monitor 12 temperature locations within the battery pack. The GUI Control Panel Window, Figure 39, displays these temperatures in two temperature displays, item 16 of Figure 39, for 6 tempera-ture locations. The DC2100B contains a daughter card that can be used to connect twisted pair wires to twelve 10K NTC thermistors, Vishay NTHS0603N01N1002JE or equivalent, within the battery pack. The daughter card is shipped with fixed resistors to simulate temperature readings within a battery pack. These resistor values are selected to display the range of possible temperatures that may be measured. When connecting the daughter card to the actual thermistor, these resistors should be removed and the twisted pair wires connected to the tur-rets provided.

24dc2100bfa

DEMO MANUAL DC2100B

Figure 35. Bypass Capacitors on Lowest LTC3300-1

Figure 36. Bypass Capacitors on the Top LTC3300-1

Quick start proceDure

dc2100b F35

C5

G5P

I5P

C4

G4P

I4P

C3

G3P

I3P

C2

G2P

I2P

G4P

I4P

G3P

I3P

G2P

I2P

C1

C2

C3

C4

C5

C6

G5P

I5P

G6P

I6P

36

3738394041

35

3433

3231

30

29

2827

26

25

2019 21 22 23 24

C6K1µF16V0603

C5K1µF16V0603C4K1µF16V0603C3K1µF16V0603

C2K1µF16V0603

C6 G6P I6PBOOST+BOOST–BOOST

V– C1G1PI1PWDT

G1PI1PWDTA

SDO

C94.7µF16V0805

C114.7µF16V0805

C124.7µF16V0805

C104.7µF16V0805

C1K1µF16V0603

C2310µF10V0805

C144.7µF16V0805

42

C30.1µF16V0402

C40.22µF16V0603

CMMSH2-40R5 R6

6.81

D1D2CMMSH2-40

1

1

2

2

0 OPT

dc2100b F36

C5

G5P

I5P

C4

G4P

I4P

C3

G3P

I3P

C2

G2P

I2P

G10P

I10P

G9P

I9P

G8P

I8P

C7

C5

C8

C9

C10

C11

C12

G11P

I11P

G12P

I12P

36

3738394041

35

3433

3231

30

29

2827

26

25

2019 21 22 23 24

C12K1µF16V0603

C11K1µF16V0603C10K1µF16V0603C9K1µF16V0603

C8K1µF16V0603

C6 G6P I6PBOOST+BOOST–BOOST

V– C1G1PI1PWDT

G7PI7P

C6

WDTC

SDO

C154.7µF16V0805

C174.7µF16V0805

C184.7µF16V0805

C164.7µF16V0805

C2410µF10V0805

C7K1µF16V0603

C204.7µF16V0805

42

C70.1µF16V0402

C80.22µF16V0603

CMMSH2-40R9 R10

6.81

D3D4CMMSH2-40

1

1

2

2

0 OPT

C134.7µF16V0805

25dc2100bfa

DEMO MANUAL DC2100B

Figure 37. Thermistor Board Location

Quick start proceDure

26dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

1. CONTROL PANEL WINDOW – FIGURE 29 (CELLS TAB)

2. CONTROL PANEL WINDOW – FIGURE 30 (GLOBAL CHANNEL MONITOR TAB)

3. CALIBRATION DATA WINDOW – FIGURE 31

4. EVENT LOG WINDOW – FIGURE 32

5. GRAPH VIEW WINDOW – FIGURE 33

6. GRAPH VIEW OPTIONS WINDOW

Figure 38. GUI Navigation

27dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

1. SYSTEM TREE VIEW

2. BOARD STATUS LED

3. SELECTED BOARD INDICATOR

4. BOARD IDENTIFICATION DISPLAY

5. DATA DISPLAY TABS

6. FIRMWARE UPGRADE BUTTON

7. CALIBRATION DATA WINDOW BUTTON

8. EVENT LOG WINDOW BUTTON

9. GRAPH VIEW WINDOW BUTTON

10. DATA LOGGING CONTROLS

11. NOMINAL BALANCE CURRENTS DISPLAY

12. OVER AND UNDER VOLTAGE SETTING CONTROLS

13. VOLTAGE DISPLAY CONTROLS

14. CELL STATE COLOR KEY

15. BOARD CONFIGURATION

16. LTC3300-1 REGISTER DISPLAY (2 INSTANCES FOR 2 ICS ON DC2100B)

17. BALANCE MODE SELECT BOXES (2 GROUPS, WITH 6 CELLS IN EACH GROUP)

18. TEMPERATURE DISPLAY (2 GROUPS, WITH 6 TEMPERATURES IN EACH GROUP)

19. MANUAL AND TIMED BALANCE CONTROLS

Figure 39. Control Panel Window – Cells Tab View

28dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

1. SYSTEM TREE VIEW

2. BOARD STATUS LED

3. SELECTED BOARD INDICATOR

4. BOARD IDENTIFICATION DISPLAY

5. DATA DISPLAY TABS

6. FIRMWARE UPGRADE BUTTON

7. CALIBRATION DATA WINDOW BUTTON

8. EVENT LOG WINDOW BUTTON

9. GRAPH VIEW WINDOW BUTTON

10. DATA LOGGING CONTROLS

11. NOMINAL BALANCE CURRENTS DISPLAY

12. OVER AND UNDER VOLTAGE SETTING CONTROLS

13. CELL VOLTAGE DISPLAY GRID

Figure 40. Control Panel Window – Global Channel Monitor View

29dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 41. Calibration Data Window

Figure 42. Event Log Window

1. CELL CAPACITY DATA GRID

2. BALANCE CURRENT DATA GRID

3. SELECTED BOARD INDICATOR

4. CANCEL BUTTON

5. CELL CAPACITY CALIBRATION CONTROLS

6. BALANCE CURRENT CALIBRATION CONTROLS

1. EVENT LOG DATA

2. LOG CLEAR CONTROL

3. LOG FILE CONTROL

30dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

1. GRAPH DISPLAY

2. STACK SUMMARY DATA SELECTION BOXES

3. BOARD SUMMARY DATA SELECTION BOXES

4. BOARD CELL VOLTAGE SELECTION BOXES

5. BOARD TEMPERATURE SELECTION BOXES

6. GRAPH DATA CONTROLS

7. SELECTED BOARD INDICATOR

Figure 43. Graph View Window

31dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

NOTE: ALL CONNECTIONS FROM EQUIPMENT SHOULD BE KELVIN CONNECTED DIRECTLY TO THE BOARD PINS WHICH THEY ARE CONNECTED TO ON THIS DIAGRAM AND ANY INPUT OR OUTPUT LEADS SHOULD BE TWISTED PAIR WHERE POSSIBLE.

Figure 44. Balancer-to-Stack Connections for 12-Cell Balancing

dc2100b F44

32dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 45. Equipment Setup for Efficiency Measurements with 12 Cells

dc2100b F45

33dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 46. Equipment Setup for Efficiency Measurements with 4 Cells

dc2100b F46

34dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 47. Configuring the Board for 4 Cells

dc2100b F47

35dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 48. Configuring the Board for 5 Cells

dc2100b F48

36dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 49. Configuring the Board for 6 Cells

dc2100b F49

37dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 50. Configuring the Board for 7 Cells

dc2100b F50

38dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 51. Configuring the Board for 8 Cells

dc2100b F51

39dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 52. Configuring the Board for 9 Cells

dc2100b F52

40dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 53. Configuring the Board for 10 Cells

dc2100b F53

41dc2100bfa

DEMO MANUAL DC2100B

Quick start proceDure

Figure 54. Configuring the Board for 11 Cells

dc2100b F54

42dc2100bfa

DEMO MANUAL DC2100B

pcB layout

Top Silk Screen Bottom Silk Screen

dc2100b PCB01dc2100b PCB02

43dc2100bfa

DEMO MANUAL DC2100B

Layer 1

pcB layout

Layer 2

dc2100b PCB03 dc2100b PCB04

44dc2100bfa

DEMO MANUAL DC2100B

pcB layout

Layer 3 Layer 4

dc2100b PCB05 dc2100b PCB06

45dc2100bfa

DEMO MANUAL DC2100B

parts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

Required Circuit Components

1 24 C1A-C12A, C1B-C12B CAP., X5R, 100µF, 6.3V, 20%, 1210 MURATA, GRM32ER60J107ME20L

2 24 C1E-C12E, C1F-C12F CAP., X7R, 470pF, 100V, 10%, 0603 AVX, 06031C471KAT2A

3 12 C1G-C12G CAP., X7R, 2200pF, 50V, 10%, 0402 MURATA, GRM155R71H222KA01D

4 12 C1H-C12H CAP., X7R, 470pF, 50V, 10%, 0402 MURATA, GRM155R71H471KA01D

5 13 C1M-C13M CAP., X7R, 0.01µF, 25V,10%, 0603 MURATA, GRM188R71E103KA01D

6 12 C1R-C12R CAP., X7R, 2.2µF, 100V,10%, 1210 MURATA, GRM32ER72A225KA35L

7 14 C1, C5, C1K-C12K CAP., X7R, 1.0µF, 16V,10%, 0603 MURATA, GRM188R71C105KA12D

8 13 C2, C6, C9-C18, C20 CAP., X5R, 4.7µF, 16V,10%, 1206 MURATA, GRM31CR71C475KA01L

9 2 C3, C7 CAP., X7R, 0.1µF, 16V, 10% 0402 MURATA, GRM155R71C104KA88D

10 2 C4, C8 CAP., X7R, 0.22µF, 16V,10%, 0603 TDK, C1608X7R1C224K

11 2 C19, C22 CAP., X7R, 470pF, 250VAC, 10%, 1808 MURATA, GA342QR7GF471KW01L

12 2 C23, C24 CAP., X7R, 10µF, 10V,10%, 0805 MURATA, GRM21BR71A106K51L

13 2 C25, C26 CAP., X7R, 0.1µF, 100V, 10%, 0805 AVX, 08051C104KAT2A

14 4 C27, C33, C50, C51 CAP., X7R, 0.1µF, 25V,10%, 0603 MURATA, GRM188R71E103KA01D

15 3 C28, C29, C31 CAP., X5R, 1µF, 25V,10%, 0603 TDK, C1608X5R1E105K

16 3 C30, C39, C46 CAP., X5R, 10µF, 6.3V, 20%, 0603 MURATA, GRM188R71C105KA12D

17 6 C34-C38, C45 CAP., X7R, 0.1µF, 16V, 20%, 0402 AVX, 0402YC104MAT2A

18 1 C42 CAP. X5R, 047µF, 16V, 10%, 0402 TDK, C1005X5R1A474K

19 2 C43, C44 CAP, C0G, 22pF, 50V, 0402 MURATA, GRM1555C1H220JZ01D

20 2 C47, C48 CAP., X5R, 1.0µF, 6.3V, 10%, 0603 TAIYO YUDEN, JMK105BJ105KV

21 12 D1E-D12E DIODE, SBR,.200, 10A, POWERDI5 DIODES INC, SBR10U200P5-13

22 4 D1-D4 SMD, SCHOTTKY CENTRAL SEMI, CMMSH2-40

23 3 D5-D7 SMD, SILICON SWITCHING DIODE VISHAY, RS07J

24 2 D8, D12 SMD, SILICON ZENER, 5.1V CENTRAL SEMI, CMHZ4689

25 2 D10, D13 SMD, SCHOTTKY, 70V CENTRAL SEMI, CMOD6263 TR

26 2 D9, D11 DIODE, ZENER 5.6V, 400MW, SOD323 PHILIPS, PDZ5.6B

27 1 D14 DIODE, SWITCHING, 1.0mm × 0.6mm DFN2 DIODES INC, 1N4448HLP

28 25 D1D-D12D, D1F-D12F, D15 LED,GREEN, CLEAR 0603 SMD LITE-ON, LTST-C190KGKT

29 1 D16 LED, YELLOW ORANGE CLEAR 0603 SMD LITE-ON, LTST-C190KFKT

30 13 F1-F12, F15 SMD, FUSE, 12.0A, FAST ACTING, 1206 BUSSMANN, 3216FF12-R

31 2 F13, F14 SMD, FUSE, 7.0A, FAST ACTING, 1206 BUSSMANN, 3216FF7-R

32 1 J1 CONN MOD JACK R/A 8P8C SHIELDED RJ45 WURTH, 615008140121

33 1 J19 USB, B RECEPTACLE, RT, SMT WURTH, 651005136521

34 1 J20 HEADER, 2mm, 2 × 3 TH HEADER WURTH, 62000621121

35 1 J21 HEADER, 2mm, 2 × 8 TH HEADER WURTH, 62501621621

36 1 J22 HEADER, 2mm, 2 × 2, TH HEADER MOLEX, 87831-0420

37 1 PB1 SWITCH TACTILE SPST-NO 0.05A 12V WURTH, 434111025826

38 12 R1A-R12A RES, CHIP, 20Ω, 1/4W, 5%,1206 VISHAY, CRCW120620R0JNEA

39 12 R1B-R12B OPT RES, CHIP,18Ω, 1/4W, 5%, 1206 VISHAY, CRCW120618R0JNEA

40 24 R1C-R12C, R1F-R12F RES, CHIP, 5.1Ω, 1/16W, 5%, 0402 VISHAY, CRCW04025R10JNED

41 24 R1G-R12G, R1H-R12H RES, CHIP, 20Ω, 1/16W, 5%, 0402 VISHAY, CRCW040220R0JNED

46dc2100bfa

DEMO MANUAL DC2100B

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

42 14 R1J-R12J, R56, R58 RES, CHIP, 2.0k, 1/16W, 5%, 0402 VISHAY, CRCW04022K00JNED

43 16 R1K-R13K, R27, R28, R37 RES, CHIP, 100Ω, 1/16W, 5%, 0402 VISHAY, CRCW0402100RJNED

44 12 R1L-R12L RES, CHIP, 470Ω, 1/16W, 5%, 0402 VISHAY, CRCW0402470RJNED

45 12 R1M-R12M RES, CHIP, 33Ω, 1W, 5%, 2512 VISHAY, CRCW251233R0JNEG

46 12 R1N-R12N RES, CHIP, 3.3k, 1/16W, 5%, 0402 VISHAY, CRCW04023K30JNED

47 1 R2 RES, CHIP, 0Ω, JUMPER, 1/16W, 5%, 0402 VISHAY, CRCW04020000Z0ED

48 2 R4, R8 RES, CHIP, 1.27M, 1/8W, 1%, 0805 VISHAY, CRCW08051M27FKED

49 2 R6, R10 RES,CHIP, 6.81Ω, 1/16W, 1%, 0402 VISHAY, CRCW04026R81FKED

50 8 R11-R18 RES, CHIP, 0Ω, 2512 VISHAY, CRCW25120000Z0EG

51 3 R19, R21, R24 RES, CHIP, 23.7k, 1/16W, 1%, 0402 VISHAY, CRCW040223K7FKED

52 2 R20, R22 RES, CHIP, 33.2k, 1/16W, 1%, 0402 VISHAY, CRCW040233K2FKED

53 2 R25, R26 RES, CHIP, 60.4Ω, 1/10W, 1%, 0603 VISHAY, CRCW060360R4FKED

54 2 R29, R63 RES, CHIP, 60.4Ω, 1/16W, 1%, 0402 VISHAY, CRCW040260R4FKED

55 4 R30, R31, R40, R41 RES, CHIP, 1.00M, 1/16W, 5%, 0402 VISHAY, CRCW04021M00JNED

56 2 R32, R39 RES, CHIP, 1.40k, 1/16W, 1%, 0402 VISHAY, CRCW04021K40JKED

57 2 R33, R38 RES, CHIP, 604Ω, 1/16W, 1%, 0402 VISHAY, CRCW0402604RJKED

58 5 R34, R36, R47, R61, R62 RES, CHIP, 2.0k, 1/16W, 5%, 0402 VISHAY, CRCW04022K00JNED

59 1 R35 RES, CHIP, 10k, 1/16W, 1%, 0402 VISHAY, CRCW040210K0FKED

60 6 R42, R43, R50-R52, R60 RES, CHIP, 10.0k, 1/16W, 5%, 0402 VISHAY, CRCW040210K0JNED

61 1 R44 RES, CHIP, 1.0Ω, 1/16W, 5%, 0402 VISHAY, CRCW04021R00JNED

62 1 R49 RES, CHIP, 1.0k, 1/16W, 5%, 0402 VISHAY, CRCW04021K00JNED

63 1 R53 RES, CHIP, 100k, 1/16W, 1%, 0402 VISHAY, CRCW0402100KFKED

64 2 R54, R55 RES, CHIP, 20Ω, 1/10W, 5%, 0603 VISHAY, CRCW060320R0JNEA

65 1 R59 RES, CHIP, 5.1k, 1/16W, 5%, 0402 VISHAY, CRCW04025K10JNED

66 1 R64 RES, CHIP, 2.49k, 1/16W, 1%, 0402 VISHAY, CRCW04022K49FKED

67 1 R65 RES, CHIP, 1.00M, 1/16W, 1%, 0402 VISHAY, CRCW04021M00FKED

68 1 R66 RES, CHIP, 301Ω, 1/10W, 1%, 0603 VISHAY, CRCW0603301RFKED

69 12 RS1A-RS12A RES, CHIP, 5mΩ, 1W, 1%, 1206 SUSUMU, PRL1632-R005-F

70 12 RS1B-RS12B RES, CHIP, 10mΩ, 1W, 1%, 1206 SUSUMU, PRL1632-R010-F

71 12 Q1A-Q12A MOSFET, 100V, 0.0087Ω, 60A, POWERPAK-SO8 VISHAY, SiR882ADP-GE3

72 12 Q1B-Q12B MOSFET, 100V, 0.058Ω, 25A, POWERPAK-1212-8 VISHAY, SiS892ADN-GE3

73 12 Q1C-Q12C MOSFET, P-CHANNEL 30V, 80MΩ, MPAK INFINEON, BSS308PEH6327XT

74 2 Q1, Q2 MOSFET, 100V, 10Ω, SOT-323 DIODES INC, BSS123W-7-F

75 1 Q3 TRANS. NPN, 180V, 0.6A, SOT-223 CENTRAL SEMI, CZT5551

76 1 Q4 TRANS, PNP, 60V, SOT-23 CENTRAL SEMI, CMPT3906E

77 1 Q5 MOSFET, P-CHANNEL 50V, 4Ω, SOT-23 CENTRAL SEMI, CMPDM8002A

78 2 Q6, Q7 TRANS, NPN, 60V, SOT-23 CENTRAL SEMI, CMPT3904E

79 1 Q8 MOSFET, 100V, 10Ω, SOT-323 DIODES INC, BSS123W

80 12 T1-T12 TRANSFORMER, 1:1, 3.0µH, 10.8A WURTH, 750312504

81 1 T13, T15 TRANSFORMER, ISOLATION PULSE ENG., PE-68386NLT

82 1 T14 IND., CHOKE COM MODE 22µH, 1.2kΩ SMD TDK, ACT458-220-2P-TL003

parts list

47dc2100bfa

DEMO MANUAL DC2100B

parts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

83 2 U1, U2 IC, SMT, BIDIRECTIONAL BATTERY BALANCER LINEAR, LTC3300ILXE-1#PBF

84 1 U3 IC, SMT, BATTERY MONITOR LINEAR, LTC6804IG-2#PBF

85 1 U4 IC, SMT, 24AA64 MICROCHIP TECH. 24AA64T-I/OT

86 1 U5 IC, SMT, ISOSPI ISOLATED COMM. INTERFACE LINEAR, LTC6820IMS#PBF

87 2 U6, U7 IC,.SMT, 8-CHANNEL MUX, SSOP-16 LINEAR, LTC1380CGN#PBF

88 1 U8 MODULE, USB ISOLATOR LINEAR, LTM2884CY#PBF

89 1 U9 IC, SMT, MICRO POWER VLDO, 3.3V, SOT23-5 LINEAR, LT1761ES5-3.3#PBF

90 1 U10 14-BIT UC W/USB, 8mm × 8mm QFN44 MICROCHIP, PIC18F47J53-I/ML

91 1 Y1 12MHz CRYSTAL ECS INC, ECS-120-20-3X

Components and Hardware for Demo Board Only

1 15 E1-E15 TURRET, 0.09" MIL-MAX, 2501-2-00-80-00-00-07-0

2 1 J17 HEADER, SMD, 1 × 15, TIN PLATED, RT ANGLE HIROSE, DF3DZ-15P-2(21)

3 6 JP1-JP6 HEADER, 3 PINS, 2mm WURTH, 62000311121

4 6 JP1-JP6 SHUNT 2mm WURTH, 60800213421

5 1 JP7 HEADER, 2.54mm, 3 × 6 THT VERT 18POS SAMTEC, TSW-106-07-L-T

6 1 JP7(MATE) JP7 JUMPER BOARD LINEAR, DC2100-ASSY-1

7 1 J17(MATE) DC2100B THERMISTOR BOARD LINEAR, DC2100B - THERM-1

8 10 STAND-OFF HEX, NYL 8/32 THR 0.25" L KEYSTONE, 1904A

9 10 SCREW, PAN PHILLIPS 8-32 1/4 NYL B&F FASTENER, NY PMS 8320025PH

Optional Components

1 0 C1C-C12C CAP., X5R, 100µF, 6.3V, 10%, 1210 MURATA, GRM32ER60J107ME20L

2 0 C1S-C12S, C1T-C12T CAP., X7R, 2.2µF, 100V, 10%, 1210 MURATA, GRM32ER72A225KA35L

3 0 C1L-C12L OPT CAP., OPT, 100V, 0805

4 0 C21, C32 OPT CAP., X7R, 100pF, 100V, 10%, 0603 AVX, 06031C101KAT

5 0 C40 OPT CAP., X5R, 10µF, 6.3V, 20% 0603 MURATA, GRM188R60J106ME47D

6 0 C49 CAP., OPT, 16V, 0402

7 0 D1A-D12A OPT DIODE, SCHOTTKY 2.0A 60V HI EFFICIENCY DIODES INC, DFLS260-7

8 0 D1B-D12B OPT DIODE, SCHOTTKY 100V 1A BARRIER RECTIFIER POWERDI123

DIODES INC, DFLS1100-7

9 0 D1C-D12C OPT SMD, SCHOTTKY CENTRAL SEMI, CMOSH-4E

10 0 R1, R7 OPT RES, CHIP, 1.00M, 1/16W, 5%, 0402 VISHAY, CRCW04021M00JNED

11 0 R3, R5, R9, R23 OPT RES, CHIP, 0Ω, 0402 VISHAY, CRCW04020000Z0ED

12 0 R45, R46, R48, R57 OPT RES, CHIP, 0Ω, 2512 VISHAY, CRCW25120000Z0EF

13 0 J2, J3, J4, J16 OPT HEADER 1 × 2 WEIDMULLER, 179313000_SC

14 0 J2, J3, J4, J16 (MATE) OPT SOCKET 1 × 2 WEIDMULLER, 1792770000

15 0 J5-J15 OPT HEADER, 1 × 3 WEIDMULLER, 179314000_SC

16 0 J5-J15 (MATE) OPT SOCKET, 1 × 3 WEIDMULLER, 1792780000

48dc2100bfa

DEMO MANUAL DC2100B

parts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

Thermistor Board

1 1 J1 CONN RECEPT 15POS 2mm VERT TIN HIROSE, DF3-15S-2DSA(25)

2 1 R1 RES, CHIP, 340k, 1/16W, 1%, 0402 VISHAY, CRCW0402340KFKED

3 1 R2 RES, CHIP, 54.9k, 1/16W, 1%, 0402 VISHAY, CRCW040254K9FKED

4 1 R3 RES, CHIP, 20k, 1/16W, 1%, 0402 VISHAY, CRCW040220K0FKED

5 1 R4 RES, CHIP, 8.06k, 1/16W, 1%, 0402 VISHAY, CRCW04028K06FKED

6 1 R5 RES, CHIP, 5.36k, 1/16W, 1%, 0402 VISHAY, CRCW04025K36FKED

7 1 R6 RES, CHIP, 3.65k,1/16W,1%, 0402 VISHAY, CRCW04023K65FKED

8 1 R7 RES, CHIP, 2.49k,1/16W,1%, 0402 VISHAY, CRCW04022K49FKED

9 1 R8 RES, CHIP, 1.24k,1/16W,1%, 0402 VISHAY, CRCW04021K24FKED

10 1 R9 RES, CHIP, 909Ω,1/16W,1%, 0402 VISHAY, CRCW0402909RFKED

11 1 R10 RES, CHIP, 681Ω,1/16W,1%, 0402 VISHAY, CRCW0402681RFKED

12 1 R11 RES, CHIP, 301Ω,1/16W,1%, 0402 VISHAY, CRCW0402301RFKED

13 1 R12 RES, CHIP, 147Ω,1/16W,1%, 0402 VISHAY, CRCW0402147RFKED

14 14 E1-E14 TURRET, 0.061" DIA MILL MAX, 2308-2-00-80-00-00-07-0

49dc2100bfa

DEMO MANUAL DC2100B

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2.2uF

1210

100V

C3S

2.2uF

1210

100V

R2A

20 1206

R2A

20 1206

C2R

2.2uF

1210

100V

C2R

2.2uF

1210

100V

C5R

2.2uF

1210

100V

C5R

2.2uF

1210

100V

C1T

2.2uF

1210

100VC1T

2.2uF

1210

100V

C4H

470p

FC4

H47

0pF

T1

WUR

TH-75

0312

504

T1

WUR

TH-75

0312

504

101 2 9

6 7 4 5

Q3B

SiS8

92DN

Q3B

SiS8

92DN

6

4

23

18

5

7

E8

BOT6

_TSE8

BOT6

_TS

D3A

DFLS

260

D3A

DFLS

260

21

R2C 5.1R2C 5.1

C3A

100u

F

1210

6.3V

C3A

100u

F

1210

6.3V

D5C

CMOS

H-4E

D5C

CMOS

H-4E

21

D3B

DFLS

1100

D3B

DFLS

1100

21

R3F

5.1R3F

5.1

R6A 20 1206

R6A 20 1206

C4A

100u

F

1210

6.3V

C4A

100u

F

1210

6.3V

C3F

470p

F10

0V06

03C3F

470p

F10

0V06

03

C6A

100u

F12

106.3

V

C6A

100u

F12

106.3

V

J2 1793

1300

0_SC

J2 1793

1300

0_SC

BOT6

_TS

1BO

T6_T

S2

R5H

20R5H

20

C4E

470p

F10

0V06

03

C4E

470p

F10

0V06

03

RS5B

0.010

RS5B

0.010

21

R4C 5.1R4C 5.1

D5E

SBR1

0U20

0P5

D5E

SBR1

0U20

0P5

213

Q1B

SiS8

92DN

Q1B

SiS8

92DN

6

4

23

18

5

7

R5F 5.1R5F 5.1

C1S

2.2uF

1210

100VC1S

2.2uF

1210

100V

D5A

DFLS

260

D5A

DFLS

260

21

C2S

2.2uF

1210

100V

C2S

2.2uF

1210

100V

D6B

DFLS

1100

D6B

DFLS

1100

21

C2C

100u

F

1210

6.3V

C2C

100u

F

1210

6.3V

C6S

2.2uF

1210

100V

C6S

2.2uF

1210

100V

D2A

DFLS

260

D2A

DFLS

260

21

C4F

470p

F10

0V06

03C4F

470p

F10

0V06

03

D3E

SBR1

0U20

0P5

D3E

SBR1

0U20

0P5

213

C2G

2.2nF

C2G

2.2nF

R1A 20 12

06

R1A 20 12

06

D1C

CMOS

H-4E

D1C

CMOS

H-4E

21

C5S

2.2uF

1210

100V

C5S

2.2uF

1210

100V

C2B

100u

F

1210

6.3V

C2B

100u

F

1210

6.3V

C2F

470p

F10

0V06

03

C2F

470p

F10

0V06

03

R6C 5.1R6C 5.1

R6B

18 1206R6

B

18 1206

T3

WUR

TH-75

0312

504

T3

WUR

TH-75

0312

504

101 2 9

6 7 4 5

R2F 5.1R2F 5.1

C1A

100u

F

1210

6.3V

C1A

100u

F

1210

6.3V

C6E

470p

F10

0V06

03

C6E

470p

F10

0V06

03

C5E

470p

F10

0V06

03

C5E

470p

F10

0V06

03

C4S

2.2uF

1210

100V

C4S

2.2uF

1210

100V

R4F 5.1R4F 5.1

Q3A

SiR8

82DP

Q3A

SiR8

82DP

6

4

23

18

5

7

D2C

CMOS

H-4E

D2C

CMOS

H-4E

21

RS6A

0.005

RS6A

0.005

21

C3T

2.2uF

1210

100VC3

T2.2

uF12

1010

0V

R5G

20R5G

20

T2

WUR

TH-75

0312

504

T2

WUR

TH-75

0312

504

101 2 9

6 7 4 5

C3R

2.2uF

1210

100V

C3R

2.2uF

1210

100V

R6F

5.1R6F

5.1

F13

7A 1206

F13

7A 1206

C2H

470p

FC2

H47

0pF

D4B

DFLS

1100

D4B

DFLS

1100

21

R5A

20 1206

R5A

20 1206

C3H

470p

FC3

H47

0pF

R3H

20R3H

20

C1F

470p

F10

0V06

03C1F

470p

F10

0V06

03

RS3A

0.005

RS3A

0.005

21

C3E

470p

F

100V 0603

C3E

470p

F

100V 0603

D6C

CMOS

H-4E

D6C

CMOS

H-4E

21

RS6B

0.010

RS6B

0.010

21

R1B

18 1206

R1B

18 1206

Q4B

SiS8

92DN

Q4B

SiS8

92DN

6

4

23

18

5

7

D6E

SBR1

0U20

0P5

D6E

SBR1

0U20

0P5

213

D4C

CMOS

H-4E

D4C

CMOS

H-4E

21

D3C

CMOS

H-4E

D3C

CMOS

H-4E

21

Q6B

SiS8

92DN

Q6B

SiS8

92DN

6

4

23

18

5

7

Q1A

SiR8

82DP

Q1A

SiR8

82DP

6

4

23

18

5

7

Q2A

SiR8

82DPQ2

ASi

R882

DP

6

4

23

18

5

7

C4B

100u

F

1210

6.3V

C4B

100u

F

1210

6.3V

R5C 5.1R5C 5.1

C1E

470p

F10

0V06

03

C1E

470p

F10

0V06

03

R2B

18 1206

R2B

18 1206

R1C 5.1R1C 5.1

C6B

100u

F

1210

6.3V

C6B

100u

F

1210

6.3V

C6F

470p

F10

0V06

03C6F

470p

F10

0V06

03

T6

WUR

TH-75

0312

504

T6

WUR

TH-75

0312

504

101 2 9

6 7 4 5

C3B

100u

F

1210

6.3V

C3B

100u

F

1210

6.3V

C5A

100u

F

1210

6.3V

C5A

100u

F

1210

6.3V

D1A

DFLS

260

D1A

DFLS

260

21C2E

470p

F

100V

0603

C2E

470p

F

100V

0603

R6G

20R6

G20

C2T

2.2uF

1210

100V

C2T

2.2uF

1210

100V

RS4B

0.010

RS4B

0.010

21

T4

WUR

TH-75

0312

504

T4

WUR

TH-75

0312

504

101 2 9

6 7 4 5

C6H

470p

FC6

H47

0pF

R2H

20R2H

20

D4A

DFLS

260

D4A

DFLS

260

21

R3C 5.1R3C 5.1

C6R

2.2uF

1210

100V

C6R

2.2uF

1210

100V

C4R

2.2uF

1210

100V

C4R

2.2uF

1210

100V

R3G

20R3G

20

RS1B

0.010

RS1B

0.010

21

C1G

2.2nFC1G

2.2nF

C5G

2.2nFC5G

2.2nF

C1R

2.2uF

1210

100V

C1R

2.2uF

1210

100V

C3C

100u

F

1210

6.3V

C3C

100u

F

1210

6.3V

C5H

470p

FC5

H47

0pF

D1B

DFLS

1100D1B

DFLS

1100

21

D4E

SBR1

0U20

0P5

D4E

SBR1

0U20

0P5

213

RS2A

0.005

RS2A

0.005

21

R4G 20R4G 20

D5B

DFLS

1100

D5B

DFLS

1100

21

R6H 20R6H 20

C3G

2.2nF

C3G

2.2nF

R3A

20 1206

R3A

20 1206

Q5B

SiS8

92DN

Q5B

SiS8

92DN

6

4

23

18

5

7

D6A

DFLS

260

D6A

DFLS

260

21

Q2B

SiS8

92DN

Q2B

SiS8

92DN

6

4

23

18

5

7

C1C

100u

F

1210

6.3V

C1C

100u

F

1210

6.3V

C6C

100u

F

1210

6.3V

C6C

100u

F

1210

6.3V

R1F

5.1R1F

5.1

T5

WUR

TH-75

0312

504

T5

WUR

TH-75

0312

504

101 2 9

6 7 4 5

RS2B

0.010

RS2B

0.010

21

D2B

DFLS

1100

D2B

DFLS

1100

21

R4B

18 1206

R4B

18 1206

50dc2100bfa

DEMO MANUAL DC2100B

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OPT

OPT

OPT

*

PLAC

E RC

CLO

SE TO

LTC3

300

OPT

OPT

*

PLAC

E RC

CLO

SE TO

LTC3

300

OPT

OPT

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

*PL

ACE

RC C

LOSE

TO LT

C330

0

OPT

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

*

OPT

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

OPT

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

PLAC

E RC

CLO

SE TO

LTC3

300

*

OPT

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

PLAC

E RC

CLO

SE TO

LTC3

300

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

*

OPT

PLAC

E RC

CLO

SE TO

LTC3

300

OPT

OPT

OPT

OPT

*

OPT

OPT

OPT

*

OPT

OPT

*

OPT

OPT

OPT

*

OPT

OPT

OPT

*

OPT

OPT

OPT

*

**

**

**

**

**

**

RS1A

-RS1

2ARS

1B-R

S12B

0.008

R1B-

R12B

0.005

C1F-

C12F

0.016

0.010

NPNP

18DC

2100

B - A

/ BDC

2100

B - C

/ D47

0pF

*

TOP6

_TS

C11

TOP6

_TS

C6

C10

TOP6

_TS

C9

TOP6

_TS

C7

C11

C6

C9

C6

C8

C6

C6

C8

TOP6

_TS

C6

C10

C12

C7

TOP6

_TS

I7P

G10P

G8P

I7S

G11S

G9S

I10P

C9

I11S

C8

G10S

G11P

G9P

C10

I8P

I12P

I9P

C12

I11P

G12P

I9S

C7

C11

I12S

G7P

TOP6

_TS

I10S

G7S

C6

G12S

G8S

I8S

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

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CIRC

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THAT

MEE

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MER-

SUPP

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SPE

CIFI

CATI

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HOW

EVER

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EMAI

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MER'

S RE

SPON

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LITY

TO

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ROPE

R AN

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LIAB

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TION

IN T

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LAP

PLIC

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N. C

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SUB

STIT

UTIO

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D PR

INTE

DCI

RCUI

T BO

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LAYO

UT M

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FICA

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AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

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ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

26

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

GN A

CIRC

UIT

THAT

MEE

TS C

USTO

MER-

SUPP

LIED

SPE

CIFI

CATI

ONS;

HOW

EVER

, IT R

EMAI

NS T

HE C

USTO

MER'

S RE

SPON

SIBI

LITY

TO

VERI

FY P

ROPE

R AN

D RE

LIAB

LE O

PERA

TION

IN T

HE A

CTUA

LAP

PLIC

ATIO

N. C

OMPO

NENT

SUB

STIT

UTIO

N AN

D PR

INTE

DCI

RCUI

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LAYO

UT M

AY S

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FICA

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AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

OR R

ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

26

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

GN A

CIRC

UIT

THAT

MEE

TS C

USTO

MER-

SUPP

LIED

SPE

CIFI

CATI

ONS;

HOW

EVER

, IT R

EMAI

NS T

HE C

USTO

MER'

S RE

SPON

SIBI

LITY

TO

VERI

FY P

ROPE

R AN

D RE

LIAB

LE O

PERA

TION

IN T

HE A

CTUA

LAP

PLIC

ATIO

N. C

OMPO

NENT

SUB

STIT

UTIO

N AN

D PR

INTE

DCI

RCUI

T BO

ARD

LAYO

UT M

AY S

IGNI

FICA

NTLY

AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

OR R

ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

26

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

Q9A

SiR8

82DP

Q9A

SiR8

82DP

6

4

23

18

5

7

J3 1793

1300

0_SC

J3 1793

1300

0_SC

TOP6

_TS

1TO

P6_T

S2

R9A

20 1206

R9A

20 1206

C9R

2.2uF

1210

100V

C9R

2.2uF

1210

100V

RS9A

0.005

RS9A

0.005

21

T11

WUR

TH-75

0312

504

T11

WUR

TH-75

0312

504

101 2 9

6 7 4 5

D9C

CMOS

H-4E

D9C

CMOS

H-4E

21

C10E

470p

F10

0V06

03

C10E

470p

F10

0V06

03

T8

WUR

TH-75

0312

504

T8

WUR

TH-75

0312

504

101 2 9

6 7 4 5

C7E

470p

F10

0V06

03

C7E

470p

F10

0V06

03

RS10

A0.0

05RS

10A

0.005

21

D12B

DFLS

1100

D12B

DFLS

1100

21

C7F

470p

F10

0V06

03C7F

470p

F10

0V06

03

R7C 5.1R7C 5.1

R10C 5.1R10C 5.1

R9C 5.1R9C 5.1

C9H

470p

FC9

H47

0pF

F14

7A 1206

F14

7A 1206

R9G

20R9G

20

R11B 18 1206

R11B 18 1206

R8B

18 1206

R8B

18 1206

R7F 5.1

R7F 5.1

R12C 5.1R12C 5.1

D10E

SBR1

0U20

0P5

D10E

SBR1

0U20

0P5

213

D11B

DFLS

1100

D11B

DFLS

1100

21

R10F 5.1R10F 5.1

R12A 20 1206

R12A 20 1206

D11C

CMOS

H-4E

D11C

CMOS

H-4E

21

C7G

2.2nFC7G

2.2nF

R10H 20R10H 20

C8C

100u

F

1210

6.3V

C8C

100u

F

1210

6.3V

C9F

470p

F10

0V06

03C9F

470p

F10

0V06

03

C8G

2.2nF

C8G

2.2nF

R11H

20R11H

20

C11E

470p

F10

0V06

03

C11E

470p

F10

0V06

03

C10B

100u

F

1210

6.3V

C10B

100u

F

1210

6.3V

R11A

20 1206

R11A

20 1206

C9T

2.2uF

1210

100VC9

T2.2

uF12

1010

0V

D12A

DFLS

260

D12A

DFLS

260

21

R11G 20R11G 20

D7B

DFLS

1100

D7B

DFLS

1100

21

C9S

2.2uF

1210

100V

C9S

2.2uF

1210

100V

C12B

100u

F

1210

6.3V

C12B

100u

F

1210

6.3V

D9A

DFLS

260

D9A

DFLS

260

21

R8A

20 1206

R8A

20 1206

T10

WUR

TH-75

0312

504

T10

WUR

TH-75

0312

504

101 2 9

6 7 4 5

C12H

470p

FC1

2H47

0pF

C11H

470p

FC1

1H47

0pF

C10C

100u

F

1210

6.3V

C10C

100u

F

1210

6.3V

R10G 20R10G 20

D11E

SBR1

0U20

0P5

D11E

SBR1

0U20

0P5

213

C7A

100u

F

1210

6.3V

C7A

100u

F

1210

6.3V

T12

WUR

TH-75

0312

504

T12

WUR

TH-75

0312

504

101 2 9

6 7 4 5

Q11A

SiR8

82DPQ1

1ASi

R882

DP

6

4

23

18

5

7

C9E

470p

F

100V 0603

C9E

470p

F

100V 0603

R8H

20R8H

20R8

G 20R8G 20 R7G 20R7G 20

C10T

2.2uF

1210 100V

C10T

2.2uF

1210 100V

Q8A

SiR8

82DPQ8

ASi

R882

DP

6

4

23

18

5

7D1

2CCM

OSH-

4ED1

2CCM

OSH-

4E

21

R10B

18 1206

R10B

18 1206

C12R

2.2uF

1210

100V

C12R

2.2uF

1210

100V

Q12A

SiR8

82DP

Q12A

SiR8

82DP

6

4

23

18

5

7

C8R

2.2uF

1210

100V

C8R

2.2uF

1210

100V

R12F 5.1R12F 5.1

C10H

470p

FC1

0H47

0pF

C10S

2.2uF

1210

100V

C10S

2.2uF

1210

100V

C11B

100u

F

1210

6.3V

C11B

100u

F

1210

6.3V

Q7A

SiR8

82DP

Q7A

SiR8

82DP

6

4

23

18

5

7

D7E

SBR1

0U20

0P5

D7E

SBR1

0U20

0P5

213

D7C

CMOS

H-4E

D7C

CMOS

H-4E

21

Q10B

SiS8

92DN

Q10B

SiS8

92DN

6

4

23

18

5

7

C9C

100u

F

1210

6.3V

C9C

100u

F

1210

6.3V

RS10

B0.0

10RS

10B

0.010

21

C8E

470p

F

100V

0603

C8E

470p

F

100V

0603

C12T

2.2uF

1210

100V

C12T

2.2uF

1210

100V

R9F 5.1R9F 5.1

D8E

SBR1

0U20

0P5

D8E

SBR1

0U20

0P5

213

D11A

DFLS

260

D11A

DFLS

260

21

C10A

100u

F

1210

6.3V

C10A

100u

F

1210

6.3V

C11R

2.2uF

1210

100V

C11R

2.2uF

1210

100V

C11F

470p

F10

0V06

03

C11F

470p

F10

0V06

03

E15

TOP6

_TS

E15

TOP6

_TS

R12G 20R12G 20

RS7A

0.005

RS7A

0.005

21

C7T

2.2uF

1210

100VC7T

2.2uF

1210

100V

D9B

DFLS

1100

D9B

DFLS

1100

21

Q9B

SiS8

92DN

Q9B

SiS8

92DN

6

4

23

18

5

7

C8A

100u

F

1210

6.3V

C8A

100u

F

1210

6.3V

D8C

CMOS

H-4E

D8C

CMOS

H-4E

21

C11C

100u

F

1210

6.3V

C11C

100u

F

1210

6.3V

C12A

100u

F12

106.3

V

C12A

100u

F12

106.3

V

C8T

2.2uF

1210

100V

C8T

2.2uF

1210

100V

RS11

B0.0

10RS

11B

0.010

21

RS7B

0.010

RS7B

0.010

21

R7A

20 1206

R7A

20 1206

C8B

100u

F

1210

6.3V

C8B

100u

F

1210

6.3V

C11G

2.2nFC11G

2.2nF

C12G

2.2nF

C12G

2.2nF

D7A

DFLS

260

D7A

DFLS

260

21

C10R

2.2uF

1210

100V

C10R

2.2uF

1210

100V

C7R

2.2uF

1210

100V

C7R

2.2uF

1210

100V

C8S

2.2uF

1210

100V

C8S

2.2uF

1210

100V

C8F

470p

F10

0V06

03C8F

470p

F10

0V06

03

D8B

DFLS

1100

D8B

DFLS

1100

21

C11T

2.2uF

1210

100V

C11T

2.2uF

1210

100V

C12E 47

0pF

100V

0603

C12E 47

0pF

100V

0603

C12S

2.2uF

1210

100V

C12S

2.2uF

1210

100V

RS8B

0.010

RS8B

0.010

21

Q12B

SiS8

92DN

Q12B

SiS8

92DN

6

4

23

18

5

7

RS9B

0.010

RS9B

0.010

21

RS8A

0.005

RS8A

0.005

21

C8H

470p

FC8

H47

0pF

R8C 5.1R8C 5.1

C12C

100u

F

1210

6.3V

C12C

100u

F

1210

6.3V

R8F 5.1R8F 5.1

C7B

100u

F

1210

6.3V

C7B

100u

F

1210

6.3V

Q7B

SiS8

92DN

Q7B

SiS8

92DN

6

4

23

18

5

7Q8

BSi

S892

DNQ8

BSi

S892

DN6

4

23

18

5

7

D9E

SBR1

0U20

0P5

D9E

SBR1

0U20

0P5

213

R7H

20R7H

20

T7

WUR

TH-75

0312

504

T7

WUR

TH-75

0312

504

101 2 9

6 7 4 5

R12B

18 1206

R12B

18 1206

Q10A

SiR8

82DP

Q10A

SiR8

82DP

6

4

23

18

5

7

C10F

470p

F10

0V06

03

C10F

470p

F10

0V06

03

R11F 5.1R11F 5.1

D12E

SBR1

0U20

0P5

D12E

SBR1

0U20

0P5

213

C7H

470p

FC7

H47

0pF

C12F

470p

F10

0V06

03C12F

470p

F10

0V06

03

R11C 5.1R11C 5.1

R9H 20R9H 20

C7C

100u

F

1210

6.3V

C7C

100u

F

1210

6.3V

C10G

2.2nF

C10G

2.2nF

R10A 20 1206

R10A 20 1206

R9B

18 1206

R9B

18 1206

D8A

DFLS

260

D8A

DFLS

260

21C9

G2.2

nFC9

G2.2

nF

Q11B

SiS8

92DN

Q11B

SiS8

92DN

6

4

23

18

5

7

C11S

2.2uF

1210

100V

C11S

2.2uF

1210

100V

RS11

A0.0

05RS

11A

0.005

21

C9B

100u

F

1210

6.3V

C9B

100u

F

1210

6.3V

T9

WUR

TH-75

0312

504

T9

WUR

TH-75

0312

504

101 2 9

6 7 4 5

RS12

B0.0

10RS

12B

0.010

21

C9A

100u

F

1210

6.3V

C9A

100u

F

1210

6.3V

D10B

DFLS

1100

D10B

DFLS

1100

21

D10A

DFLS

260

D10A

DFLS

260

21

C7S

2.2uF

1210

100VC7S

2.2uF

1210

100V

D10C

CMOS

H-4E

D10C

CMOS

H-4E

21

RS12

A0.0

05RS

12A

0.005

21

R12H 20R12H 20

C11A

100u

F

1210

6.3V

C11A

100u

F

1210

6.3V

R7B

18 1206

R7B

18 1206

51dc2100bfa

DEMO MANUAL DC2100B

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

2512

2512

2010

2512

2512

2512 25

12

OPT

From

U3 P

in 32

0402

0402

From

U3 P

in 33

From

U3 P

in 29

OPT

OPT

OPT

2512

OPT

OPT

R19

R20

15.4k

R21

23.7k

R24

20.5k 33.2k

15.4k

15.4k

23.7K

DC21

00B

- A / B

DC21

00B

- C / D

R22

20.5k

R4R8

845k

845k

1.27M

33.2k

23.7K

1.27M

*

*

**

*

*

*

*

V-

VREG

2

WDTA

WDTC

C6

V-

C6

C6

C5

VREG

1

C7 C6

C5

WDT

A

WDT

C

C6

C6

V-

VREG

1

C12

C6

I2SI3P

C10

SDIO

C5

I9SI11S

G7S

G4S

C9

C3

I1S

G10S

G3S

I5P

C6

G2S

G11P

G8S I7S

I10S

I5S

C2G1

SI6S

G1P

C11

I3S

I1P

I11P

G4P

I8P

G9S

I4S

I10P

G6S

I7P

G12P

C4

BOT6

_TS

C7

I2P

G8P

G12S

G2P

I12P

G5S

CSB

C1

SCKB

V-

G10P

G11S

G5P

G9P

TOP6

_TS

I8S

G3P

I9P

G6P

I6P

C8

G7P

I4P

I12S

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

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Conf

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Use

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CUST

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HIGH

EFF

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BIDI

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N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

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NC J. DR

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10 -

8 - 14

MUL

TICE

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ATTE

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ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

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ENG.

TEC

HN

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GY

Fax:

(408

)434

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7

Milp

itas,

CA 95

035

Phon

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08)4

32-1

900

1630

McC

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Conf

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tial-F

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Use

Onl

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CUST

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NOT

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300I

LXE-

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TC68

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NC J. DR

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10 -

8 - 14

MUL

TICE

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ATTE

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ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

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ENG.

TEC

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(408

)434

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Use

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CUST

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DEM

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BIDI

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LXE-

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10 -

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MUL

TICE

LL B

ATTE

RY B

ALAN

CER

C23

10uF

10V

0805

C23

10uF

10V

0805

D1

CMMS

H2-40

D1

CMMS

H2-40

21

R8 1.27M

0805R8 1.27M

0805

C11K

1.0uF

16V

0603

C11K

1.0uF

16V

0603

R54

20 0603

R54

20 0603

C15

4.7uF

16V

1210C1

54.7

uF16

V12

10

D5 RS07

JD5 RS

07J

1 2

R1 1MR1 1M

C20

4.7uF 16V

1210C20

4.7uF 16V

1210

C17

4.7uF 16V

1210C17

4.7uF 16V

1210

Q2BS

S123

WQ2BS

S123

W

3

1

2

TP1

WDT

A

TP1

WDT

A

D3

CMMS

H2-40

D3

CMMS

H2-40

21

R7 1MR7 1M

R11

0R11

0

Q5 CMPD

M800

2AQ5 CM

PDM8

002A

2

1

3

R15

0R15

0

U1LT

C330

0-1U1

LTC3

300-1

G6S

1

I6S2

G5S

3

I5S4

G4S

5

I4S6

G3S

7

I3S8

G2S

9

I2S10

G1S

11

I1S12

RTONS 13

RTONP 14

CTRL 15

CSBI 16

SCKI 17

SDI 18

SDO 19

WDT 20

V- 21

I1P 22

G1P 23

C1 24

I2P25

G2P

26C2

27I3P

28G3

P29

C330

I4P31

G4P

32C4

33I5P

34G5

P35

C536

I6P37G6P38

C639BOOST+40BOOST-41BOOST42

SDOI43SCKO44CSBO45

VMODE46TOS47

VREG48

GND

49

R18 0R18 0

D9 PDZ5

.6BD9 PD

Z5.6B

21

R16

0R16

0

C18

4.7uF 16V

1210

C18

4.7uF 16V

1210

R20

33.2kR20

33.2k

C6K

1.0uF 16V

0603C6K

1.0uF 16V

0603

C4K

1.0uF

16V

0603

C4K

1.0uF

16V

0603

Q4CM

PT39

06E

Q4CM

PT39

06E

1

32

D7 RS07

JD7 RS

07J

1 2

C7K

1.0uF 16V

0603

C7K

1.0uF 16V

0603

D12

CMHZ

4689

D12

CMHZ

4689

21

R9 0R9 0

D6 RS07

JD6 RS

07J

1 2

C11

4.7uF

16V

1210

C11

4.7uF

16V

1210

R56

2.0k

R56

2.0k

C4 0.22u

F16

V06

03C4 0.22u

F16

V06

03

C7 0.1uF

16VC7 0.1uF

16V

C10

4.7uF

16V

1210

C10

4.7uF

16V

1210

C10K

1.0uF

16V

0603

C10K

1.0uF

16V

0603

C14

4.7uF

16V

1210

C14

4.7uF

16V

1210

R2 0R2 0

R22

33.2kR2

233

.2k

C9K

1.0uF

16V

0603C9K

1.0uF

16V

0603

R58

2.0k

R58

2.0k

R5 0R5 0

R21

23.7kR2

123

.7k

R19

23.7kR1

923

.7k

C2 4.7uF

16V

1210

C2 4.7uF

16V

1210

D10

CMOD

6263

D10

CMOD

6263

2 1

R55

20 0603R5

520 0603

R6 6.81

R6 6.81

C6 4.7uF

16V

1210

C6 4.7uF

16V

1210

R17

0R17

0

C12K

1.0uF 16V

0603

C12K

1.0uF 16V

0603

C3 0.1uF

16VC3 0.1uF

16V

C3K

1.0uF

16V

0603C3K

1.0uF

16V

0603

C16

4.7uF

16V

1210

C16

4.7uF

16V

1210

D4 CMMS

H2-40

D4 CMMS

H2-40

21

R12

0R12

0

C12

4.7uF

16V

1210

C12

4.7uF

16V

1210

Q1BS

S123

WQ1BS

S123

W

3

1

2

R24

23.7k

R24

23.7k

R14

0R14

0C2

K1.0

uF 16V

0603C2

K1.0

uF 16V

0603

C9 4.7uF

16V

1210C9 4.7uF

16V

1210

R3 0R3 0C1 1.0

uF16

V06

03

C1 1.0uF

16V

0603

R4 1.27M

0805R4 1.27M

0805

R47

2.0K

R47

2.0K

C8K

1.0uF

16V

0603

C8K

1.0uF

16V

0603

R23

0R23

0

D11

PDZ5

.6BD1

1PD

Z5.6B

21

C13

4.7uF

16V

1210C13

4.7uF

16V

1210

C5 1.0uF

16V

0603

C5 1.0uF

16V

0603

D8 CMHZ

4689

D8 CMHZ

4689

21

R10

6.81

R10

6.81

R13

0R13

0

D13

CMOD

6263

D13

CMOD

6263

21

C5K

1.0uF 16V

0603

C5K

1.0uF 16V

0603

D2 CMMS

H2-40

D2 CMMS

H2-40

21

Q6 CMPT

3904

EQ6 CM

PT39

04E

1

23

C1K

1.0uF

16V

0603C1K

1.0uF

16V

0603

U2LT

C330

0-1U2

LTC3

300-1

G6S

1

I6S2

G5S

3

I5S4

G4S

5

I4S6

G3S

7

I3S8

G2S

9

I2S10

G1S

11

I1S12

RTONS 13

RTONP 14

CTRL 15

CSBI 16

SCKI 17

SDI 18

SDO 19

WDT 20

V- 21

I1P 22

G1P 23

C1 24

I2P25

G2P

26C2

27I3P

28G3

P29

C330

I4P31

G4P

32C4

33I5P

34G5

P35

C536

I6P37G6P38

C639BOOST+40BOOST-41BOOST42

SDOI43SCKO44CSBO45

VMODE46TOS47

VREG48

GND

49

C8 0.22u

F16

V06

03C8 0.22u

F16

V06

03

TP2

WDT

CTP

2W

DTC

R53

100kR5

3

100k

C24

10uF

10V

0805

C24

10uF

10V

0805

52dc2100bfa

DEMO MANUAL DC2100B

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

OPTI

ONAL

PAS

SIVE

BAL

ANCI

NG C

IRCU

ITS

C12 K

ELVI

N

F1 -

F12 ,

F15

7ADC

2100

B - C

/ DDC

2100

B - A

/ B12

A

*

*

**

*

**

*

* *

**

*

*

C11_

FILT

ER

C5_F

ILTE

R

C2

C10_

FILT

ER

C5C1

C8

C4_F

ILTE

R

C1

C9C4

C7

C9_F

ILTE

R

C9

C10

C6

C3

C7_F

ILTE

R

C3_F

ILTE

R

C12

C4

V-

C12

C8

C11

C6

C8_F

ILTE

R

C2

C7

C10

C6_F

ILTE

R

C5C11

C3

C2_F

ILTE

R

C12_

FILT

ER

C1

V-C1

C2

C2

C3

C3

C4

C4

C5

C5

C6

C6

C7

C7

C8

C8

C9

C9

C10C1

0

C11C1

1

C12

C0_F

ILTE

R

C1_F

ILTE

R

V- V-V-V- V-V- V- V-V-V-

V-

V-

V-

C3

C2

C5_F

ILTER

C9_F

ILTER

C5

C11_

FILTE

R

C6_F

ILTER

C2_F

ILTER

C10

C11

V-C3

C4

C1_F

ILTER

C10_

FILTE

R

C9

C8_F

ILTER

C2 C1C7 C6C11

C7

C4_F

ilter

C4

C7_F

ILTER

C12

C3_F

ILTER

C1

C10

C5

C8

V-

C8

C12_

FILTE

R

C6

C9

G1P

G2P

G3P

G4P

G5P

G6P

G7P

G8P

G9P

G10P

G11P

G12P

S1S2

S3S4S5S6S7S8S9S10

S11

S12

C0_F

ILTER

SIZE

DATE

:

IC N

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V.

SHEE

TOF

TITL

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APPR

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PCB

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Fax:

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300I

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1 / L

TC68

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10 -

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MUL

TICE

LL B

ATTE

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ALAN

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SIZE

DATE

:

IC N

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SHEE

TOF

TITL

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DEM

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RCUI

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HIGH

EFF

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BIDI

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IONA

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LTC3

300I

LXE-

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10 -

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MUL

TICE

LL B

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C8L

OPT

0805

C8L

OPT

0805

R8J

2.00k

R8J

2.00k

D6F

GRN

LED-

LND6

FGR

NLE

D-LN

R8M

33 2512

R8M

33 2512

E13

C11

E13

C11

C11M

10nF

25V

0603

C11M

10nF

25V

0603

F2

12A

1206

F2

12A

1206

J11

1793

1400

0_SC

J11

1793

1400

0_SC

C7S+

1C7

+2

C8S-

3

C4M

10nF

25V

0603

C4M

10nF

25V

0603

R1M

33 2512

R1M

33 2512

R12K 100

R12K 100

R8L

470R8

L

470

D8D

GRN

LED-

LND8

DGR

NLE

D-LN

Q2C

RQJ0

303P

GDQA

LTQ2

CRQ

J030

3PGD

QALT

2

1

3

R9N

3.3KR9

N

3.3K

F6

12A

1206

F6

12A

1206

R5J

2.00k

R5J

2.00k

R11N

3.3KR1

1N

3.3K

R8K

100

R8K

100

R6J

2.00kR6

J

2.00k

Q4C

RQJ0

303P

GDQA

LTQ4

CRQ

J030

3PGD

QALT

2

1

3

J8 1793

1400

0_SC

J8 1793

1400

0_SC

C4S+

1C4

+2

C5S-

3

J5 1793

1400

0_SC

J5 1793

1400

0_SC

C1S+

1C1

+2

C2S-

3

E9C7

E9C7

R4M

33 2512

R4M

33 2512

R11K 100

R11K 100

R1K

100

R1K

100

R2M

33 2512

R2M

33 2512

D9F

GRN

LED-

LND9

FGR

NLE

D-LN

F10 12

A

1206

F10 12

A

1206

D11F

GRN

LED-

LND1

1FGR

NLE

D-LN

R4L

470R4

L

470

E12

C10

E12

C10

C1L

OPT

0805

C1L

OPT

0805

R1N

3.3KR1

N

3.3K

R2L

470

R2L

470

C10M

10nF

25V

0603

C10M

10nF

25V

0603

Q1C

RQJ0

303P

GDQA

LTQ1

CRQ

J030

3PGD

QALT

2

1

3

C9L

OPT

0805

C9L

OPT

0805

R12N

3.3KR1

2N

3.3K

Q7C

RQJ0

303P

GDQA

LTQ7

CRQ

J030

3PGD

QALT

2

1

3

F1

12A12

06F1

12A12

06

D5D

GRN

LED-

LND5

DGR

NLE

D-LN

D12F

GRN

LED-

LND1

2FGR

NLE

D-LN

R3J

2.00kR3J

2.00k

R5K

100

R5K

100

R3N

3.3KR3

N

3.3K

D11D

GRN

LED-

LND1

1DGR

NLE

D-LN

C13M

10nF

25V

0603

C13M

10nF

25V

0603

R4J

2.00k

R4J

2.00k

R1L

470

R1L

470

C1M

10nF

25V

0603

C1M

10nF

25V

0603

E1V-

E1V-

R7M

33 2512

R7M

33 2512

E11

C9E1

1C9

Q5C

RQJ0

303P

GDQA

LTQ5

CRQ

J030

3PGD

QALT

2

1

3

F5

12A12

06F5

12A12

06

J13

1793

1400

0_SC

J13

1793

1400

0_SC

C9S+

1C9

+2

C10S

-3

C10L

OPT

0805

C10L

OPT

0805

D3F

GRN

LED-

LND3

FGR

NLE

D-LN

D12D

GRN

LED-

LND1

2DGR

NLE

D-LN

R3K

100

R3K

100

R12J

2.00k

R12J

2.00k

C5L

OPT

0805

C5L

OPT

0805

E14

C12

E14

C12

C7M

10nF

25V

0603

C7M

10nF

25V

0603

F9

12A12

06F9

12A12

06

R7L

470R7

L

470

E4C3

E4C3

J10

1793

1400

0_SC

J10

1793

1400

0_SC

C6S+

1C6

+2

C7S-

3

R5M

33 2512

R5M

33 2512

Q6C

RQJ0

303P

GDQA

LTQ6

CRQ

J030

3PGD

QALT

2

1

3

C3L

OPT

0805

C3L

OPT

0805

R6M

33 2512

R6M

33 2512

R10N

3.3KR1

0N

3.3K

C9M

10nF

25V

0603

C9M

10nF

25V

0603

E3C2

E3C2

R5L

470R5

L

470

J7 1793

1400

0_SC

J7 1793

1400

0_SC

C3S+

1C3

+2

C4S-

3

Q9C

RQJ0

303P

GDQA

LTQ9

CRQ

J030

3PGD

QALT

2

1

3

R13K

100

R13K

100

D3D

GRN

LED-

LND3

DGR

NLE

D-LN

E7C6

E7C6

C5M

10nF

25V

0603

C5M

10nF

25V

0603

Q11C

RQJ0

303P

GDQA

LTQ1

1CRQ

J030

3PGD

QALT

2

1

3

C2M

10nF

25V

0603

C2M

10nF

25V

0603

D10F

GRN

LED-

LND1

0FGR

NLE

D-LN

D1F

GRN

LED-

LND1

FGR

NLE

D-LN

R6L

470R6

L

470

R2K

100

R2K

100

E2C1

E2C1

R4K

100

R4K

100

R8N

3.3KR8

N

3.3K

D10D

GRN

LED-

LND1

0DGR

NLE

D-LN

R9M

33 2512

R9M

33 2512

D1D

GRN

LED-

LND1

DGR

NLE

D-LN

F4

12A12

06F4

12A12

06

C2L

OPT

0805

C2L

OPT

0805

R11M

33 2512

R11M

33 2512

F8

12A12

06F8

12A12

06

J15

1793

1400

0_SC

J15

1793

1400

0_SC

C11S

+1

C11+

2C1

2S-

3

R9L

470R9

L

470R1

1L

470R1

1L

470

R1J

2.00k

R1J

2.00k

C12L

OPT

0805

C12L

OPT

0805

Q12C

RQJ0

303P

GDQA

LTQ1

2CRQ

J030

3PGD

QALT

2

1

3

D8F

GRN

LED-

LND8

FGR

NLE

D-LN

C11L

OPT

0805

C11L

OPT

0805

R4N

3.3KR4

N

3.3K

E6C5

E6C5

C8M

10nF

25V

0603

C8M

10nF

25V

0603

Q3C

RQJ0

303P

GDQA

LTQ3

CRQ

J030

3PGD

QALT

2

1

3

J12

1793

1400

0_SC

J12

1793

1400

0_SC

C8S+

1C8

+2

C9S-

3

J4 1793

1300

0_SC

J4 1793

1300

0_SC

C1S-

1C1

-2

R2N

3.3KR2

N

3.3K

F12 12

A1206

F12 12

A1206

F15

12A1206

F15

12A1206

R12M

33 2512

R12M

33 2512

J9 1793

1400

0_SC

J9 1793

1400

0_SC

C5S+

1C5

+2

C6S-

3

D4F

GRN

LED-

LND4

FGR

NLE

D-LN

R3M

33 2512

R3M

33 2512

R9J

2.00k

R9J

2.00k

R12L

470R1

2L

470

D2F

GRN

LED-

LND2

FGR

NLE

D-LN

R2J

2.00kR2J

2.00k

C12M

10nF

25V

0603

C12M

10nF

25V

0603

R3L

470R3

L

470

J6 1793

1400

0_SC

J6 1793

1400

0_SC

C2S+

1C2

+2

C3S-

3

R7J

2.00k

R7J

2.00k

TP9

V-TP

9V-

D6D

GRN

LED-

LND6

DGR

NLE

D-LN

D9D

GRN

LED-

LND9

DGR

NLE

D-LN

C3M

10nF

25V

0603

C3M

10nF

25V

0603

F3

12A

1206

F3

12A

1206

D2D

GRN

LED-

LND2

DGR

NLE

D-LN

D7D

GRN

LED-

LND7

DGR

NLE

D-LN

R7N

3.3KR7

N

3.3K

F7

12A

1206

F7

12A

1206

C4L

OPT

0805

C4L

OPT

0805

R7K

100

R7K

100

D4D

GRN

LED-

LND4

DGR

NLE

D-LN

R6K

100

R6K

100

R10J

2.00k

R10J

2.00k

R9K

100

R9K

100

E5

C4

E5

C4

Q10C

RQJ0

303P

GDQA

LTQ1

0CRQ

J030

3PGD

QALT

2

1

3

C7L

OPT

0805

C7L

OPT

0805

R10M

33 2512

R10M

33 2512

C6M

10nF

25V

0603

C6M

10nF

25V

0603

D7F

GRN

LED-

LND7

FGR

NLE

D-LN

R5N

3.3KR5

N

3.3K

R10K

100

R10K

100

F11 12

A1206

F11 12

A1206

R6N

3.3KR6

N

3.3K

C6L

OPT

0805

C6L

OPT

0805

R10L

470R1

0L

470

Q8C

RQJ0

303P

GDQA

LTQ8

CRQ

J030

3PGD

QALT

2

1

3

J16

1793

1300

0_SC

J16

1793

1300

0_SC

C12S

+1

C12+

2

E10

C8E1

0C8

D5F

GRN

LED-

LND5

FGR

NLE

D-LN

J14

1793

1400

0_SC

J14

1793

1400

0_SC

C10S

+1

C10+

2C1

1S-

3

R11J

2.00k

R11J

2.00k

53dc2100bfa

DEMO MANUAL DC2100B

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

THER

MIST

ORS

To U

1 Pin

18

isoSP

IB O

UT

To U

1 Pin

17

isoSP

IA I

N

To U

1 Pin

16

A0

1 0A1

A2SW

TEN

A3

OPTI

ON A

AND

C O

NLY

DO N

OT IN

STAL

L J18

IN O

PTIO

NS A

AND

C

RECO

MMEN

DED

THER

MIST

ORVI

SHAY

NTH

S01N

1002

JE

OPTIO

N A

AND

C O

NLY

OPT

TERM

10

INST

ALL

ASSY

1 ON

TO JP

7 SUC

HTH

AT A

SSY

1-1B

CON

NECT

S TO

JP7-

1C A

ND A

SSY

1-1A

CON

NECT

STO

JP7-

1B

C12 P

OWER

CON

NECT

ION

NOTE

: DC2

100A

-ASS

Y 1 I

S US

EDON

LY FO

R BU

ILD O

PTIO

N -A

AND

-C.

BA

OPT

RT10

RT6

RT8

RT3

SDIO

RT7

RT3

VREG

RT1

SDIO

RT9

RT11

RT4

SDIO

RT8

RT12

RT4

CSB

RT10

RT5

SCKB

RT5

RT9

DRV

RT2

GPIO

1

RT2

RT11

SCKB

DRV

RT6

SCKB

RT1

RT12

VREG

RT7

VREG

VREG

VREG

VREG

VREG

CSB

SDIO

SCKB

V-

V-

V-

V-

V-V-

V-

V-

V-

V-

V-

V-

V-

V-

V-

V-V-

V-

V-

ISO

SPI_

GND

ISO

SPI_

GND

ISO

SPI_

GND

CS

C3_F

ILTER

C12

SCKB

C10_

FILTE

R

C9_F

ILTER

SDI

SCK

C6_F

ILTER

C5_F

ILTER

CSB

C8_F

ILTER

SDO

C2_F

ILTER

V- C12_

FILTE

R

SDIO

C7_F

ILTER

C4_F

ILTER

C1_F

ILTER

C11_

FILTE

R

V-

VCC_

3V3

S1S2S3S4S5S6S7S8S9S1

0

S11

S12

C0_F

ILTER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

GN A

CIRC

UIT

THAT

MEE

TS C

USTO

MER-

SUPP

LIED

SPE

CIFI

CATI

ONS;

HOW

EVER

, IT R

EMAI

NS T

HE C

USTO

MER'

S RE

SPON

SIBI

LITY

TO

VERI

FY P

ROPE

R AN

D RE

LIAB

LE O

PERA

TION

IN T

HE A

CTUA

LAP

PLIC

ATIO

N. C

OMPO

NENT

SUB

STIT

UTIO

N AN

D PR

INTE

DCI

RCUI

T BO

ARD

LAYO

UT M

AY S

IGNI

FICA

NTLY

AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

OR R

ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

56

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

GN A

CIRC

UIT

THAT

MEE

TS C

USTO

MER-

SUPP

LIED

SPE

CIFI

CATI

ONS;

HOW

EVER

, IT R

EMAI

NS T

HE C

USTO

MER'

S RE

SPON

SIBI

LITY

TO

VERI

FY P

ROPE

R AN

D RE

LIAB

LE O

PERA

TION

IN T

HE A

CTUA

LAP

PLIC

ATIO

N. C

OMPO

NENT

SUB

STIT

UTIO

N AN

D PR

INTE

DCI

RCUI

T BO

ARD

LAYO

UT M

AY S

IGNI

FICA

NTLY

AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

OR R

ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

56

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

CA 95

035

Phon

e: (4

08)4

32-1

900

1630

McC

arth

y Blvd

.

LTC

Conf

iden

tial-F

or C

usto

mer

Use

Onl

y

CUST

OMER

NOT

ICE

LINE

AR T

ECHN

OLOG

Y HA

S MA

DE A

BES

T EF

FORT

TO

DESI

GN A

CIRC

UIT

THAT

MEE

TS C

USTO

MER-

SUPP

LIED

SPE

CIFI

CATI

ONS;

HOW

EVER

, IT R

EMAI

NS T

HE C

USTO

MER'

S RE

SPON

SIBI

LITY

TO

VERI

FY P

ROPE

R AN

D RE

LIAB

LE O

PERA

TION

IN T

HE A

CTUA

LAP

PLIC

ATIO

N. C

OMPO

NENT

SUB

STIT

UTIO

N AN

D PR

INTE

DCI

RCUI

T BO

ARD

LAYO

UT M

AY S

IGNI

FICA

NTLY

AFF

ECT

CIRC

UIT

PERF

ORMA

NCE

OR R

ELIA

BILI

TY. C

ONTA

CT L

INEA

RTE

CHNO

LOGY

APP

LICA

TION

S EN

GINE

ERIN

G FO

R AS

SIST

ANCE

.

THIS

CIR

CUIT

IS P

ROPR

IETA

RY T

O LI

NEAR

TEC

HNOL

OGY

AND

SCHE

MATI

C

SUPP

LIED

FOR

USE

WIT

H LI

NEAR

TEC

HNOL

OGY

PART

S.SC

ALE

= NO

NE

www.

linea

r.com 1

DEM

O CI

RCUI

T 21

00B

56

HIGH

EFF

ICIE

NCY

BIDI

RECT

IONA

L

N/A

LTC3

300I

LXE-

1 / L

TC68

04IG

-2

NC J. DR

EW

10 -

8 - 14

MUL

TICE

LL B

ATTE

RY B

ALAN

CER

U5

LTC6

820IM

SU5

LTC6

820IM

SEN1

MOSI

2

MISO

3

SCK

4

CSB

5

VCCS

6

POL

7

PHA

8VC

C9

IP11

GND

14VC

MP15

MSTR

12SL

OW13

IBIA

S16

IM10

JP2

JP2 1

2

3

C26

0.1uF

100V 0805

C26

0.1uF

100V 0805

T14

ACT4

5B-22

0-2P

T14

ACT4

5B-22

0-2P 3

214

TP7 VR

EGTP

7 VREG

TP3

WDT

B

TP3

WDT

B

Q3CZ

T555

1Q3

CZT5

551

1

2 34

TP5

SCKB

TP5

SCKB

R36 2.0

K

R36 2.0

K

R59

5.1k

R59

5.1k

R25

60.4

0603

R25

60.4

0603

C50

0.1uF

25V

0603

C50

0.1uF

25V

0603

C25

0.1uF

100V

0805

C25

0.1uF

100V

0805

R37

100

R37

100

C28

1uF

25V

0603

C28

1uF

25V

0603

R41 1MR41 1M

R63

60.4

R63

60.4

C21

100p

F06

03

C21

100p

F06

03

U424

AA64

U424

AA64

SCL 1

VSS 2

VCC4

WP5

SDA 3

R32 1.4

0k

R32 1.4

0k

R30

1MR30

1M

R29

60.4

R29

60.4

C29

0603

1uF

25V

C29

0603

1uF

25VR3

510

KR3

510

K

12

34 8

7

109

12115

6

DC21

00A-

ASSY

1

TSW

-106

-07-

L-T

12

34 8

7

109

12115

6

DC21

00A-

ASSY

1

TSW

-106

-07-

L-T

TP4

GPIO

1

TP4

GPIO

1

JP4

JP4 1

2

3

C31

1uF

25V

0603

C31

1uF

25V

0603

JP7

TSW

-106

-07-

L-T

JP7

TSW

-106

-07-

L-T

1C1A

2C 3C 4C 5C 6C

1B 2B2A

3B3A

4B4A

5B5A

6B6A

TP6 CS

BTP

6 CSB

R43

10k

R43

10k

T13

PE-68

386

T13

PE-68

386

46 1

3

R31

1MR31

1M

J17

CON-

DF3D

Z-15

P-2H

51

J17

CON-

DF3D

Z-15

P-2H

51

TEMP

115

TEMP

214

TEMP

313

TEMP

412

TEMP

511

TEMP

610

TEMP

79

TEMP

88

TEMP

97

TEMP

106

TEMP

115

TEMP

124

GND

3

GND

2

GND

1

U7 LTC1

380IG

NU7 LT

C138

0IGN

S01

S12

S23

S34

S45

S56

S67

S78

DO9

GND

11

SDA

14

SCL

15A1

12A0

13

VCC

16VE

E10

C27

0.1uF

25V

0603C27

0.1uF

25V

0603

C30

10uF

6.3V

0603

C30

10uF

6.3V

0603

R39

1.40k

R39

1.40k

JP5

JP5 1

2

3

C51

0.1uF

25V

0603

C51

0.1uF

25V

0603

R28

100

R28

100

TP8 SD

IOTP

8 SDIO

U6 LTC1

380IG

NU6 LT

C138

0IGN

S01

S12

S23

S34

S45

S56

S67

S78

DO9

GND

11

SDA

14

SCL

15A1

12A0

13

VCC

16VE

E10

J18

RJ45

J18

RJ451

23

45

67

8

1112

R34

2.0K

R34

2.0K

R42

10k

R42

10k

R26

60.4

0603R26

60.4

0603

E16

SHIE

LD

E16

SHIE

LD

U3 LTC6

804-

2

U3 LTC6

804-

2

VP1

C12

2

S12

3

C11

4

S11

5

C10

6

S10

7

C98

S99

C810

S811

C712

S713

C614

S615

C516

S517

C418

S419

C320

S321

C222

S223

C124

S125

CO26

GPIO

127

GPIO

228

GPIO

329

VM2

30VM

31GP

IO4

32GP

IO5

33VR

EF2

34VR

EF35

SWTE

N36

VREG

37DR

IVE38

WDT

39ISO

MD40

CSB(

IMA)

41SC

K(IPA

)42

SDI(IC

MP)

43SD

O(IB

IAS)

44A0

45A1

46A2

47A3

48

J1

RJ45

J1

RJ451

23

45

67

8

1112

R40

1MR40

1M

T15

PE-68

386

T15

PE-68

386

46 1

3

C32

100p

F06

03C3

210

0pF

0603

JP1

JP1 1

2

3

R27

100

R27

100

C33

0.1uF

25V

0603C33

0.1uF

25V

0603

R33 604

R33 604

JP6

JP6

1

2

3

R38

604

R38

604

JP3

JP3 1

2

3

54dc2100bfa

DEMO MANUAL DC2100B

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Clos

e to

J19

Isolat

ion

Bypa

ssCo

mpo

nent

s: 25

12 fo

r5m

m cl

eara

nce

ICD

INTE

RFAC

E

OPT

OPT

OPT

OPT

C40

only

use

d in

non-

isol

ated

case

ALL C

OMPO

NENT

S ON

PAG

E 6 A

REFO

R "B

UILD

OPT

ION

A A

ND C

ONL

Y".

GPIO

WUR

TH: 6

5100

5136

521

STAN

D AL

ONE

LDO

ASSE

MBLY

NOT

E:

OPT

OPT

OPT

OPT

OPT

AN3 AN

2AN

1AN

0

AN5

AN6

AN7

AN1

AN3

AN5

AN7

SDO2

AN0 AN

2AN

6SS

2

VCC_

3V3

VCC_

5V

VCC_

3V3

AN0

SS2

SDI2

SDO2

SCL2

SDI2

SCL2

VCC_

5V

VCC_

3V3

VCC_

3V3

VCC_

3V3

VCC_

3V3

VCC_

3V3

VCC_

3V3

CS

SCK

SDI

SDO

C12

V-

VCC_

3V3

SIZE

DATE

:

IC N

O.RE

V.

SHEE

TOF

TITL

E:

APPR

OVAL

S

PCB

DES.

APP

ENG.

TEC

HN

OLO

GY

Fax:

(408

)434

-050

7

Milp

itas,

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55

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77

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1515

1616

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R66

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2

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34

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C44

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R62

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C22

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C49

C49

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R50

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R51

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SC1

32

RA6/C

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SC2

33

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s1 6

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Vdd229

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1

30

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17

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34

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P22

3

RD3/P

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P20

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2/RP1

940

RD4/P

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P21

2

RD1/P

MD1/S

DA2

39RD

0/PMD

0/SCL

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MCS

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1/AN6

/PMW

R26

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MRD

25

C42

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R61

2.00k

R61

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3.3V

U9 LT17

61ES

5-3.

3

3.3V

U9 LT17

61ES

5-3.

3

IN1

GND 2

SHDN

3BY

P4

OUT

5

55dc2100bfa

DEMO MANUAL DC2100B

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

schematic Diagram5 5

4 4

3 3

2 2

1 1

DD

CC

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3.65k

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RT12

E12

RT12

E11

RT11

E11

RT11

R113

01R1

1301

E2RT

2E2

RT2

E10

RT10

E10

RT10

R72.4

9kR7

2.49k

E1RT

1E1

RT1

R81.2

4kR8

1.24k

E5RT

5E5

RT5

E9RT

9E9

RT9

R121

47R1

2147

E6RT

6E6

RT6

R134

0kR1

340k

E4RT

4E4

RT4

E7RT

7E7

RT7

E14

V-E1

4V-

R990

9R9

909

E13

V-E1

3V-

J1

CON-

DF3-

15S-

2DSA

21

J1

CON-

DF3-

15S-

2DSA

21

TEM

P1

15

TEM

P2

14

TEM

P3

13

TEM

P4

12

TEM

P5

11

TEM

P6

10

TEM

P7

9

TEM

P8

8

TEM

P9

7

TEM

P10

6

TEM

P11

5

TEM

P12

4

GN

D3

GN

D2

GN

D1

R254

.9kR2

54.9k

56dc2100bfa

DEMO MANUAL DC2100B

LINEAR TECHNOLOGY CORPORATION 2015

LT 0517 REV A • PRINTED IN USA

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:

This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.

This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

Copyright © 2004, Linear Technology Corporation