13
[email protected] EUDET Annual Meeting – October 8, 2007 1 Status of the CEA Status of the CEA Saclay R&D activities Saclay R&D activities on pixelised readout of on pixelised readout of TPC TPC David Attié , Paul Colas, Marc Riallot, Franck Senée Eudet Annual Meeting, Ecole Polytechnique 8-10 October 2007

[email protected] Annual Meeting – October 8, 20071 Status of the CEA Saclay R&D activities on pixelised readout of TPC David Attié, Paul Colas,

Embed Size (px)

Citation preview

[email protected] EUDET Annual Meeting – October 8, 2007 1

Status of the CEA Status of the CEA Saclay R&D activities on Saclay R&D activities on pixelised readout of TPCpixelised readout of TPC

David Attié, Paul Colas, Marc Riallot, Franck Senée

Eudet Annual Meeting, Ecole Polytechnique 8-10 October 2007

[email protected] EUDET Annual Meeting – October 8, 2007 2

Overview

• TimePix wafer tests

• Status of TimePix/Micromegas chamber at Saclay

• Large Prototype Endplate

• Next steps

[email protected] EUDET Annual Meeting – October 8, 2007 3

TimePix wafer tests at CERN

Class

A No dead columns

B 1 dead column

C 2 dead columns

D >2 dead columns

E Bad DACs

F Bad Digital Test

Fnt Not tested

20 wafers

from the first run

have been tested

~ 66 %

of chips are usable

1 m² ~ 4400 chips ~ 68 wafers Thanks to X. LLOPART (CERN)

Wafer n° Location A B C D E F Fnt Wafer A+B+C8_A9FWR6X CERN 31 27 6 11 12 20 0 107 64

9_ACFWR3X CERN 42 15 13 10 9 17 1 107 70

10_A6FWQ5X CERN 40 27 7 12 11 9 1 107 74

11_ATFWTLX CERN 54 18 7 6 14 8 0 107 79

12_ASFWTMX CERN 45 21 7 2 18 13 1 107 73

13_ARFWTNX CERN 15 18 14 27 17 16 0 107 47

14_A5FWQTX Diced 44 26 3 6 8 20 0 107 73

15_AQFWTPX VTT 55 20 10 6 9 7 0 107 85

16_GX11ILX CERN 44 27 8 10 13 5 0 107 79

17_G111GIX CERN 41 31 8 7 14 6 0 107 80

18_GG11G3X CERN 58 26 5 4 9 5 0 107 89

19_GF11G4X CERN 49 30 9 6 9 4 0 107 88

20_GV11INX CERN 51 23 15 13 3 2 0 107 89

21_GV11GPX CERN 49 27 8 9 9 5 0 107 84

22_GZ11H2X CERN 48 25 9 7 14 4 0 107 82

23_GU11H7X CERN 58 26 2 3 12 6 0 107 86

24_GY11IKX CERN 47 23 8 6 18 5 0 107 78

25_GW11H5X CERN 46 18 8 15 2 18 0 107 72

26_GS11H9X CERN 35 39 7 8 11 7 0 107 81

27_GH11G2X CERN 56 27 5 4 13 2 0 107 88

TOTAL 908 494 159 172 225 179 3 2140 1561 (%) 42,4 23,1 7,4 8,0 10,5 8,4 0,1 100 72,9

TimePix classification Total

[email protected] EUDET Annual Meeting – October 8, 2007 4

TimePix/Micromegas chamber at Saclay

Field cage

Cover

Micromegas

mesh

Medipix2/TimePix chip

M. RIALLOT (DAPNIA/SEDI)

Windows for X sources

Windows for source

• Blueprint :

[email protected] EUDET Annual Meeting – October 8, 2007 5

TimePix/Micromegas chamber at Saclay

• 3 Specific Micromegas meshes build at CERN are available

- 55 m of pitch holes- 75 m of pillar diameter- 50 m of gap

[email protected] EUDET Annual Meeting – October 8, 2007 6

TimePix/Micromegas chamber at Saclay

[email protected] EUDET Annual Meeting – October 8, 2007 7

TimePix/Micromegas chamber: status

• The field cage is ready to work in He/Iso 80/20 (the cathode bear up to 6 kV) and Ar/Iso mixture

• 1 TimePix dead by HV accident

• 2 TimePix Chip don’t show the same behavior after putting up the micromegas mesh

• 4 TimePix have been protected by 20 m of amorphous silicon

cosmic tracks should be observed soon !

[email protected] EUDET Annual Meeting – October 8, 2007 8

Large Prototype endplate

InterchangeableMicromegas bulk technology

= 80cm

D. Peterson, Cornell

[email protected] EUDET Annual Meeting – October 8, 2007 9

Micromegas Large Prototype endplate

Pad ~ 2,8 x 6, 8 mm²

HT

connection

[email protected] EUDET Annual Meeting – October 8, 2007 10

Deliverable panel with TimePix

1x8 chips

Si-Prot+Ingrid

1 MUROS

Pad ~ 2,8 x 6, 8 mm²

HT

connection

[email protected] EUDET Annual Meeting – October 8, 2007 11

Deliverable panel with TimePix

2x8 chips

Si-Prot+Ingrid

2 MUROS

Pad ~ 2,8 x 6, 8 mm²

HT

connection

[email protected] EUDET Annual Meeting – October 8, 2007 12

Large Prototype Endplate

[email protected] EUDET Annual Meeting – October 8, 2007 13

Next steps

•4 Si-protected TimpePix are ready to be tested with the TimePix chamber

•The design engineering about a PCB board of 1x8 TimePix matrix has started

•Add “Integrated Grid” (InGrid) on top a matrix (2x4, 1x8,…)

•Helpful to have one panel-box for tests before LP endplate