David Malaspina CU/LASP

D Malaspina 1FIELDS I-CDR – DFB

Solar Probe Plus FIELDSInstrument CDR

Digital Fields Board (DFB) Subsystem

David MalaspinaCU/LASP

[email protected]


DFB Agenda

Digital Fields Board (DFB)

• Science Requirements• Performance and Interface Requirements• Block Diagrams• EM Development • FPGA Development• ASIC Development• Test Results


DFB Heritage

The SPP FIELDS DFB has strong heritage:

Mission (# DFBs) Year Launched Current Status

THEMIS (5x) 2007 Operating nominally

Van Allen Probes (2x) 2012 Operating nominally

MAVEN (1x) 2013 Operating nominally

MMS (8x) 2015 Ready for Launch

Solar Probe Plus (1x) 2018 Instrument CDR


DFB Specific Science Overview

DFB frequency coverage: E [DC - 60 kHz] B [10 Hz – 60 kHz]

“Trace the flow of energy that heats and accelerates the solar corona and solar wind”- Alfvén waves and Poynting flux- Turbulent cascade and dissipation - Compressive waves and cyclotron damping- Magnetic reconnection and collisionless shocks - Signatures of ambipolar/IP potential

“Determine the structure and dynamics of the plasma and magnetic fields at the sources of the solar wind”- Flux tube structure- Reconnection current sheets- Streamer belt reconnection

“Explore mechanisms that accelerate and transport energetic particles” - Interplanetary shocks - Solar wind magnetic reconnection


DFB Electric Field Frequency Coverage

band pass filter bank


DFB Magnetic Field Frequency Coverage

band pass filter bank


DFB High-Level Tasks

Accepts signals from 5 electric field sensors, 4 search coil magnetic field sensors

Performs analog processing, digitization, and digital processing of:Voltage signals (antenna-to-spacecraft ground)

DC-coupled, AC-coupledElectric field signals (antenna-to-antenna)

DC-coupled (High-gain, Low-gain), AC-coupledMagnetic field signals (> 10 Hz)

Low-frequency coil signals (High-gain and Low-gain)Medium-frequency coil signals

Generates time domain and spectral domain data products, transmits them to the digital control board (DCB)

Generates calibration signals for search coil magnetometer


DFB Design Drivers

SPP Science Challenges– Unknown / highly variable plasma environment: Requires large dynamic range.

• Programmable gain states• Low-noise operational amplifiers• Flexible configurations

– Low telemetry volume: Requires on-board pre-selection of highest-rate data• Burst memory• Waveform and spectral compression• Flexible data rates

SPP Engineering Challenges– Low power and mass requirement + large # of channels + high sample rate

• Teledyne SIDECAR ASIC for A/D conversion– Accommodating non-ideal behavior of SIDECAR

• distortion near rails, high temperature operation– High temperature environment

• Testing and characterization at expected temperatures– Must accommodate low-noise radio receiver (RFS)

• NY second ≈ 0.87 sec = 217 / 150,000 = one ‘cycle’ • PPC = pulse per cycle (as opposed to PPS = pulse per second, on prior missions)


FIELDS Block Diagram


DFB Block Diagram

9 inputs:5 E-field antennas4 search coil channels

26 signals digitized @ 150 kS/s

Anti-aliasing filters / Gain stages

FPGA processing


DFB Data Products

Product Inputs Cadence Does Input/Cadence meet requirements?

Continuous Waveform select 12 of 18 possible input channels

18,750 / 2N S/s Exceeds L4 performance req.

Burst Waveform[DFB Burst Memory (DBM)]

select 6 of 33 possibleinput channels

150,000 / 2N S/s Exceeds L4 performance req.

Power Spectra [AC/DC] select 4 AC / 4 DC of 15 AC / 18 DC inputs

16 to 1/1024 S/NYs

Exceeds L4 performance req.

Cross Spectra [AC/DC] select 4 AC / 4 DC of15 AC / 18 DC inputs

16 to 1/1024S/NYs


Band Pass Filter Bank [AC/DC]

select 4 AC / 4 DC of 15 AC / 18 DC inputs

128 to 1/256 S/NYs


Housekeeping command / memory / mode status

1 to 1/32,767 S/NYs

Meets L4 interface req.

Spacecraft Potential 4 channels 4 S/NYs


Coordinated Burst Packets

burst buffer type / timestamp / quality

generated on DBM buffer queue change



DFB L4 Performance Requirements 1of 2

ID Name Requirement Parent Method Criteria Due

DFB-09 SCM Interface (LF Magnetic Fields)

The DFB shall be capable of measuring 3D vector magnetic fields from SPP, as follows:-- frequency range: 10 Hz to greater than 50 KHz;-- maximum field intensity: 3000nT above noise floor at 3.5kHz;-- cadence: up to 2x the highest frequency in vectors/sec;-- minimum sensitivity better than: 1 x 10^(-3) nT/sqrt(Hz) at 100 Hz; 1 x 10^(-4) nT/sqrt(Hz) at 3.5 kHz; -- in three orthogonal components.

PAY-38 Test Verification via Calibration Report

Delivery

DFB-10 SCM Interface (MF Magnetic Fields)

DFB shall be capable of measuring AC magnetic field amplitude over solar orbital distances of 9.86 Rs to 0.25 AU as follows:-- frequency range: 1 kHz – 60 kHz;-- maximum field intensity: 6 nT above noise floor at 30 kHz;-- cadence: up to 150,000 vectors/second;-- sensitivity (excluding power converter frequencies and external noise sources) better than: 1 x 10^(-4) nT/sqrt(Hz) at 10 kHz; 5 x 10^(-5) nT/sqrt(Hz) at 30 kHz;-- one component aligned with one axis of SCM-LF


Delivery

DFB-11 SCM Interface (Magnetic Field Power Spectra)

DFB shall be capable of measuring power spectra of AC magnetic fields over solar orbital distances of 9.86 Rs to 0.25 AU as follows: -- frequency range: 10 Hz – 60 kHz;-- cadence: up to 1 spectrum/second.


Delivery

DFB-12 SCM Calibration

DFB calibration shall synthesize a SCM calibration signal with agreed upon characteristics.

PAY-231 Demonstration Captured waveform matches DFB FPGA Spec.

Delivery


DFB L4 Performance Requirements 2 of 2

ID Name Requirement Parent Method Criteria Due

DFB-06 AEB Interface (Electric Fields)

DFB shall be capable of measuring 3D vector electric fields from SPP, as follows: -- frequency range: DC to 60 kHz; -- maximum field intensity: ±10V/m at DC; ±5V/m at 20kHz;-- cadence: up to 2x the highest frequency in vectors/sec;-- sensitivity (excluding power converter frequencies) better than: 1 mV/m in 10V/m range at DC; 100 μV/m in 1V/m range at DC; 3x10^(-7) V/m/sqrt(Hz) at 30 kHz;


Delivery

DFB-07 AEB Interface (Electric Fields Power Spectra)

DFB shall be capable of measuring power spectra of AC electric fields from SPP over solar orbital distances of 9.86 Rs to 0.25 AU as follows: -- frequency range: 5 Hz – 60 kHz;-- cadence: up to 1 spectrum/second.C84


Delivery

DFB-13 E to B Field Crosstalk

DFB shall make measurements with less than 80dB crosstalk between Electric field and Magnetic field signals

PAY-170,PAY-172

Test Verification via Calibration Report

Delivery


DFB L4 Interface Requirements

ID Name Requirement Parent Method Criteria DueDFB-05 AEB Interface DFB shall provide an electrical interface to the AEB capable of:

[a] receiving 5 single ended analog signals V1,2,3,4,5[b] providing high input impedance to minimize effects of signal loading from the multiple boards in the MEP

PAY-170,PAY-172

Analysis Review of the schematics

CDR

DFB-08 SCM Interface DFB shall provide an electrical interface to the SCM capable of:[a] receiving 4 differential analog signals Bx,y,z low frequency and Bx medium frequency[b] providing high input impedance to minimize effects of signal loading from the multiple boards in the MEP [c] providing unbuffered output of the SCM Bx medium frequency signal to the TDS and RFS

PAY-38,PAY-172,PAY-174

Analysis Review of the schematics

CDR

DFB-14 MEP mechanical interface

The DFB mechanical interface shall comply with the SPF_MEP_102_DFB_ICD

PAY-279 Analysis

Inspection

-DFB mechanical drawings will show compliance with MEP ICD-Acceptance of DFB assembly to MEP will confirm compliance

CDR

Delivery

DFB-15 MEP Thermal Interface

DFB shall be designed for -25C to +60C operating range (change from Peer Review) and -30C to +65C survival range.

PAY-141 Analysis

Test

-EEE Component Specifications and Stress Analysis Report. And PWBA thermal modeling-Thermal vacuum testing results.

CDR

Post-Delivery

DFB-16 Timing DCB Interface

The DFB shall comply with the time sharing protocols as described in SPF_MEP_100_CDI_ICD.

PAY-113 Demonstration Verify DFB returns correct times in telemetry packets.

Delivery

DFB-17 DCB interface The DFB interface to the DCB shall comply with the SPF-MEP_100_CDI_ICD

PAY-279 Demonstration Verify DFB responds to commands per the CDI and returns CCSDS telemetry correctly

Delivery


DFB EM1 in MEP at SSL

EM1 testing in SPF-MEP– Contains most functionality– Upgrades to the Xilinx FPGA can be loaded at SSL

Lessons from EM1 incorporated into EM2


DFB EM2 is Flight Like

• Design is for flight configuration• Layout and fabrication to flight

specs– Schedule allows for re-spin

if needed• PCBs passed coupon testing• Extensive testing to validate flight

design in process • Accommodates programmable or

one-time burn FPGA daughter boards

• Targeted for SPF MEP Flatsat

FPGA DB

ASIC


DFB Mechanical Design

Frame

EMI Shield

Main PWB • t= 0.063”• polyimide aramid

PWA/Frame/EMI fasteners (17)

Daughter Board (DB)• t = 0.072”• CCGA FPGA• HDLP90 connectors (4)• Corner attached

Connectors (5)• Flying leadConnector

Nut Plate (5)

SIDECAR Cap

SIDECAR CCGA

DFB single slice in MEP electronics box• First MEP mode 500Hz• First DFB PWB mode one octave below

Vent

ZX

Y


DFB Mechanical Analysis and Test Results

• DFB PWB board level analysis and verification completed– Loads requirements to the EDTRD Rev B – CCGA Solder Column (90Pb/10Sn from BAE)

• Analysis results– Analyzed with and without daughter board

connectors– Local CCGA stiffener added– Recalculated post test for 234Hz first mode

• Testing and results– Passed random vibe of mechanical CCGA– Retired CCGA to PWB structural integrity risk

Margin of Safety Table

36g RV 100gSolder stress (psi) 570 855 1577MS yield 5.6 1.0 0.4MS ultimate 4.9 4.9 1.1PWB stress (psi) 2250 2640 6250

MS ultimate 7.9 4.9 2.2

Frequency 236 Hz


DFB CDR Thermal Design

• MEP Thermal Test Requirements per EDTRD: -25°C to +60°C• Per EEE-INST-002: All junction temperatures shall remain below 110°C, or 40°C below

manufacturer’s spec, whichever is lower• Modeled components shown in table below

– Per Peer Review, added underfill to MSKennedy part • Remaining 860mW of low powered (<30mW) components spread across board


DFB FM Development Plan

• High Fidelity EM2 testing to confirm FM final design– Rigorous testing continues thru early spring 2015– Progression tests with FPGA Xilinx and ProtoRTAX DBs verify final DFB prior to flight build

• DFB schedule allows for spin of PWB if needed in late spring 2015 • Any changes between EM and FM formalized thru LASP practices and DFB/SPF/SPP teams• EEE parts and materials procured, received, approved by PMCB, in flight-controlled stores• Most mechanical parts received and in flight-controlled stores• Flight Production

– Fabrication Assembly Instructions (FAI) draft developed for EM2• Extreme ESD standards (LASP 105222revD) in-place for SIDECAR ASIC.

– Manufacturing Readiness Review (MRR) convened before production starts• Using same vendors (BAE, Aeroflex) as for EM2 • Extreme ESD requirements flowed to sub-contractors

– Flight Problem/Failure reporting procedures in-place (LASP 000057revE)• Integration & Test

CCGA Columns - BAE - PWBA

Checkout

Connectors & Mechanical Assembly - LASP -

PWBA Assembly

- Aeroflex -

DeliveryCalibration

over Temperature

PolymericsXilinx FPGA

Daughter Board

RTAX Proto Daughter

Board - APL -

RTAX Daughter

Board - APL -

Functional Verification

CompatibilityTesting

MIP

MIP

MEP I&T-SSL-


DFB Pre-ICDR Peer Review and Action Items

No Title Detail Status

DFB-01 Pre-ICDR

ESD Handling of DFB Provide DFB ESD handling procedures to SSL/Fields team due to sensitivity of SIDECAR ASIC

Procedure written, in-review

DFB-02 Pre-ICDR

BandPass APIDs Detail which of the BandPass APIDs are for FSW to use for the CBS. Resolve: Filters 1-4 are DC, 5-8 are AC; Filters 3,4,7,8 used by DCB for Burst Triggers

Closed

DFB-03Pre-ICDR

DBM Gain Selection Determine if gain select can be done within DBM. If not, select the gain external to DBM. Check on DCB ability to switch gain to low if all high samples were saturating

Open, in-process

DFB-04 Pre-ICDR

Updated DFB Specification

Spec is out-of-date; specifically, change DBM/CBS holding buffers from 4 to 6

Updated, in release cycle

DFB-06 Pre-IPDR

Signal Integrity on FPGA DB

Consider adding more grounding on FPGA DB Testing, Closing ICDR

DFB Pre-ICDR Peer Review was held at LASP on Dec 4, 2014Actions from this review and open actions from prior reviews shown in table below


SPF DFB FPGA and SIDECAR ASIC

David MalaspinaCU/LASP

[email protected]


DFB FPGA DIAGRAM


DFB FPGA Functions

• FPGA functions– Signal Averaging– Timing Synchronization– Data Compression– Digital Housekeeping– CCSDS Data Packetization

• FPGA DSP Functions– FFT Spectral and Cross-

Spectral Processing– Digital Filters– Digital Burst Memory– Band-Pass Filter Banks– Waveforms– Spacecraft Potential

• Fields Probe/Processing Control– 16 Programmable modes– Modes are loaded from the DCB at power on

• Signal Acquisition & Digital Filtering– 26 channels sampled simultaneously at 150K

samples/second – AC signals: digitally filtered and decimated to

produce samples from 150KS/s down to 2.3KS/s – DC signals: digitally filtered and decimated to

produce samples from 18.75KS/s down to 1.1S/s. • DCB Interface

– Serial Command Interface– Serial Telemetry Interface– 19.2Mhz system clock– 4.8Mhz telemetry clock

• SCM Calibration– Digitally Synthesized sine wave– Sine values generated via the CORDIC algorithm– Sent to 16bit DAC for analog conversion


DFB FPGA – Design Drivers

• Calculate FFTs on four 18.75kss channels with 100% coverage• Calculate FFTs on four 150kss channels with at least 12.5%

coverage• Drives SRAM size and bandwidth

• Provide digital filtering for 16 channels of 150kS/s data and 16 channels of 18.75kS/s data

• Package science data into CCSDS packets• Perform compression on time series waveform and DBM data• Perform pseudo-log compression on Spectra, X-Spectra, and Band-

Pass Filter Banks results• Generate sine wave data for SCM calibration signal


DFB FPGA Development Strategy

• FPGA development in VHDL• Development follows 108864 LASP FPGA

Development Guide• All FPGA build files under version control and will

be in configuration management• Prototype DFB has a Xilinx Spartan 6 FPGA

soldered directly to the motherboard

• Flight, EM1 and EM2 DFB boards will use an SPF FPGA daughterboard– daughterboard can be built with ProASIC, Xilinx

Spartan6 or RTAX FPGA

• FPGA build automated with compile scripts – Xilinx and RTAX versions are compiled for every FPGA release– RTAX timing is checked for every release

• RTAX FPGA is much slower than Xilinx Spartan 6• Frequent timing checks ensure that the design meets

timing in the flight device and will not require any modifications for the flight build.


DFB FGPA Resource Summary

Device: Actel RTAX4000S (1272 CCGA)

Cell Type Total Used AvailablePercent

Utilization

Sequential (R-Cells) 14314 20160 71%

Combinatorial (C-Cells) 33465 40320 83%

Logic (R+C Cells) 47779 60480 79%

RAM Blocks 87 120 73%

IO 279 840 35%

CBE gate utilization for final flight design


DFB Data Products

• Register Read Response• Digital Housekeeping Packets• Survey Waveform Packets

– Time series ≤ 18.75kS/s– 12 channels, configurable

• Spacecraft Potential– V1, V2, V3, V4 data at 4.58 sample/s

(one sample per ¼ PPC)• DC Band-Pass Filter Bank

– Up to 4 channels• AC Band-Pass Filter Bank

– Up to 4 channels• DC Spectra/Cross-Spectra

– Up to 4 Chs 4688 Hz max freq• AC Spectra/Cross-Spectra

– Up to 4 Chs 75,000 Hz max freq • Digital Burst Memory (DBM)

– 6 channels time series data ≤150kS/s • ADC RAW data capture

– Time series data at 150kS/s which bypasses all internal processing

– For ground testing only

44 DFB Data Products

DC

AC


SCM Calibration Signal

• FPGA generates 16 bit sine wave samples• 16bit DAC converts samples into an analog signal• Continuous sine wave, or programmable “chirp” operation• Option for pure sine wave, or two summed sines• For chirp, 2^N cycles of a sine wave are generated, the frequency is divided

by 2, then 2^N cycles are generated at the new frequency• Process repeats until the end frequency is reached• Sharp “corner” produced by slope change in between frequencies


SCM Calibration Signal

Step Number Frequency Number of Cycles

Duration

0 9.96kHz 64 0.0064s1 4.61kHz 64 0.014s2 2.27kHz 64 0.028s3 1.35kHz 64 0.047s4 696Hz 64 0.092s5 330Hz 64 0.19s6 183Hz 64 0.357 73.3Hz 64 0.87s8 36.6Hz 64 1.75 s

Total Time: 3.35s

SCM Calibration signal default configuration:


DFB FPGA Timing

• System Clock = 19.2Mhz = 52.1ns period• 120% clock rate used as goal to improve timing margin• 19.2Mhz X 120% = 23.0Mhz = 43.4ns period• Design meets timing with 20% margin


DFB FPGA Verification Plan

• Extensive Behavioral Simulation of all logic– IDL generated data used as the input for the VHDL test-benches– IDL verification of data output from FPGA test-bench

• Static timing analysis with – 120% clock rate used for timing analysis– No back annotated post route simulation

• Extensive lab testing– Test data from the lab is captured on a PC and compared to IDL models

of the algorithms– This approach was very successful for THEMIS/MAVEN verification

• EM Configuration– DFB Layout for FPGA Daughterboard which can support

1. Xilinx Spartan 6 2. Pro-Asic A3Pe3000-FG4843. RTAX4000/Proto


DFB FPGA Status

Module Name Owner VHDL Code Simulation Lab Testing

Top Level Module DS 100% 100% 100%Arithmetic Logic Unit DS MK 100% 75% 50%SIDECAR ASIC Interface DS 100% 100% 80%Mid-Freq Filters MK 100% 80% 80%Low-Freq Filters MK 100% 80% 80%AC Band-pass Filter MK 100% 75% 25%DC Band-pass Filter MK 100% 75% 25%Waveform Player DS MK 100% 100% 90%Digital Burst Memory (DBM) MK 90% 40% 15%DC Spectra DS 100% 80% 75%AC Spectra DS 100% 80% 75%DC Cross-Spectra DS 100% 80% 75%AC Cross-Spectra DS 100% 80% 75%SDRAM controller for DBM DS MK 100% 75% 75%SRAM controller for Spectra/Cross-Spectra

DS100% 100% 90%

SRAM controller for Data Processor DS 100% 100% 90%Command Processor DS 100% 100% 100%Data Processor (CCSDS packetizer, data compression)

DS100% 80% 75%

SCM Calibration Signal Generator DS 100% 100% 100%

Simulation Test-bench DS MK 40% 20% N/A

DFB FPGA lab testing• Tested on Prototype

DFB, EM1 DFB, EM2 DFB boards

• Tested on Xilinx and Microsemi ProtoRTAX FPGAs

• Interface works with FIG GSE and prototype DCB

• All data products have been lab tested except digital burst memory

– DBM module is currently being simulated and lab tested

• FFT results match IDL model nicely


DFB FPGA To Do List

• To Do– Test and debug of Digital Burst Memory and Band-Pass Filter Banks

(complete Q1 2015)– Continue simulation and lab testing of all modules (on-going thru 2015)– Add SCM vector rotation for cross-spectra (complete Q1 2015)

• SCM axes are not aligned with the fields antennas• Must rotate SCM X,Y,Z samples into the same coordinate system as the

fields antennas• Simple matrix multiply (no trigonometric functions required)

– Develop a self-checking constrained random test-bench for VHDL verification (complete Q2 2015)

• Reuse the same architecture that worked well on MAVEN LPW• Allows us to run hundreds of randomized test cases • Random testing will take place in parallel with interactive directed test cases • Test-bench reports back when a test fails• Failing test case can be re-run in interactive mode for debug


Teledyne SIDECAR ASICOverview

SIDECAR ASIC features:• 32 analog input channels (26 used for SPF DFB)• Built in Preamplifiers• Up to 500kHz A/D conversion with 16-bit resolution per channel

• Higher sample rates require higher bias currents which increases overall power dissipation

• SPP Application samples at 150k samples/s• ~600mW for 26 A/D channels at 150kss

• 23mW per channel• 20% of the power of a comparable 16 bit ADC

• 16-bit Microcontroller• For SPP application, used for configuration and internal memory scrubbing• In-flight programmable

• 16 bit parallel science data interface to DFB FPGAFlight heritage:

• Hubble ACS-R• JWST (future)

DFB SIDECAR ASIC firmware complete


DFB SIDECAR Firmware

• Loads SIDECAR Configuration Registers

• Provides a mechanism to allow the FPGA to control the timing of the ADC sampling to within +/-1us

• Periodically reads SIDECAR program/data memory locations for EDAC scrubbing.

• Scrub rate: one address every 7us• SIDECAR has built-in EDAC, processor needs only to read memory locations.• SIDECAR automatically detects, corrects and writes back locations with errors


DFB SIDECAR FirmwareImplementation Complete

• ~600 lines of SIDECAR configuration instructions• Configuration instructions bypass the microprocessor

• 38 lines of executable assembly code as shown• (comments removed for presentation)


Test Results ASIC SIDECAR Characterization

SIDECAR channels 27-31show increased noise (~2x) and variability with temperature for lowinput voltages

Four flight candidate SIDECARASICS were tested for

noisenonlinearitysaturationcrosstalk

At three temperatures25 C45 C 65 C

All ASICs behaved in-family across temperature

Performance meets DFB science requirements


Test Results Spec / Xspec FPGA Calculation

Blue = FPGA sim. calculation result

Red = IDL nearly-bit-accurate calculationwith binning +compression / decompression

Differences are ~1-2 count (rounding)


Test Results Spec / Xspec FPGA Calculation

Blue = FPGA sim. calculation result

Red = IDL nearly-bit-accurate calculationwith binning +compression / decompression

Differences are ~1-2 count (rounding)


Test Results Spec / Xspec Board Level

Input 1: 10,000.0 Hz sineInput 2: 10,000.1 Hz sine

Expect inputs 1 and 2in/out of phase at ~0.1 Hz

Rela

tive

Phas

e (d

eg)

Power input 1 Power input 2

Phase from DFB Xspec


Test Results Waveform Delta-Compression

Most efficient for slowly varying data

For a 1200 count, 500 Hz sine wave [35% size reduction]

1312 words compr. ------ = 0.65 = ---------------- 2016 words decompr.

For ~3 count rms noise:[83% size reduction]

336 words compr. ------ = 0.17 =2016 words decompr.

Raw Bits

Decompressed

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David Malaspina CU/LASP