datasheet74HC139

8/6/2019 datasheet74HC139

1/8

Semiconductor Components Industries, LLC, 2000

March, 2000 Rev. 7

1 Publication Order Number:

MC74HC139A/D

M C 7 4 H C 1 3 9 A

D u a l 1 - o f - 4 D e c o d e r /

D e m u l t i p l e x e r

HighPerformance SiliconGate CMOS

The MC74HC139A is identical in pinout to the LS139. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of two independent 1of4 decoders, each of

which decodes a twobit Address to oneoffour activelow outputs.

Activelow Selects are provided to facilitate the demultiplexing and

cascading functions. The demultiplexing function is accomplished by

using the Address inputs to select the desired device output, and

utilizing the Select as a data input.

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

Chip Complexity: 100 FETs or 25 Equivalent Gates

LOGIC DIAGRAM

A0a

A1a

SELECTa

A0b

A1b

1

SELECTb

Y0a

Y1a

Y2aY3a

Y0b

Y1b

Y2b

Y3b

ACTIVELOW

OUTPUTS

ADDRESS

INPUTS

PIN 16 = VCCPIN 8 = GND

ACTIVELOW

OUTPUTS

3

2

ADDRESS

INPUTS 13

14

15

4

5

6

7

12

11

10

9

FUNCTION TABLE

Inputs Outputs

Select A1 A0 Y0 Y1 Y2 Y3

H X X H H H H

L L L L H H H

L L H H L H H

L H L H H L H

L H H H H H L

X = dont care

SO16

D SUFFIX

CASE 751B

http://onsemi.com

1

16

PDIP16

N SUFFIX

CASE 648

116

MARKING

DIAGRAMS

1

16

MC74HC139ANAWLYYWW

1

16

HC139A

AWLYWW

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

Device Package Shipping

ORDERING INFORMATION

MC74HC139AN PDIP16 2000 / Box

MC74HC139AD SOIC16 48 / Rail

MC74HC139ADR2 SOIC16 2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

SELECTa

A1a

A0a

GND

A1b

A0b

SELECTb

VCC

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b


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MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

VCC

DC Supply Voltage (Referenced to GND)

0.5 to + 7.0

V

Vin

DC Input Voltage (Referenced to GND)

1.5 to VCC + 1.5

V

Vout

DC Output Voltage (Referenced to GND)

0.5 to VCC + 0.5

V

Iin

DC Input Current, per Pin

20

mA

Iout

DC Output Current, per Pin

25

mA

ICC

DC Supply Current, VCC and GND Pins

50

mA

PD

Power Dissipation in Still Air, Plastic DIP

SOIC Package

750

500

mW

Tstg

Storage Temperature

65 to + 150

_C

TL

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260

_C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

Derating Plastic DIP: 10 mW/_ C from 65 _ to 125 _ C

SOIC Package: 7 mW/_C from 65

_to 125

_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

VCC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

0

VCC

V

TA

Operating Temperature, All Package Types

55

+ 125

_ C

tr, tf

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0

0

0

1000

500

400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

VCC

V

55 to

25_ C

v 85_ C

v 125_ C

Unit

VIH

Minimum HighLevel Input

Voltage

Vout = 0.1 V or VCC 0.1 V

|Iout| v 20 A

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

VIL

Maximum LowLevel Input

Voltage

Vout = 0.1 V or VCC 0.1 V

|Iout| v 20 A

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

VOH

Minimum HighLevel Output

Voltage

Vin = VIH or VIL|Iout| v 20 A

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL |Iout| v 4.0 mA

|Iout| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

VOL

Maximum LowLevel Output

Voltage

Vin = VIH or VIL

|Iout| v 20 A

2.0

4.56.0

0.1

0.10.1

0.1

0.10.1

0.1

0.10.1

V

Vin = VIH or VIL |Iout| v 4.0 mA

|Iout| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

Iin

Maximum Input Leakage

Current

Vin = VCC or GND

6.0

0.1

1.0

1.0

A

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 A

6.0

4

40

160

A

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book

(DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this highimpedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to therange GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.


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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

VCCV

55 to

25_C

v 85_ C

v125

_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Select to Output Y

(Figures 1 and 3)

2.0

4.5

6.0

115

23

20

145

29

25

175

35

30

ns

tPLH,tPHL

Maximum Propagation Delay, Input A to Output Y(Figures 2 and 3)

2.04.5

6.0

11523

20

14529

25

17535

30

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

75

15

13

95

19

16

110

22

19

ns

Cin

Maximum Input Capacitance

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor HighSpeed CMOS Data Book (DL129/D).

Typical @ 25C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Decoder)* 55 pF

* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

tTHL

tTLH

Figure 1.

VCC

GND

tr

tPHL tPLH

OUTPUT Y

SELECT

90%50%

10%

90%50%10%

Figure 2.

50%

tPHLtPLH

VCC

GND

OUTPUT Y 50%

INPUT A

*Includes all probe and jig capacitance

Figure 3. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

tfVALID VALID


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PIN DESCRIPTIONS

ADDRESS INPUTS

A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13)

Address inputs. These inputs, when the respective 1of4

decoder is enabled, determine which of its four activelow

outputs is selected.

CONTROL INPUTSSelecta, Selectb (Pins 1, 15)

Activelow select inputs. For a low level on this input, the

outputs for that particular decoder follow the Address

inputs. A high level on this input forces all outputs to a high

level.

OUTPUTS

Y0a Y3a, Y0b Y3b (Pins 4 7, 12, 11, 10, 9)

Activelow outputs. These outputs assume a low level

when addressed and the appropriate Select input is active.These outputs remain high when not addressed or the

appropriate Select input is inactive.

SELECT

A0

A1

Y0

Y1

Y2

Y3

EXPANDED LOGIC DIAGRAM

(1/2 OF DEVICE)


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PACKAGE DIMENSIONS

PDIP16N SUFFIX

CASE 64808ISSUE R

MIN MINMAX MAX

I NC HE S M IL LI ME TE RS

DIM

A

B

C

D

F

G

H

J

K

L

M

S

18.806.35

3.690.391.02

0.21

2.807.50

0

0.51

19.556.85

4.440.531.77

0.38

3.307.7410

1.01

0.7400.250

0.1450.0150.040

0.008

0.1100.295

0

0.020

0.7700.270

0.1750.0210.070

0.015

0.1300.305

10

0.040

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

2.54 BSC1.27 BSC

0.100 BSC0.050 BSC

A

B

1 8

916

F

HG

D 16 PL

S

C

T

SEATING

PLANE

KJ

M

L

T A0.25 (0.010) M M

0.25 (0.010) T B AM S S

MIN MINMAX MAX

M IL LI ME TE RS I NC HE S

DIM

A

B

C

D

F

G

J

K

M

P

R

9.803.80

1.350.350.40

0.190.10

0

5.800.25

10.004.00

1.750.491.25

0.250.25

76.200.50

0.386

0.1500.0540.014

0.016

0.008

0.0040

0.229

0.010

0.393

0.1570.0680.019

0.049

0.009

0.0097

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

916

A

B

D 16PL

K

C

G

TSEATING

PLANE

R X 45

M J

F

P 8 PL

0.25 (0.010) BM M

SOIC16D SUFFIX

CASE 751B05ISSUE J


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Notes


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Notes


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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must bevalidated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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MC74HC139A/D

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datasheet74HC139