Datalink controls and LSI circuits-the confluence of architecture and technology LSI technology has been introduced into the field of data communications. Alan Weissberger describes recent developments.

Data~ink control chips (DLCCs) will simplify the implemen- tation of data-communications and control procedures. The use of protocols and the field o f datalink controls in general are surveyed. The possible role for DLCCs within micro- computer systems are described.

The growth of distributed processing, intelligent terminals and microprocessor-based remote controllers has increased the need for efficient, reliable and straightforward methods of digital data communications. Recently, a new type of large-scale integrated (LSI) circuit, the data link control chip (DLCC), has been developed which will greatly simplify the implementation of accepted data-communications and control procedures. These circuits are functionally more dense than microprocessors and continue the trend of integrating system functions, both hardware and software, into programmable MOS/LSI circuits dedicated to a particular generic task (other examples are keyboard/display, floppy disc, CRT and instru- mentation). The user realizes large savings in parts count, reduced software requirements and greatly increased system throughput. In most cases, the DLCC can easily interface to 8-bit microprocessors and some will even interface with a 16-bit microprocessor or minicomputer.

MEANING OF PROTOCOLS

A protocol is simply a set of rules that must be obeyed for orderly information exchange between two or more parties. This encompasses electrical, mechanical and functional characteristics of the data-communications link as well as the necessary control procedures to facilitate transfer of the data across the interface and to the user application program. The proliferation of different protocols and associated desig- nations by standard-making organizations (EIA, ANSI, ISO, CCITT, US Federal Government etc.) have made it extremely diff icult to identify the control functions associated with any one protocol. There are almost always two or more versions of the same protocol from the different standards groups. To remedy this situation, protocols have been divided into a layered architecture. The intent is to define unambiguously the various functions and logical operations necessary for data communications by identifying distinct levels. Each level is designed to be functionally independent of the others,

MOS Microprocessors, Signetics Corp., PO Box 9052, 811 East Arques Avenue, Sunnyvale, CA 94086, USA

but builds on previous ones. That is each level is dependent on the correct operation of the previous level in order for it to function. Data from higher levels is transparant to the lower levels.

ANSI task groups X3S3 and DISY have defined five- and six-level architectures, respectively. ISO SC16, and ECMA have defined a seven-level architecture. These are summarized in Table 1 while Figure 1 depicts the SC16 reference model. Note that levels 1 - 4 deal with actual data communications (the transport service) and levels 5 - 7 are implemented in software by users of the transport service. The levels are:

• level 1 - physical, electrical and functional interchange used to establish, maintain, and disconnect the physical link between the data terminal equipment (DTE) and the data-circuit terminating equipment (DCE) or between two DTEs,

• level 2 - data link control contains the functions needed to reliably transfer data over a single communication link; this level provides control between the two physical nodes in a network that are connected by level 1 facilities; the datalink is illustrated in Figure 2,

• level 3 - network control; this level provides the functions required for intranetwork operation, such as addressing, routing etc., above those individual link functions provided by the level 2 facilities. Level 3 facilities direct the control of switching points, they do not provide for the transfer of data between the switching points. On public data net- works this level establishes a circuit-switched call (X.21) or a node-to-node logical connection across multiple links in a packet-switched network (X.25)

• level 4 - transport end-to-end control; this level provides a network-independent interface to transport service users. The interface allows end-to-end control and information exchange across simple or complex networks. Reliability, data assurance, flow control and operational attributes are examples of the interface's characteristics,

• level 5 - session control; this level supports a dialogue (i.e. structural data) between processes. This level enquires if the program is free and if services can be allocated,

• level 6 - presentation control; this level provides requested transformations of information being transferred. This includes compaction, encryption, peripheral-device code and formatting,

• level 7 - process control; this level performs application/ system activities to provide/support the information pro- cessing function of the enterprise.

234 0 1 4 0 - 3 6 6 4 / 7 8 / 0 1 0 5 - 0 2 3 4 5 0 2 . 0 0 © 1978 IPC Business Press computer communications

Table 1. Comparison of architecture control levels

ANSI X3S3 ANSI DISY ECMA, ISO SC16

5 User control 6 Process control 7 Application control

4 System control 5 Presentation control 6 Presentation control

4 Session control 5 Session control

3 Communication network control 3 Transport control

4 Transport control end-to-end

3 Network control

2 Datalink control 2 Datalink control 2 Datalink control

1 Physical link control 1 Physical link control 1 Physical link control

5 Levels 6 Levels 7 Levels

Process control

Presentation control

Session control

" , / / / / / / / / / / ,

Transport end-to-end ~ - - - control

Network ~m- control

Link control

Physical control

-- i ra

Peerprotocol -im

Peer protocol

Peer protocol -ID

Peer protocol - i h

Process control

Presentotion control

Session control

" / / / / / / / / / /

Transport end- to - end control

Network control

Link control

Physical control

Figure 1. Layers in the 5ClS reference mode/

5

~-Tronspor t service access

4

FOCUS ON D A T A - L I N K CONTROLS

With communications and software costs consuming an ever increasing portion of the costs of a data-communication system, it makes sense to use an efficient, reliable DLC pro- cedure that is easy to implement. Having recognized this need, ANSI, ISO, and the US Federal Government have adopted the bit-oriented advanced data communication control procedures (ADCCP) as the standard for the level 2 protocol. ANSI ADCCP (BSR X3. 66) is now identical in content with ISO high-level data link control (HDLC) but differs from bit- oriented protocols (BOPs) supported by the computer manu- facturers, e.g. IBM SDLC, Univac UDLC, Burroughs BDLC etc. Despite the advantages, however, bit-oriented protocols will not replace the older character-controlled and character- count protocols very quickly. This is because much hard- ware and software is already in place to support the older character-controlled protocols, particularly the IBM Bisync and related versions. These systems represent a considerable investment in engineering resources and time. Unfortunately,

the character-controlled protocols do not conform to the layered-architecture model, but instead contain many func- tions now assigned to higher levels. If a BOP was adopted, level-2 hardware would have to be redesigned and almost all the software would have to be rewritten. Because of the magnitude of the task, the existing level-2 protocols will continue to be used for some time. Thus, it is essential for an LSl DLCC to be capable of supporting multiple data-link control procedures.

A DLC has five main functions:

framing - the process of locating the beginning and end of a message by recognizing groups of bits which act as message delimiters; each message is referred to as a frame or block, link management - controlling transmission and reception on the link; this includes controlling the direction of transmission control, who may transmit material, identi- fication of sender and receiver and the establishment and termination of a logical connection between two stations. The various physical communication link configurations are the point-to-point, multipoint, and switched types, data transfer and message integrity - the process of trans- ferring data sequentially and without error over the link. For better line utilization a synchronous transmission format is usually used. Errors are detected by parity checks (vertical and horizontal) or cyclic redundancy checks (CRC-12, CRC-CCI'I-I-). CRCs are capable of burst mul- tiple-bit error detection, a common error characteristic of communication channels. A request-for-transmission scheme is used when errors are detected. This may be the stop-and-wait type, where a positive or negative acknow- ledgement is required after each message is sent, or a con- tinuous 'go-back-N' type, where frames remain unacknow- ledged until a response is requested. In the latter type, separate send and receive frame counts are maintained by the transmitter and the receiver. When an acknowledg- ment is requested, the receiver sends back its received- frame count which is compared to the send-frame count by the transmitter. If they are not equal, the difference N represents the number of frames that must be retrans- mitred. (A variation of the 'go-back-N' is the selected

vol 1 no 5 october 1978 235

Serio,. I I------1 iCn(~emrfmoUc~Catl°ns ~ M°cdl~r~ I

,aTE, I I . . . . I J

Communications channel

Datalink

~ S e r a communications interface (DTE)

_1

DTE A

f Binary seriolinterfoce

Computer or terminal

b

control

Hardware I Rate generator 2 SYNCH/ASYNCH R/T 3 Modem control logic 4 Self-test loop-back 5 Datolink control support

I ( _1

DTE/DCE interface DCE ^

CCITT, EIA or [SO line drivers/line receivers ]-7

Figure 2. Representative SC76 reference model datalink ( a - hardware elements, b - data terminal equipment and data circuit terminating equipment)

reject supervisory command in ADCCP). In addition to detection and requests for retransmission, time outs are used to identify stations on a link that have not responded within a prescribed time period. In that case, either the link or the station is down,

• information transparency - it is often necessary to trans- Information transfer

mit binary data, floating point numbers, packed binary- coded decimal data, unique specialized codes, or machine- language computer programs. To do this, all data, includ- ing the normally restricted data-link control characters, are treated onty as specific bit patterns. There must be a way to distinguish between the pure data and the control characters of the information code set (i.e. ASCI I, EBCDIC, HOLLERITH etc.). Fortunately, this feature is inherent in BOPs, bootstrapping - secondary stations on an unbalanced link may not be able to configure themselves for data-com- munication operations. Bootstrapping provides a means for the primary station to set the initial logical states and control modes of all such secondary sta'dons. The boots- trapping is done in a transient state where no other com- munications are permitted.

BOP characteristics

The architecture of BOPs has been carefully designed to be efficient, reliable, unambiguous and widely applicable with easy to implement software. The development of the LSl DLCC means that hardware implementation is equally straight- forward.

Data is transmitted serial by bit in synchronous format on either a half-or full-duplex facility. BOPs can be employed on point-to-point, multipoint, or dial-up links. I BMs SDLC also includes a loop-mode configuration for their 3650 retail store system.

There is one frame format for all messages and link con- figurations as opposed to the numerous message formats needed: for character-controlled protocols. There are three message types: information transfer, supervisory control, and nonsequenced commands/responses. They are specified

Control field ( single octet)

Supervisory

~ rst bit sent (and received) I 2 3 4 5 6 7 8

Send sequence Poll/ Receive sequence count final count

bit

Nonsequenced ] I [ J

a

Supervisory function bits - 4 possible actions

~ \ v s

Modifier function bits up to 3: > commands and 32 responses

I 2 3 4 5 6 7 8 9 I0 II 12 13 14 15 16 Information transfer Iol .s I IP/d .r I

Supervisory I ' O I SSI 0 0 0 0 I M .r I

.onsequenced I' ' IMMIP/FIM M MI M O O O O O O OI b

Figure 3. Control field ( a - standard field (single octet), b - field extension (two octets))

by the control field (see Figure 3). Positional significance is used in place of control characters to define the various fields of a frame. The defined fields are address (A), control (C) and information (I) and frame check sequence (FCS). The A field may be recursively extended, the C field may be one or two octets and I field length is variable and may be zero.

Outside of the defined fields there are three meaningful bit sequences:

236 computer communications

Table 2. Message format comparisons

Binary synchronous communication (BSC) Block format for text message

SYN SYN SOH Header STX Text ETX BCC ETB LRC-8, CRC-12, or ITB CRC-16, depending on

character code (ASCII) transcode (EBCDIC)

Digital data-communications message Block format for all messages protocol (DDCMP)

Reader

SYN SYN SOH COUNT FLAGS Response Sequence Address CRC-16 Information CRC-16 (14-bit) (2-bit) (8 bit) (8 bit) (8 bit) (16 bit) (any number (16 bit)

of 8-bit characters)

Frame format for all messages ADCCP/HDLC (ANSI/ISO)

Header

Information (any number of bit) ECS (I 6 bit FLAG C RC-CCITT (8 bit) Inverted remainder)

Flag Address Control (8 bit) (8 bit) one or one or more two octets octets

Zero insertion/deletion, CRC accumulation

FLAG=01111110 ABORT= 01111111/11111111 IDLE=111111111111111ormorels

• 0111110 = FLAG, this delimits the start and end of each frame; the closing FLAG of one frame may be the beginning FLAG of the next frame,

• 7-14 1 s = ABORT, this prematurely terminates a frame due to a problem at the transmitting station, i.e. underrun; FLAGS may follow an ABORT to retain link continuity,

• I S or more Is = IDLE, this identifies a link state in half- duplex operation; a secondary station can use the asynchro- nous response mode to effect a line turnaround once the idle state has been detected.

Information code transparency is achieved by a technique known as zero insertion/deletion. Following the opening FLAG trans- mission, a 0 is inserted whenever five successive I s have been transmitted. The receiver also counts the number of contiguous Is. When the number is S, the sixth bit is deleted if it is a 0. Thus it is impossible for any bit sequence in a frame to be mis- interpreted as a FLAG, ABORT, or IDLE. Character-controlled DLCs require a specific transparent mode of operation. This mode is initiated and terminated by specific sequences of characters. Furthermore, a bit sequence matching the code of data link escape (DLE) must be preceded by a DLEcharacter. This involves considerable software overhead.

Error checking is on the entire frame between opening and closing FLAGs, using the CCITT CRC polynomial X l~ + X 12 + X s + I as a divisor, with thedividend preset to 16 Is and the inverted remainder transmitted as the FCS. The 0s inserted to maintain transparency are not included in the FCS calculation. An error- free frame will yield the hexadecimal constant FoB8 as the CRC remainder. Most other DLCs only check the information

field for errors and do not check control messages or acknow- ledgements.

Full-duplex operation is facilitated by acknowledging a group of frames rather than an individual acknowledgement of each frame. Frames can be outstanding (unacknowledged, unreceived or being received) during transmission due to the 'go-back-N frames' request-for-transmission technique previously discussed. This will also reduce line turnarounds in half-duplex operations.

Line use is efficient because of:

• the 'go-back-N' frames technique, • ability to acknowledge a group of frames while trans-

mitting data in an information frame, • the ability to terminate transmission in an information

frame rather than requiring a separate control message to do SO.

The ability to bootstrap secondary stations is provided by using the 'set initialization mode' command.

The number and type of commands and responses are modular. The specific combination can be optimally configured to suit a given application. Many of the manufacturers versions of BOPs include user-defined commands and responses in the nonsequenced control field, although these are not recognized by ISO or ANSl.

Table 2 shows the various message-block and frame formats for character-controlled Bisync (I BM), character count DDCMP (DEC) and bit-oriented ADCCP/HDLC (ANSl/ISO).

vol I no 5 october 1978 237

Table 3. Hierarchy of protocols

Level (ISO) Function and examples

I Physical link between DTE and network (DCE or DTE) Electrical - RS232C, CCITT V.28, V.35;

RS 422, RS423; CCITT V.10 (X.26), V . l l (X.27) M I L - STD - 188 - I 14

Functional and mechanical - RS232C, RS449; CCITT V.24, V.35, V-Series revised, X.21/ X.24; ISO 2110, 2593, 4902, 4903

Datalink control between physical nodes Char;~cter controlled - IBM BISYNC, ANSI

X3.28, ISO 1745 Character count - DEC DDCM P Bit oriented - ANSI ADCCP/ISO HDLC,

IBM SDLC, UNIVAC UDLC, BURROUGHS BDLC

3,4 Communication path control between ori- ginating and target nodes Packet switching - CCITT X.25" Call establishment - C C I T T X.21 t Front-end communicat ions- IBM NCP,

DEC NSP Code independent headings - ANSI X3-

281

5, 6, 7 System and user control within one com- puter No standards exist for these levels. Computer manufacturers network software architecture includes: IBM SNA, DEC DECNET, UNIVAC DCA, NCR DNA, COMTEN CNS

t X.21 encompasses levels 1,2, and 3. It is a general-purpose inter- face for synchronous transmission on public data networks and has been implemented in the Nordic countries {Norway, Sweden, Finland and Denmark) and lapan. ANSI is considering it for adoption as American National Standard BSR X3.69. * X.25 specifies X.21 level 1, HDLC LAPB level 2, and its packet- switching procedures for levels 3 and 4.

This is a rigidly-defined point-to-point class of DLC procedure between the DTE and the DCE (network). Each station on a balanced (point-to-point) link has identical data-transfer and link-control responsibilities. Either station may initiate a trans- mission at the first opportunity. An older level-2 version (LAP) used the concept of an unbalanced link where a control station was responsible for configuring tributary stations, selecting them to receive and soliciting them to transmit. The Datapac network in Canada and the Telenet network in the USA use the LAP version of level 2. Telenet embeds an HDLC frame in a Bisync transparent-mode message block.

LSI SERIAL DATA RECEIVER/TRANSMITTER

The advantages of using programmable LSI circuits as serial data-communication interfaces are well established. LSl circuits' functional density shrinks the size, power and cost of equivalent hardware, while programmable operation per- mits the same part to be used as a standard component throughout the system. This standardization, in turn, simpli- fies incoming inspection and test, inventory/stocking, main- tenance and replacement of defective units. Adaptability is another important benefit of programmability. Changes in baud rates, transmission formats, character lengths, error checking and protocols can be accommodated exclusively through reconfiguration of mode and control registers. This has a significant effect on redesign time and cost and minimizes product obsolescence.

The task of this class of circuit is to assemble 5- to 8-bit characters from a received binary serial data stream (receive) and to serialize characters into a transmitted sequence of binary pulses (transmit). This function is necessary whenever character- or word-oriented devices communicate with one another over a serial-communications facility. Examples are terminal to local CPU, terminal to remote CPU and CPU- CPU communications. Equipment requiring a binary serial interface includes intelligent terminals, cluster controllers, front-end processors, remote data concentrators, intelligent (statistical) multiplexers, network diagnostic processors and data-communication test equipment.

Some LSl circuits support asynchronous transmission only (UART), synchronous only (USRT) or both (USART). Many of the newer LSl receiver/transmitters are bus-oriented, operate from a single +SV power supply, contain modem- control pins, bit-rate generators, include loopback and echo modes and have datalink control- support. Table 4 compares the attributes of the four available USART circuits.

X.21 and X.25

CCITT's Recommendations X.21 and X.25 (see Table 3) each specify a different level 2 procedure. X.21 is partially character- oriented, using International Alphabet No 5 (IAS) specified by X.4. This is essentially the same as ASCII in the USA. There are four phases of operation: idle, call establishment, data and disconnection. The call establishment phase spans levels 2 and 3. Character synchronization during this phase uses two or more 7-bit SYN characters with odd parity for each signalling sequence. The data phase specifies a full-duplex, transparent, mutually agreed DLC which promises to be ADCCP/HDLC. Thus, a DLCC supporting X.21 must switch between character- controlled call establishment and bit-oriented data phases.

The level-2 interface for X.25 is a subset of ISO HDLC which is known as a link access procedure balanced (LAPB) interface.

FUNCTIONS OF DLCC

The DLCC contains logic to support bit-oriented and possibly other DLC procedures. High-speed data rates (up to 2 Mbit/s), full-duplex operation, CRC generation/checking, zero insertion/ deletion, FLAG and ABORT generation/detection and stripping, interrupt or direct memory access (DMA) interface, 8- or 16-bit databus are characteristics of the DLCC. Table 5 provides a survey of announced DLCCs.

Most DLCCs contain a secondary-station address register and comparitor. A station on a multipoint link should receive a BOP frame only if the A field matches its own address or a global (eight 1 s) address. When the secondary receive mode is enabled, the DLCC compares the A field with the software- programmed secondary-address register. A match enables

238 computer communications

Table 4. Comparison o f MOS/LSI USARTS

Signetics Intel Western Digital Zilog 2651 8251A UC1671B (Astro) Z80-$10"

Number of pins 28 28 40 40 Power supplies +5V +5V +5V, +12V, - 5 V +5V Up oriented Yes Yes No Z80 only Bit-rate generator for TxC and RxC Yes Yes No No Maximum data transfer rates (BPS) 1M 64K 1M 550K/880K Self-test modes Local and None Local None

remote Modem control pins 5 4 6 4/channel Data set change indicators Yes No No Yes Transparent mode Yes No Yes No Auto-echo mode Yes No Yes No CRC generation/checking No No No Yes Full-duplex channels 1 1 1 2

* Also is a DLCC.

Table 5. Announced DLCCs

Standard Western Signetics Microsystems Zilog Fairchild Motorola Intel Digital

Feature 2652 5025 $ I0 3846 6854 8273 1933

Max data rate (bit/s) 1 M/2M 1 .SM Package pins 40 40 Databus pins 8/16 8/16 Modem control/general

purpose I/O pins None None Character length (bits) 1 -8 1 -8 System clock required No No Separate Rx/Tx interrupts/

DMA pins Yes Yes Rx FIFO buffers 6 None None Tx FIFO buffers 7 None None Loopback self-test mode Yes Yes Multiprotocol (BISYNC,

DDCMP) Yes Yes BISYNC CRC handling External External

Secondary address compare Global address recognition Automatic extended address,

extended control Residual character handling BOP underrun linefill

NRZI coding Rx clock recovery Short frame rejection

Yes Yes Yes Yes

No Rx Yes Yes ABORTs ABORTs ABORT- ABORT- Flags FLAGs No No No No Yes Yes

550K/880K 1M 1M/1.5M/2M 64K 1M 40 40 28 40 40 8 8/16 8 8 8

4/channel 6 4 10 6 5-82 5-84 5 - 8 8 5 - 8 Yes No Yes No No

No Yes No Yes Yes 2 None 2 None None None None 2 None None No Yes No Yes Yes

Yes t Yes No No No Start/stop Yes NA NA NA CRC-16 Yes Yes No Yes Yes Yes Yes No Yes Yes

No Yes 3 Yes No Yes Yes No Rx FCS- ABORTs ABORTs ABORTs FLAGs ABORT- ABORT-

FLAGs FLAGs No Yes Yes Yes No No No Yes No No Yes Yes

Yes Yes s ABORTs ABORT- F LAGs Yes Yes Yes

1 Supports asynchronous, 2 full duplex channels 2 8-bit SYN character restricts character length to 8 bits in synchronous mode 3 Single address octet must have bit 0 = ! 4 Transmit character length may be 1 - 8 bits 5 Independent Tx residual character register 6 In addition to receive holding and shift registers 7 In addition to transmitter holding and shift registers. NA = not applicable Rx = receiver Tx = transmitter

vol 1 no 5 october 1978 239

~ 8 - b i t i= Dotabus microprocessor Address Control

~ Reset H ~ - ff L. i L..TxC /~ou er rStatus J r" i Ln I

/RxC w l =4 - / DBo-7 I MPCC I-- , L , , ,

~ > ~ I TxSO m _ A 2-O R/W DBEN CEI . . . . ~ LU

TR,E T,E Modem I [ I contro, I_ LOCO C,S logic

latch and TS buffer J J

Syn~ronous modem

RTS,CTS, DTR,DSR, DCD

Figure 4. 8-bit microprocessor interfaced to the Signetics 2652 MPCC (Possible microprocessor interrupt requests are: RxDA, RxSA, TxBE and TxU. Other 2652 status signals and possible users are: S /F line - idle indicator, frame delimeter; RxA hand- shake on RxE, line turn around control; TxA handshake on TxE, line turn around control. Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice versa, RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low. Corresponding high and low order bits o f DB should be OR tied.)

the receiver datapath from the serial receiver datapin to the databus. Detection of the global address field will similarly enable the receiver.

The automatic extended A and C field switches the charac- ter length (receive or transmit) to the length required by the I field characters. If the I field character length is 8 bits, nothing is done. If the length is less than 8 bits, the software (or firmware) must do the character-length switching. This usually requires one to four instructions, not much appreciable overhead in nonDMA systems. (The DLCC secondary address compare is disabled during extended A field reception.)

Residual character handling is necessary when the last I field character length does not match the programmed charac- ter length. This is quite possible in the ADCCP when a pure bit stream I field may be transmitted. In SDLC when the I field is not a multiple of 8 bit, a residual character must be transmitted to guarantee that the I field is a multiple of 8 bit. In either ADCCP or SDLC, the transmitter character length can be out of step with that of the receiver, this may happen in multiplexer or data concentrator applications. The DLCC should be able to handle all of these situations by transmitting and receiving a last-data (residual) character of 1 to 8 bit. This usually requires changing the character length on transmit and detecting the number of bits in the character received just before the FCS.

When the controller (CPU or DMA) cannot service the DLCC transmitter within one character time, the transmitted BOP frame must be aborted. The DLCC BOP line fill should be eight consecutive binary ls. This ABORT bit pattern may be followed by seven or more additional 1 s (a total of at least 15 contiguous 1 s) which idles the link, or it may be followed by FLAGs which retains link continuity. The latter situation is desirable when the controller wishes to retransmit the aborted frame without necessitating a line turnaround. Some DLCCs can line fill with ABORTs or ABORT FLAGs during an underrun.

Short-frame rejection is a DLCC feature whichprevents a received frame of less than 32 bits, or a frame with an exten- ded A or C field pending, being accepted. Recall that a mini- mum frame consists of an 8-bit address, 8-bit control and 16- bit FCS. If a shorter frame is received, it must be rejected. To implement this feature, DLCCs may ignore the short frame, automatically send and detect an ABORT or activate an Invalid frame interrupt.

For BOPs, a coding technique known as NRZI (non return to zero inverted) can be used to effectively reduce cabling costs for limited-distance communications without modems.

(Line driver and receiver integrated circuits that meet the E IA RS422 specification can transfer serial data at speeds up to 100kbit/s at 4000 ft. Packaged line drivers and receivers can extend this distance to a few miles). NRZI coding inverts the line state whenever a binary 0 is encountered in the serial data stream. BOPs insert a 0 after five consecutive ls have been transmitted. With line transitions guaranteed within 6 bit times, it becomes possible to recover the received clock from the received serial data, thereby eliminating the clock wire from the source to the destination. NRZI also permits BOPs to be transmitted and received, utilizing lower cost asynchronous modems, provided the speed degradation can be tolerated. (Asynchronous modems are generally limited to 1 800 bit/s.)

Self-test capability is essential to bring a system up and to isolate defective equipment on the datalink. Used in con- junction with analogue and digital modem Ioopbacks, a loop- back mode on the DLCC will identify communication pro- blems or malfunctions. Local Ioopback internally loops the transmitted serial data and transmit clock back onto the receiver serial data and receiver clock respectively; remote Ioopback does the opposite. In either case, the program at the source compares the received characters with the charac- ters it had transmitted to verify the correct operation of the link.

M U L T I P R O T O C O L D L C C

In addition to the BOP features discussed, several DLCCs can also support character-controlled and/or character-count protocols. One such device is the Signetics 2652 MPCC. The 2652, like all LSl receiver/transmitters, has two independent interfaces, one to the communication line and the other to the bidirectional databus. Integrated circuit line drivers and receivers meeting the appropriate EIA, CCl]-I- or ISO electri- cal standards are needed for each signal to and from the communications line interface. The databus interface is to a CPU for mode initialization, command generation, status checking and character transfers. The latter can also be handled by a DMA controller.

Figure 4 shows an 8-bit microprocessor interfaced to the 2652 which in turn is connected to a synchronous modem. Line driver and receiver circuits convert the TTL voltage levels of the 2652 to the EIA/CCII-F/ISO voltage levels of the chosen modem. External logic (a simple latch) generates modem signals REQUEST-TO-SEND (RTS) and DATA

240 computer communications

Chorocter count Address PTR R/W control

DMA control ler

2652 Address ond control

Dotabus

IR.DREQ

I To processor

I RRBO

DB 15-00 Dotobus Dotobus txDA

RxA

RxE RxSA

FxBE TxA TxE

2652 TxU S/F

A2 - AO BYTE R/W RESET CE MM DBEN

Processor ond support logic

RxDA TxBE

R/W memory

Address, R/W controls RxC TxC RxSI T x S O Address,R/Wcontrol Address,CE,R/W

System address and control bus

Figure 5. DMA/processor interface (For non DMA operation, TxBE and RxDA are sent to the processor which then loads or reads data characters as required.)

TERMINAL READY (DTR). CLEAR-TO-SEND (CTS), DATA SET READY (DSR) and DATA CARRIER DETECT (DCD) are read by the CPU through a three-state buffer. The modem supplies both the transmit and receive clocks (TxC and RxC). Serial data is transmitted on TxSO and received on RxSI. The straight forward address and control signals re- quried by the 2652 enables it to be cleanly interfaced to most 8/16 bit microprocessors. The BYTE input determines if an 8 or 16 bit databus is to be used. If BYTE is high, an 8-bit bus is specified. The corresponding high-and low-order bits are directly tied together (i.e. bit 0 with 8, bit I with 9 etc.). If BYTE is low, a 16-bit bus transfers two bytes in parallel between 2652 and the CPU. The status signals shown could be interrupt inputs or program-polled status bits. These include Rx DATA AVAILABLE, Rx STATUS CHANGE, Tx BUFFER EMPTY and Tx UNDERRUN.

The DMA/processor interface in Figure 5 is most advan- tageous with high-speed serial data rates. At 2Mbit/s with 8-bit characters, the transmitter and receiver must each be serviced within 4#s to prevent underrun and overrun, respec- tively. At that speed, hardware control of I/O is essential for all but the fastest processors.

During MPCC initialization, 16-bit mode can be used to transfer a pair of 8-bit configuration commands for each write instruction. Frame transmission is initiated by simul-

taneously setting the TRANSMIT START OF MESSAGE command bit and loading the transmit data register with the first character of the frame. This will cause the opening FLAG and A field to be serialized and transmitted.

After the processor initializes the 2652 and the DMA controller, all data transfers can be made directly from 2652 to memory (receive) or from memory to 2652 (transmit) in 8-bit mode. The 2652 generates read and write requests (RDREQ and WRREQ) while the DMA supplies the address and control signals to access the 2652. The DMA controller increments the address pointer, decrements the character count and tests it for zero for each character transferred. Two sets of these registers are necessary for a full-duplex DMA.

As the last character is being transmitted the DMA con- troller sends a data-transfer-complete interrupt to the CPU which responds by directing the 2652 to send the frame check sequence and closing FLAG via the TRANSMIT END OF MESSAGE command bit. On the receiving end, closing FLAG detection will generate a RxSA interrupt with the RECEIVED END OF MESSAGE status bit set. The receiving CPU will then examine selected bits to determine whether or not a valid frame was received. A complete description of 2652 MPCC operation can be found in the datasheet for that device.

G L O S S A R Y O F D A T A - C O M M U N I C A T I O N S A B B R E V I A T I O N S

ADCCP

BOP CRC CTS DCE DLC DLCC DMA DSR

- advanced data-communication control DTE procedure

- bit-oriented protocol DTR - cyclic redundancy check FCS - clear-to-send HDLC - data circuit terminating equipment LSI - datalink control N RZI - datalink control chip RTS - direct memory access SDLC - data set ready TTL

data-terminal equipment

- data terminal read - frame-check sequence - high level datalink control - large-scale integrated - nonreturn to zero inverted - request to send - synchronous datalink control - transistor-transistor logic

vol I no 5 october 1978 241