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DESCRIPTION
Data Types. Each data object has a type associated with it. The type defines the set of values that the object can have and the set of operation that are allowed on it. Data types defined in the standard package. Predefined data type are as follows: Bit Bit_vector Boolean Character - PowerPoint PPT Presentation
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04/21/23 DSD, USIT, GGSIPU 1
Data Types
• Each data object has a type associated with it.
• The type defines the set of values that the object can have and the set of operation that are allowed on it.
04/21/23 DSD, USIT, GGSIPU 2
Data types defined in the standard package
• Predefined data type are as follows:– Bit– Bit_vector– Boolean– Character– File_open_kind*– File_open_status*– Integer– Natural– Positive– Real– Severity_level– String– Time*
04/21/23 DSD, USIT, GGSIPU 3
User-defined Types
• The Syntax isTYPE identifier is Type_definition;
Example:
type small_int is range 0 to 1024;
type my_word_length is range 31 downto 0;subtype data_word is my_word_length range 7 downto 0;
04/21/23 DSD, USIT, GGSIPU 4
Data Types
• A type declaration defines the name of the type and the range of the type.
• Type declaration are allowed in package declaration sections, entity declaration sections, architecture declaration sections, subprogram declaration section and process declaration sections.
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04/21/23 DSD, USIT, GGSIPU 6
Types available in VHDL
• Scalar types– Integer types– Real types– Enumerated– Physical
• Composite Types– Arrays type– Records
• Access Types (equivalent of pointers in C)• File types
04/21/23 DSD, USIT, GGSIPU 7
Scalar Types
• Scalar types describe objects that can hold , at most, one value at a time.
• Integer Type– It is same as mathematical integers.– All of the normal predefined mathematical
function apply to integer types.– Minimum Range: -2,147,483,647 to
12,147,483,647
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Example - IntegerArchitecture test of test isBegin
Process (x)Variable a: integer;Begin
a := 1; --ok a := -1 ; -- oka := 1.0; -- error
End process;End test;
04/21/23 DSD, USIT, GGSIPU 9
Real Types
• Real Types are used to declare objects that emulate mathematical real numbers.
• Real number can be used to represent numbers out of the range of integer value as well as fractional values.
• Minimum Range: -1.0E+38 to +1.0E+38
04/21/23 DSD, USIT, GGSIPU 10
Example – Real Types
Architecture test of test issignal a : real;
Begina <= 1.0; -- oka <= 1; -- errora <= -1.0E10; -- oka <= 1.5E-20; --oka <= 5.3 ns; -- error
End test;
04/21/23 DSD, USIT, GGSIPU 11
Enumerated types
• Enumerated type is used to represent exactly the values required for a specific operation.
• All of the values of an enumerated type are user-defined.
• This values can be identifiers or single-character literals.
• A typical example: TYPE fourval IS (‘x’, ‘0’, ‘1’, ‘z’);
TYPE color IS (red,yellow, blue,green,orange);
04/21/23 DSD, USIT, GGSIPU 12
IEEE standard 1164Type std_logic is (
‘U’, -- uninititalized‘X’, -- forcing unknown‘0’, -- forcing 0‘1’, -- forcing 1‘Z’, -- high impedence‘W’, -- weak unknown‘L’, -- weak 0‘H’, -- weak 1‘-’); -- don’t care
04/21/23 DSD, USIT, GGSIPU 13
Physical Types
• Physical types are used to represent physical quantities such as distance,current, time and so on.
• A physical type provides for a base unit,and successive units are then defined in terms of this unit.
• The smallest unit represented is one base unit.• The largest unit is determined by the range
specified in physical type declaration.• TIME is a predefined physical types
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Example – Physical TypePackage example is
type current is range 0 to 10000000000units
na;ua = 1000 na; -- nano ampma = 1000 ua; -- micro ampa = 1000 ma;
End units;type load_factor is (small, med, big);
End example;
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Architecture delay-cal of delay isBegin
delay <= 10 ns when (load = small) else20 ns when (load = med) else30 ns when (load = big) else40 ns;
out-current <= 1000 ua when (load= small) else1 ma when (load = med) else100 ua;
End delay-cal;
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Predefined physical type - TimeType TIME is Range <implementation defined>
units
fs; --femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nansecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
End units;
04/21/23 DSD, USIT, GGSIPU 17
Composite Types
• Arrays Type are groups of elements of the same type.– Arrays are useful for modeling linear structure
such as RAMs and ROMs.
• Record Types allow the grouping of elements of different types.– Record are useful for modeling data packets,
instructions and so on.
04/21/23 DSD, USIT, GGSIPU 18
Array Types
• Array types group one or more elements of the same type together as a single object
• Each element of the array can be accessed by one or more array indices.
• Format of type declaration:TYPE data_bus IS array (0 to 31) of BIT;
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Array slices and Ranges
• Assignment of arrays preserves the left-to-right ordering regardless of the direction.
• ExampleSignal x : std_logic_vector(0 to 3);--case 1Signal y : std_logic_vector(3 downto 0); --case2X <= “1010”;Y <= “0101”;
04/21/23 DSD, USIT, GGSIPU 20
Cont..
• The assignment x<=y is equivalent to:X(0) <= Y(3); -- the left elementX(1) <= y(2);X(2) <=Y(1);X(3) <=Y(0); -- the right elementsThe array range for case I in 0 to 3 loop, the elements of
the array would be accessed from left to right.The array range for caseII in 3 downto 0 loop, the
elements of the array would be accessed from right to left.
04/21/23 DSD, USIT, GGSIPU 21
Multidimensional Array
Type aggregate is array (range<>) of std_logic;
Type identifier_a is array(range<>) of aggregate;
Constant identifier_b : identifier_a :=
((e1,e2…en), -- E1
(e1,e2,…en), --E2
.
(e1,e2,…en)); --En
04/21/23 DSD, USIT, GGSIPU 22
Example-Multidimensional arrays
Library ieee;Use ieee.std_logic_1164.all;Package memory is
constant width : integer := 3;constant memsize : integer := 7;Type data_out is array (0 to width) of std_logic;Type mem_data is arrary (0 to memsize) of data_out;
End memory;
04/21/23 DSD, USIT, GGSIPU 23
Library ieee;
Use ieee.std_logic_1164.all;
Use work.memory.all;
Enity rom is -- ROM declaration
port (addr : in integer;
data : out data_out;
cs : in std_logic;
End rom;
04/21/23 DSD, USIT, GGSIPU 24
Architecture basic of rom is
constant z_state : data_out := (‘z’, ‘z’, ‘z’, ‘z’);
constant x_state : data_out := (‘x’, ‘x’, ‘x’, ‘x’);constant rom_data : mem_data := (
(‘0’, ‘0’, ‘0’, ‘0’),(‘0’, ‘0’, ‘0’, ‘1’),(‘0’, ‘0’, ‘1’, ‘0’),(‘0’, ‘0’, ‘1’, ‘1’),(‘0’, ‘1’, ‘0’, ‘0’),(‘0’, ‘1’, ‘0’, ‘1’),(‘0’, ‘1’, ‘1’, ‘0’),(‘0’, ‘1’, ‘1’, ‘1’), );
Begindata <= rom_data (addr) when cs = ‘1’ else
x_state when cs = ‘0’ elsez_state;
End basic;
04/21/23 DSD, USIT, GGSIPU 25
Record Types
• Record types group object of may types together as a single object.
• Each element of the record can be accessed by its field name.
• Record elements can include elements of any type, including arrays and records.
• The elements of a record can be of the same type or different types.
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Features of Records
• A record is referenced by a single identifier.• Records are very useful to collapse multiple
related elements into a single type so that record objects can be handle as a objects.
• They are very useful in Bus Functional Models and test benches to pass a set of information to another process or another component.
• Values can be assigned to a record type using aggregates in a manner similar to aggregates for arrays.
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Limitation
• Many synthesizers can compile records provided the elements of the record are of type Bit, bit_vector, boolean, std_ulogic, Std_ulogic_vector, integer or subtypes of these types.
• However, most current synthesizers do not accept record aggregate assignments, and thus require individual assignment of the record elements.
04/21/23 DSD, USIT, GGSIPU 28
Example - Records
Type optype is (add,sub,mpy,div,jmp);
Type instruction is
Record -- declaration of record
opcode : optype; -- field of record
src : integer;
dat : integer;
End record;
04/21/23 DSD, USIT, GGSIPU 29
Process (x)variable inst : instruction;variable source,dat : integer;variable operator : optype;
Beginsource := inst.src; -- okdest := inst.src; -- oksource := inst.opcode; -- erroroperator := inst.opcode; --okinst.src := dest; --ok
04/21/23 DSD, USIT, GGSIPU 30
Access Types
• Access types allow the designer to model objects of a dynamic nature.
E.g. Queues, FIFO, Creating and Maintaining of a linked list.
• Only variables can be declared as access types.
• Used in Sequential processing• Not Synthesizeable statement.
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Cont..
• Access types are used to declare values that access dynamically allocated variables.
• Dynamically allocated variables are referenced, not by name, but by an access value that acts like a pointer to the variable.
• Access types are used in the TextIO subprograms to read and write text strings.
• Access types were efficiently used in VHDL in the functional modeling of large memories where fixed memory allocation is not realistic.
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File Types
• A file type allows declaration of objects that have a type FILE.
• A file object type is actually a subset of the variable object type.
• A variable object can be assigned with a variable assignment, while a file object cannot be assigned.
• A file object can be read from, written to, and checked for end of file only with special procedure and functions.
04/21/23 DSD, USIT, GGSIPU 33
Cont..
• File types are typically used to access files in the host environment.
• File types are used to define objects representing files in the host system environment.
• The value of a file object is the sequence of values contained in the host environment.
• Package TextIO provides for the definition of file type TEXT as “type TEXT is file of string”.
• TextIO package supports human readable IO.
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Characters, Strings
• To use character literal in a VHDL Code, one puts it in a single quotation mark.
‘a’, ‘B’, ‘,’• A string of character are placed in double
quotation marks: “aa”, “bb”
Any printing character can be included inside a string.
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Bit Strings
• A bit-strings represents a sequence of bit values. E.g.Binary : B “1100_1001”, b “1001011”
Hexagonal : X “C9”, X “4b”
Octal : O “311”, o “113”