Data Sheet of Pic

© 2007 Microchip Technology Inc. Preliminary DS70152D-page 1

dsPIC33F/PIC24H

1.0 DEVICE OVERVIEW

This document defines the programming specificationfor the dsPIC33F 16-bit Digital Signal Controller (DSC)and PIC24H 16-bit Microcontroller (MCU) families. Thisprogramming specification is required only for thosedeveloping programming support for the dsPIC33F/PIC24H family. Customers only using one of thesedevices should use development tools that alreadyprovide support for device programming.

This document includes programming specificationsfor the following devices:

• dsPIC33FJ64GP206• dsPIC33FJ64GP306• dsPIC33FJ64GP310





• dsPIC33FJ64MC506• dsPIC33FJ64MC508• dsPIC33FJ64MC510




• PIC24HJ64GP206• PIC24HJ64GP210• PIC24HJ64GP506




• PIC24HJ256GP610• dsPIC33FJ12GP201• dsPIC33FJ12GP202

• dsPIC33FJ12MC201• dsPIC33FJ12MC202• PIC24HJ12GP201

• PIC24HJ12GP202

2.0 PROGRAMMING OVERVIEW OF THE dsPIC33F/PIC24H

There are two methods of programming the dsPIC33F/PIC24H family of devices discussed in this programming specification. They are:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Enhanced In-Circuit Serial Programming

The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe chip.

The Enhanced ICSP protocol uses a faster method thattakes advantage of the programming executive, asillustrated in Figure 2-1. The programming executiveprovides all the necessary functionality to erase, pro-gram and verify the chip through a small command set.The command set allows the programmer to programthe dsPIC33F/PIC24H Programming Specificationdevices without having to deal with the low-levelprogramming protocols of the chip.

dsPIC33F/PIC24H Flash Programming Specification

dsPIC33F/PIC24H PROGRAMMING SPECIFICATION

DS70152D-page 2 Preliminary © 2007 Microchip Technology Inc.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This specification is divided into major sections thatdescribe the programming methods independently.Section 3.0 “Device Programming – EnhancedICSP” describes the Enhanced ICSP method.Section 5.0 “Device Programming – ICSP” describesthe ICSP method.

2.1 Power Requirements

All devices in the dsPIC33F/PIC24H family are dual volt-age supply designs: one supply for the core and anotherfor the peripherals and I/O pins. A regulator is providedon-chip to alleviate the need for two external voltagesupplies.

All of the dsPIC33F/PIC24H devices power their coredigital logic at a nominal 2.5V. To simplify systemdesign, all devices in the dsPIC33F/PIC24H Program-ming Specification family incorporate an on-chip regu-lator that allows the device to run its core logic fromVDD.

The regulator provides power to the core from the otherVDD pins. A low-ESR capacitor (such as tantalum) mustbe connected to the VDDCORE pin (Figure 2-2). Thishelps to maintain the stability of the regulator. Thespecifications for core voltage and capacitance arelisted in Section TABLE 8-1: “AC/DC Characteristicsand Timing Requirements”.

FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

2.2 Program Memory Write/Erase Requirements

The program Flash memory on the dsPIC33F/PIC24Hhas a specific write/erase requirement that must beadhered to for proper device operation. The rule is thatany given word in memory must not be written withoutfirst erasing the page in which it is located. Thus, theeasiest way to conform to this rule is to write all the datain a programming block within one write cycle. The pro-gramming methods specified in this document complywith this requirement.

dsPIC33F/PIC24H

ProgrammerProgramming

Executive

On-Chip Memory

Note: A program memory word can be pro-grammed twice before an erase, but onlyif (a) the same data is used in both pro-gram operations or (b) bits containing ‘1’are set to ‘0’ but no ‘0’ is set to ‘1’.

Note 1: These are typical operating voltages. Refer to Section TABLE 8-1: “AC/DC Charac-teristics and Timing Requirements” for the full operating ranges of VDD and

VDD

VDDCORE

VSS

dsPIC33F/PIC24H

CF

3.3V



2.3 Pin Diagrams

The pin diagrams for the dsPIC33F/PIC24H devicefamily are shown in the following figures. The pins thatare required for programming are listed in Table 2-1.The MCLR, PGC1, PGD1, PGC2, PGD2, PGC3 andPGD3 pins are shown in bold letters in the figures.Refer to the appropriate device data sheet for completepin descriptions.

TABLE 2-1: PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING)

Pin NameDuring Programming

Pin Name Pin Type Pin Description

MCLR MCLR P Programming Enable

VDD and AVDD(1) VDD P Power Supply

VSS and AVSS(1) VSS P Ground

VDDCORE VDDCORE P Regulated Power Supply for Core

PGC1 PGC1 I Primary Programming Pin Pair: Serial Clock

PGD1 PGD1 I/O Primary Programming Pin Pair: Serial Data

PGC2 PGC2 I Secondary Programming Pin Pair: Serial Clock

PGD2 PGD2 I/O Secondary Programming Pin Pair: Serial Data

PGC3 PGC3 I Tertiary Programming Pin Pair: Serial Clock

PGD3 PGD3 I/O Tertiary Programming Pin Pair: Serial Data

Legend: I = Input, O = Output, P = PowerNote 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground

(AVSS).



Pin Diagrams

64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14PGD2/EMUD2/SOSCI/T4CK/CN1/RC13OC1/RD0IC4/INT4/RD11

IC2/U1CTS/INT2/RD9IC1/INT1/RD8VSS

OSC2/CLKO/RC15OSC1/CLKIN/RC12VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6U1RX/SDI1/RF2U1TX/SDO1/RF3

COFS/RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6SDI2/CN9/RG7

SDO2/CN10/RG8MCLR

VSS

VDD

AN3/CN5/RB3AN2/SS1/LVDIN/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1PGD3/EMUD3/AN0/VREF+/CN2/RB0

OC

8/C

N16

/RD

7

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

VD

DC

OR

E

RG

1R

F1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/C

N18

/RF

5U

2RX

/CN

17/R

F4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9

AN5/IC8/CN7/RB5AN4/IC7/CN6/RB4

IC3/INT3/RD10

VD

D

RF

0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

dsPIC33FJ64GP206dsPIC33FJ128GP206



Pin Diagrams (Continued)

64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2




SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/C

N16

/RD

7

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

VD

DC

OR

E

RG

1R

F1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

RF

0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4





64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2




SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/C

N16

/RD

7

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

VD

DC

OR

E

RG

1C

1TX

/RF

1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

C1R

X/R

F0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

dsPIC33FJ256GP506




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2




SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/C

N16

/RD

7

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

VD

DC

OR

E

C2T

X/R

G1

C1T

X/R

F1

C2R

X/R

G0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

C1R

X/R

F0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4





80-Pin TQFP

72

74

73

71

70

69

68

67

66

65

64

63

62

61

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

50

49

48

47

46

45

44

21

41

4039383736353423 24 25 26 27 28 29 30 31 32 33dsPIC33FJ64GP708

17

18

19

75

1

57

56

55

54

53

52

51

60

59

58

43

42

76

78

77

79

2280

IC5/

RD

12O

C4/

RD

3

OC

3/R

D2

OC

2/R

D1

CS

CK

/RG

14A

N23

/CN

23/R

A7

AN

22/C

N22

/RA

6

C2R

X/R

G0

C2T

X/R

G1

C1T

X/R

F1

C1R

X/R

F0

CS

DO

/RG

13

CS

DI/R

G12

OC

8/C

N16

/RD

7

OC

6/C

N14

/RD

5

OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

IC3/RD10

VSS

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RX/RF2

U1TX/RF3

PGC2/EMUC2/SOSCO/T1CK/

PGD2/EMUD2/SOSCI/CN1/RC13V

RE

F+

/RA

10

VR

EF-/

RA

9

AV

DD

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2R

X/C

N17

/RF

4

IC8/

U1R

TS

/CN

21/R

D15

U2T

X/C

N18

/RF

5

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

VSS

VDD

COFS/RG15

AN16/T2CK/T7CK/RC1

TDO/AN21/INT2/RA13

TMS/AN20/INT1/RA12

TC

K/A

N12

/RB

12

TD

I/AN

13/R

B13

U2R

TS

/AN

14/R

B14

AN

15/O

CF

B/C

N12

/RB

15

VD

D

VD

DC

OR

E

OC

5/C

N13

/RD

4

IC6/

CN

19/R

D13

SDA1/RG3

SDI1/RF7

SDO1/RF8

AN5/CN7/RB5

VS

S

OSC2/CLKO/RC15O

C7/

CN

15/R

D6

SCK1/INT0/RF6

IC7/

U1C

TS

/CN

20/R

D14

SDA2/INT4/RA3

SCL2/INT3/RA2

dsPIC33FJ128GP708

CN0/RC14




9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 7820

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

7677

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

AN

26/R

E2

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

AN

25/R

E1

AN

24/R

E0

RG

0

AN

28/R

E4

AN

27/R

E3

RF0 VD

DC

OR

E

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14VR

EF+

/RA

10VR

EF-

/RA

9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

VDD

TMS/RA0

AN20/INT1/RA12AN21/INT2/RA13

AN5/CN7/RB5AN4/CN6/RB4


SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLRA

N12

/RB

12A

N13

/RB

13A

N14

/RB

14A

N15

/OC

FB/C

N12

/RB

15

RG

1R

F1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSS

VD

D

TDI/RA4

TCK

/RA

1

100-Pin TQFP


100




9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

7677

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

AN

26/R

E2

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

AN

25/R

E1

AN

24/R

E0

RG

0

AN

28/R

E4

AN

27/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


EF+

/RA

10VR

EF-

/RA

9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0




SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLR

AN

12/R

B12

AN

13/R

B13

AN

14/R

B14

AN

15/O

CFB

/CN

12/R

B15

RG

1C

1TX

/RF1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSSV

DD

TDI/RA4

TCK

/RA

1

100-Pin TQFP

dsPIC33FJ256GP510

100




9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 7820

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

7677

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

AN

26/R

E2

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

AN

25/R

E1

AN

24/R

E0

C2R

X/R

G0

AN

28/R

E4

AN

27/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


EF+

/RA

10VR

EF-

/RA

9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0




SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLRA

N12

/RB

12A

N13

/RB

13A

N14

/RB

14A

N15

/OC

FB/C

N12

/RB

15

C2T

X/R

G1

C1T

X/R

F1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSS

VD

D

TDI/RA4

TCK

/RA

1

100-Pin TQFP

dsPIC33FJ128GP710

100

dsPIC33FJ256GP710

dsPIC33FJ64GP710




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25


IC2/U1CTS/FLTB/INT2/RD9IC1/FLTA/INT1/RD8VSS


SCL1/RG2


PWM3H/RE5PWM4L/RE6PWM4H/RE7


SDO2/CN10/RG8MCLR

VSS

VDD

AN3/INDX/CN5/RB3AN2/SS1/LVDIN/CN4/RB2


OC

8/U

PD

N/C

N16

/RD

7

PW

M3L

/RE

4P

WM

2H/R

E3

PW

M2L

/RE

2

VD

DC

OR

E

PW

M1L

/RE

0C

1TX

/RF

1

PW

M1H

/RE

1

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/C

N18

/RF

5U

2RX

/CN

17/R

F4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9

AN5/QEB/IC8/CN7/RB5AN4/QEA/IC7/CN6/RB4

IC3/INT3/RD10V

DD

C1R

X/R

F0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

dsPIC33FJ64MC506




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25


IC2/U1CTS/FLTB/INT2/RD9IC1/FLTA/INT1/RD8VSS


SCL1/RG2


PWM3H/RE5PWM4L/RE6PWM4H/RE7


SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/U

PD

N/C

N16

/RD

7

PW

M3L

/RE

4P

WM

2H/R

E3

PW

M2L

/RE

2

VD

DC

OR

E

PW

M1L

/RE

0C

1TX

/RF

1

PW

M1H

/RE

1

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9

AN5/QEB/IC8/CN7/RB5AN4/QEA/IC7/CN6/RB4

IC3/INT3/RD10

VD

D

C1R

X/R

F0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

dsPIC33FJ128MC506 dsPIC33FJ64MC506dsPIC33FJ128MC706




80-Pin TQFP

72

74

73

71

70

69

68

67

66

65

64

63

62

61

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

50

49

48

47

46

45

44

21

41

4039383736353423 24 25 26 27 28 29 30 31 32 33

17

18

19

75

1

57

56

55

54

53

52

51

60

59

58

43

42

76

78

77

79

2280

IC5/

RD

12

OC

4/R

D3

OC

3/R

D2

OC

2/R

D1

PW

M2L

/RE

2P

WM

1H/R

E1

PW

M1L

/RE

0

CR

X2/

RG

0

C2T

X/R

G1

C1T

X/R

F1

C1R

X/R

F0

PW

M3L

/RE

4

PW

M2H

/RE

3

OC

8/C

N16

/UP

DN

/RD

7

OC

6/C

N14

/RD

5

OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

IC3/RD10

VSS

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RX/RF2

U1TX/RF3

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14


VR

EF+

/RA

10

VR

EF-/

RA

9

AV

DD

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2R

X/C

N17

/RF

4

IC8/

U1R

TS

/CN

21/R

D15

U2T

X/C

N18

/RF

5

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

PWM4H/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3




VSS

VDD

PWM3H/RE5

PWM4L/RE6

TDO/FLTB/INT2/RE9

TMS/FLTA/INT1/RE8

TC

K/A

N12

/RB

12

TD

I/AN

13/R

B13

U2R

TS

/AN

14/R

B14

AN

15/O

CF

B/C

N12

/RB

15

VD

D

VD

DC

OR

E

OC

5/C

N13

/RD

4

IC6/

CN

19/R

D13

SDA1/RG3

SDI1/RF7

SDO1/RF8

AN5/QEB/CN7/RB5

VS

S

OSC2/CLKO/RC15

OC

7/C

N15

/RD

6

SCK1/INT0/RF6

IC7/

U1C

TS

/CN

20/R

D14

INT4/RA3

INT3/RA2

dsPIC33FJ64MC508




80-Pin TQFP

72

74

73

71

70

69

68

67

66

65

64

63

62

61

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

50

49

48

47

46

45

44

21

41

4039383736353423 24 25 26 27 28 29 30 31 32 33

17

18

19

75

1

57

56

55

54

53

52

51

60

59

58

43

42

76

78

77

79

2280

IC5/

RD

12O

C4/

RD

3

OC

3/R

D2

OC

2/R

D1

PW

M2L

/RE

2P

WM

1H/R

E1

PW

M1L

/RE

0

CR

X2/

RG

0

C2T

X/R

G1

C1T

X/R

F1

C1R

X/R

F0

PW

M3L

/RE

4

PW

M2H

/RE

3

OC

8/C

N16

/UP

DN

/RD

7

OC

6/C

N14

/RD

5

OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

IC3/RD10

VSS

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RX/RF2

U1TX/RF3


PGD2/EMUD2/SOSCI/CN1/RC13V

RE

F+

/RA

10

VR

EF-/

RA

9

AV

DD

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2R

X/C

N17

/RF

4

IC8/

U1R

TS

/CN

21/R

D15

U2T

X/C

N18

/RF

5

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

PWM4H/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3




VSS

VDD

PWM3H/RE5

PWM4L/RE6

TDO/FLTB/INT2/RE9

TMS/FLTA/INT1/RE8

TC

K/A

N12

/RB

12

TD

I/AN

13/R

B13

U2R

TS

/AN

14/R

B14

AN

15/O

CF

B/C

N12

/RB

15

VD

D

VD

DC

OR

E

OC

5/C

N13

/RD

4

IC6/

CN

19/R

D13

SDA1/RG3

SDI1/RF7

SDO1/RF8

AN5/QEB/CN7/RB5

VS

S

OSC2/CLKO/RC15O

C7/

CN

15/R

D6

SCK1/INT0/RF6

IC7/

U1C

TS

/CN

20/R

D14

SDA2/INT4/RA3

SCL2/INT3/RA2

dsPIC33FJ128MC708




92

94

93

91

90

89

88

87

86

85

84

83

82

81

80

79

78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

76

77

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

96

98

97

99

27 46 47 48 49 50

55

54

53

52

51

100

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

PW

M2L

/RE

2C

SD

O/R

G13

CS

DI/R

G12

CS

CK

/RG

14P

WM

1H/R

E1

PW

M1L

/RE

0

RG

0

PW

M3L

/RE

4P

WM

2H/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

RA3

RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


VRE

F+/R

A10

VRE

F-/R

A9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

PWM3H/RE5

PWM4L/RE6PWM4H/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0

AN20/FLTA/INT1/RE8AN21/FLTB/INT2/RE9

AN5/QEB/CN7/RB5AN4/QEA/CN6/RB4


SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLR

AN

12/R

B12

AN

13/R

B13

AN

14/R

B14

AN

15/O

CFB

/CN

12/R

B15

RG

1C

1TX

/RF1

OC

8/U

PD

N//C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSS

VD

D

TDI/RA4

TCK

/RA

1

100-Pin TQFP

dsPIC33FJ64MC510




92

94

93

91

90

89

88

87

86

85

84

83

82

81

80

79

78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

76

77

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

96

98

97

99

27 46 47 48 49 50

55

54

53

52

51

100

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

PW

M2L

/RE

2C

SD

O/R

G13

CS

DI/R

G12

CS

CK

/RG

14P

WM

1H/R

E1

PW

M1L

/RE

0

RG

0

PW

M3L

/RE

4P

WM

2H/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


EF+

/RA

10VR

EF-

/RA

9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

PWM3H/RE5

PWM4L/RE6PWM4H/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0




SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLRA

N12

/RB

12A

N13

/RB

13A

N14

/RB

14A

N15

/OC

FB/C

N12

/RB

15

RG

1C

1TX

/RF1

OC

8/U

PD

N//C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSSV

DD

TDI/RA4

TCK

/RA

1

100-Pin TQFP

dsPIC33FJ128MC510dsPIC33FJ256MC510




92

94

93

91

90

89

88

87

86

85

84

83

82

81

80

79

78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

95

1

76

77

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

96

98

97

99

27 46 47 48 49 50

55

54

53

52

51

100

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

PW

M2L

/RE

2C

SD

O/R

G13

CS

DI/R

G12

CS

CK

/RG

14P

WM

1H/R

E1

PW

M1L

/RE

0

C2R

X/R

G0

PW

M3L

/RE

4P

WM

2H/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


VRE

F+/R

A10

VRE

F-/R

A9

AVD

D

AVS

S

AN

8/R

B8

AN

9/R

B9

AN

10/R

B10

AN

11/R

B11

VD

D

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VD

D

VS

S

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

PWM3H/RE5

PWM4L/RE6PWM4H/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0




SDI2/CN9/RG7

SDO2/CN10/RG8



COFS/RG15

VDD

SS2/CN11/RG9

MCLR

AN

12/R

B12

AN

13/R

B13

AN

14/R

B14

AN

15/O

CFB

/CN

12/R

B15

C2T

X/R

G1

C1T

X/R

F1

OC

8/U

PD

N//C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VS

S

VSS

VD

D

TDI/RA4

TCK

/RA

1

100-Pin TQFP

dsPIC33FJ64MC710dsPIC33FJ128MC710dsPIC33FJ256MC710




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2


RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2


SDO2/CN10/RG8MCLR

VSS

VDD

AN3/CN5/RB3AN2/SS1/CN4/RB2


OC

8/C

N16

/RD

7

RG

13R

G12

RG

14

VD

DC

OR

E

RG

1R

F1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/C

N18

/RF

5U

2RX

/CN

17/R

F4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

RF

0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

PIC24HJ64GP206PIC24HJ128GP206PIC24HJ256GP206

Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2


RG15AN16/T2CK/T7CK/RC1AN17/T3CK/T6CK/RC2


SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/C

N16

/RD

7

RG

13R

G12

RG

14

VD

DC

OR

E

RG

1R

F1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

RF

0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

PIC24HJ128GP306




64-Pin TQFP

12345678910111213 36

353433

32313029282726

64 63 62 61 60 59 58 57 56

141516

17 18 19 20 21 22 23 24 25




SCL1/RG2




SDO2/CN10/RG8MCLR

VSS

VDD



OC

8/C

N16

/RD

7

CS

DO

/RG

13C

SD

I/RG

12C

SC

K/R

G14

VD

DC

OR

E

RG

1C

1TX

/RF

1

RG

0

OC

2/R

D1

OC

3/R

D2

PG

C1/

EM

UC

1/A

N6/

OC

FA/R

B6

PG

D1/

EM

UD

1/A

N7/

RB

7A

VD

D

AV

SS

U2C

TS

/AN

8/R

B8

AN

9/R

B9

TM

S/A

N10

/RB

10T

DO

/AN

11/R

B11

VS

S

VD

D

TC

K/A

N12

/RB

12T

DI/A

N13

/RB

13U

2RT

S/A

N14

/RB

14A

N15

/OC

FB

/CN

12/R

B15

U2T

X/S

CL2

/CN

18/R

F5

U2R

X/S

DA

2/C

N17

/RF

4

SDA1/RG3

43424140393837

44

484746

50 495154 53 5255

45

SS2/T5CK/CN11/RG9


IC3/INT3/RD10

VD

D

C1R

X/R

F0

OC

4/R

D3

OC

7/C

N15

/RD

6O

C6/

IC6/

CN

14/R

D5

OC

5/IC

5/C

N13

/RD

4

PIC24HJ64GP506PIC24HJ128GP506




9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

951

7677

72

71

70

69

68

67

66

75

74

73

58

57

2423

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN23

/CN

23/R

A7AN

22/C

N22

/RA6

AN26

/RE2

RG

13R

G12

RG

14AN

25/R

E1AN

24/R

E0

RG

0

AN28

/RE4

AN27

/RE3

RF0

VDD

CO

RE


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


VREF

+/R

A10

VREF

-/RA9

AVD

D

AVSS

AN8/

RB8

AN9/

RB9

AN10

/RB1

0AN

11/R

B11

V DD

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

V DD

VSS

PGC

1/EM

UC

1/AN

6/O

CFA

/RB6

PGD

1/EM

UD

1/AN

7/R

B7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6

AN31/RE7AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13



SDI2/CN9/RG7

SDO2/CN10/RG8



RG15

VDD

SS2/CN11/RG9

MCLR

AN12

/RB1

2AN

13/R

B13

AN14

/RB1

4AN

15/O

CFB

/CN

12/R

B15

RG

1R

F1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VSS

VSS

VDD

TDI/RA4

TCK/

RA1

100-Pin TQFP


100





9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

951

7677

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN

23/C

N23

/RA

7A

N22

/CN

22/R

A6

AN

26/R

E2

RG

13R

G12

RG

14A

N25

/RE

1A

N24

/RE

0

RG

0

AN

28/R

E4

AN

27/R

E3

C1R

X/R

F0

VD

DC

OR

E


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


VREF

+/R

A10

VREF

-/RA9

AVD

D

AVSS

AN8/

RB8

AN9/

RB9

AN10

/RB1

0AN

11/R

B11

V DD

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

VDD

VSS

PGC

1/EM

UC

1/AN

6/O

CFA

/RB6

PGD

1/EM

UD

1/AN

7/R

B7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6

AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2


SCK2/CN8/RG6

VDD

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4


SDI2/CN9/RG7

SDO2/CN10/RG8



RG15

VDD

SS2/CN11/RG9

MCLR

AN12

/RB1

2AN

13/R

B13

AN14

/RB1

4AN

15/O

CFB

/CN

12/R

B15

RG

1C

1TX

/RF

1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VSS

VSS

VD

D

TDI/RA4

TCK/

RA1

100-Pin TQFP

PIC24HJ64GP510

100

PIC24HJ128GP510




9294 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78

20

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

65

64

63

62

61

60

59

26

56

4544434241403928 29 30 31 32 33 34 35 36 37 38

17

18

19

21

22

951

7677

72

71

70

69

68

67

66

75

74

73

58

57

24

23

25

9698 979927 46 47 48 49 50

55

54

53

52

51

OC

6/C

N14

/RD

5O

C5/

CN

13/R

D4

IC6/

CN

19/R

D13

IC5/

RD

12O

C4/

RD

3O

C3/

RD

2O

C2/

RD

1

AN23

/CN

23/R

A7AN

22/C

N22

/RA6

AN26

/RE2

RG

13R

G12

RG

14AN

25/R

E1AN

24/R

E0

C2R

X/R

G0

AN28

/RE4

AN27

/RE3

C1R

X/R

F0

VDD

CO

RE


OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS


VRE

F+/R

A10

VRE

F-/R

A9

AVD

D

AVSS

AN8/

RB8

AN9/

RB9

AN10

/RB1

0AN

11/R

B11

V DD

U2C

TS

/RF1

2U

2RT

S/R

F13

IC7/

U1C

TS

/CN

20/R

D14

IC8/

U1R

TS

/CN

21/R

D15

V DD

VSS

PGC

1/EM

UC

1/AN

6/O

CFA

/RB6

PGD

1/EM

UD

1/AN

7/R

B7

U2T

X/C

N18

/RF5

U2R

X/C

N17

/RF4

AN29/RE5

AN30/RE6

AN31/RE7AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

VDD

TMS/RA0




SDI2/CN9/RG7

SDO2/CN10/RG8



RG15

VDD

SS2/CN11/RG9MCLR

AN12

/RB1

2AN

13/R

B13

AN14

/RB1

4AN

15/O

CFB

/CN

12/R

B15

C2T

X/R

G1

C1T

X/R

F1

OC

8/C

N16

/RD

7O

C7/

CN

15/R

D6

TDO/RA5

INT4/RA15

INT3/RA14

VSS

VSS

VSS

VDD

TDI/RA4

TCK/

RA1

100-Pin TQFP

100

PIC24HJ256GP610




18-PIN SDIP18-PIN SOIC

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

INT0/RP7/CN23/RB7

PGD3/EMUD3/SOSCI/RP4/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2

PGC1/EMUC1/AN3/RP1/CN5/RB1

PGD1/EMUD1/AN2/RP0/CN4/RB0

AN6/RP15/CN11/RB15

AN7/RP14/CN12/RB14

SCL1/RP9/CN21/RB9

SDA1/RP8/CN22/RB8

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

VSS

VSS

VDD

VDDCORE

MCLR

dsPIC

33FJ12GP

201 P

IC24H

J12GP

201





20-PIN SDIP20-PIN SSOP

INT0/RP7/CN23/RB7

MCLR

Vss

PWM1H1/RP14/CN12/RB14

VDDCORE

PWM2H1/SCL1/RP8/CN22/RB8

PWM2L1/SDA1/RP9/CN21/RB9

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11


PGC2/EMC2/AN1/VREF-/CN3/RA1



OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2


PGC1/EMUC1/AN3/RP1/CN5/RB1 PWM1L2/RP13/CN13/RB13

PWM1L1/RP15/CN11/RB15


VDD

VSS

dsP

IC33F

J12MC

201


INT0/RP7/CN23/RB7

MCLR

AV ss

AN7/RP14/CN12/RB14

VDDCORE

ASCL1/RP6/CN24/RB6

TDO/SDA1/RP9/CN21/RB9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AN4/RP2/CN6/RB2


OSCI/CLKI/CN29/RA3

AN5/RP3/CN7/RB3

PGD3/EMUD3/SOSC/RP4/CN1/RB4

AVDD

AN8/RP13/CN13/RB13

AN6/RP15/CN11/RB15

AN9/RP12/CN14/RB12

ASDA1/RP5/CN27/RB5

Vss

OSCO/CLK1/CN30/RA2

VDD

TMS/RP11/CN15/RB11

TDI/RP10/CN16/RB10

Vss

TCK/SCL1/RP8/CN22/RB8





dsPIC

33FJ12GP

202 P

IC24H

J12GP

202





INT0/RP7/CN23/RB7

MCLR

AVss


VDDCORE

ASCL1/RP6/CN24/RB6

TDO/PWM2L1/SDA1/RP9/CN21/RB9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AN5/RP3/CN7/RB3





OSCI/CLKI/CN30/RA2

AN4/RP2/CN6/RB2


PGC1/EMUC1/AN3/RP1/CN5/RB1 PWM1L2/RP13/CN13/RB13



ASDA1/RP5/CN27/RB5

Vss

OSCO/CLKO/CN29/RA3

VDD

TMS/PWM1L3/RP11/CN15/RB11

TDI/PWM1H3/RP10/CN16/RB10

Vss

TCK/PWM2H1/SCL1/RP8/CN22/RB8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

d

sPIC

33FJ12M

C202

AVDD




28-Pin QFN 6*6mm

1

2

3

4

5

6

7

21

20

19

18

17

16

15

28 27 26 25 24 23 22

8 9 10 11 12 13 14

V SS



AN4/RP2/CN6/RB2

AN5/RP3/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

VDDCORE

TDI/RP10/CN16/RB10

TMS/RP11/CN15/RB11

AN9/RP12/CN14/RB12

TDO/SDA1/RP9/CN21/RB9

AN8/RP13/CN13/RB13

PG

C3/

EM

UC

3/S

OS

CO

/T1C

K/C

N0/

RA

4

PG

D3/

EM

UD

3/S

OS

CI/R

P4/

CN

1/R

B4

VD

D

AS

DA

1/R

P5/

CN

27/R

B5

AS

CL1

/RP

6/C

N24

/RB

6

INT

0/R

P7/

CN

23/R

B7

TC

K/S

CL1

/RP

8/C

N22

/RB

8

PG

D2/

EM

UD

2/A

N0/

VR

EF

+/C

N2/

RA

0

PG

C2/

EM

UC

2/A

N1/

VR

EF

-/C

N3/

RA

1

MC

LR

AN

6/R

P15

/CN

11/R

B15

AN

7/R

P14

/CN

12/R

B14

V SS

dsPIC33FJ12GP202

AV

SS

AV

DD

PIC24HJ12GP202




28-Pin QFN 6*6mm

1

2

3

4

5

6

7

21

20

19

18

17

16

15

8 9 10 11 12 13 14

dsPIC33FJ12MC202



AN4/RP2/CN6/RB2

AN5/RP3/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

VSS

VDDCORE

TDI/PWM1H3/RP10/CN16/RB10

TMS/PWM1L3/RP11/CN15/RB11


TDO/PWM2L1/SDA1/RP9/CN21/RB9


PG

C3/

EM

UC

3/S

OS

CO

/T1C

K/C

N0/

RA

4

PG

D3/

EM

UD

3/S

OS

CI/R

P4/

CN

1/R

B4

VD

D

AS

DA

1/R

P5/

CN

27/R

B5

AS

CL1

/RP

6/C

N24

/RB

6

INT

0/R

P7/

CN

23/R

B7

TC

K/P

WM

2H1/

SC

L1/R

P8/

CN

22/R

B8

PG

C2/

EM

UC

2/A

N1/

VR

EF

-/C

N3/

RA

1

PG

D2/

EM

UD

2/A

N0/

VR

EF

+/C

N2/

RA

0

MC

LR

AVD

D

AV

ss

PW

M1L

1/R

P15

/CN

11/R

B1

5

PW

M1H

1/ R

P14

/CN

12/R

B14

28 27 26 25 24 23 22

VSS



2.4 Memory Map

The program memory map extends from 0x0 to0xFFFFFE. Code storage is located at the base of thememory map and supports up to 88K instructions(about 256 Kbytes). Table 2-2 shows the programmemory size and number of erase and program blockspresent in each device variant. Each erase block, orpage, contains 512 instructions and each programblock, or row, contains 64 instructions.

Locations 0x800000 through 0x800FFE are reservedfor executive code memory. This region stores theprogramming executive and the debugging executive.The programming executive is used for device pro-

gramming and the debug executive is used for in-circuitdebugging. This region of memory can not be used tostore user code.

Locations 0xF80000 through 0xF80017 are reservedfor the device Configuration registers.

Locations 0xFF0000 and 0xFF0002 are reserved forthe Device ID Word registers. These bits can be usedby the programmer to identify what device type is beingprogrammed. They are described in Section 7.0“Device ID”. The Device ID registers read outnormally, even after code protection is applied.

Figure 2-3 shows the memory map for the dsPIC33F/PIC24H family variants.

TABLE 2-2: CODE MEMORY SIZE

dsPIC33F/PIC24H DeviceUser Memory Address

Limit(Instruction Words)

Write Blocks Erase BlocksExecutive Memory Address

Limit (Instruction Words)

dsPIC33FJ64GP206 0x00ABFE (22K) 344 43 0x800FFE (2K)






dsPIC33FJ128GP206 0x0157FE (44K) 688 86 0x800FFE (2K)









dsPIC33FJ64MC506 0x00ABFE (22K) 344 43 0x800FFE (2K)





dsPIC33FJ128MC506 0x0157FE (44K) 688 86 0x800FFE (2K)







PIC24HJ64GP206 0x00ABFE (22K) 344 43 0x800FFE (2K)




PIC24HJ128GP206 0x0157FE (44K) 688 86 0x800FFE (2K)











dsPIC33FJ12GP201 0x001FFE (4K) 64 8 0x8007FE (1K)

dsPIC33FJ12GP202 0x001FFE (4K) 64 8 0x8007FE (1K)

dsPIC33FJ12MC201 0x001FFE (4K) 64 8 0x8007FE (1K)

dsPIC33FJ12MC202 0x001FFE (4K) 64 8 0x8007FE (1K)

PIC24HJ12GP201 0x001FFE (4K) 64 8 0x8007FE (1K)

PIC24HJ12GP202 0x001FFE (4K) 64 8 0x8007FE (1K)

TABLE 2-2: CODE MEMORY SIZE (CONTINUED)



FIGURE 2-3: PROGRAM MEMORY MAP

Use

r M

emor

yS

pace

0x000000

Configuration Registers

Code Memory

0x02AC000x02ABFE

Con

figur

atio

n M

emor

yS

pace

(87552 x 24-bit)

0x800000

0xF80000(12 x 8-bit) 0xF80017

0xF80018

Device ID

0xFEFFFE0xFF0000

0xFFFFFE

Reserved

0xF7FFFE

Reserved

0x800FFE0x801000

Executive Code Memory

0x7FFFFE

Reserved

0xFF00020xFF0004

Reserved

(2 x 16-bit)

Note: The address boundaries for user Flash and Executive code memory are device dependent.

User Flash

(2048 x 24-bit)



3.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the devicethrough Enhanced ICSP and the programming execu-tive. The programming executive resides in executivememory (separate from code memory) and is executedwhen Enhanced ICSP Programming mode is entered.The programming executive provides the mechanismfor the programmer (host device) to program and verifythe dsPIC33F/PIC24H Programming Specificationfamily devices using a simple command set and com-munication protocol. There are several basic functionsprovided by the programming executive:

• Read Memory• Erase Memory

• Program Memory• Blank Check• Read Executive Firmware Revision

The programming executive performs the low-leveltasks required for erasing, programming and verifyinga device. This allows the programmer to program thedevice by issuing the appropriate commands and data.Table 3-1 summarizes the commands. A detaileddescription for each command is provided inSection 4.2 “Programming Executive Commands”.

TABLE 3-1: COMMAND SET SUMMARY

The programming executive uses the device’s dataRAM for variable storage and program execution. Afterthe programming executive has run, no assumptionsshould be made about the contents of data RAM.

3.1 Overview of the Programming Process

Figure 3-1 shows the high-level overview of theprogramming process. After entering Enhanced ICSPmode, the programming executive is verified. Next, thedevice is erased. Then, the code memory is pro-grammed, followed by the nonvolatile device Configu-ration registers. Code memory (including theConfiguration registers) is then verified to ensure thatprogramming was successful.

After the programming executive has been verifiedin memory (or loaded if not present), the dsPIC33F/PIC24H Programming Specification can be pro-grammed using the command set shown in Table 3-1.

FIGURE 3-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

Command Description

SCHECK Sanity check

READC Read Configuration registers or Device ID registers

READP Read code memory

PROGC Program a Configuration register and verify

PROGP Program one row of code memory and verify

PROGW Program one word of code memory and verify

QBLANK Query if the code memory is blank

QVER Query the software version

Start

Done

Perform BulkErase

Program Memory

Verify Program

Enter Enhanced ICSP™

Program Configuration Bits

Verify Configuration Bits

Exit Enhanced ICSP



3.2 Confirming the Presence of the Programming Executive

Before programming can begin, the programmer mustconfirm that the programming executive is stored inexecutive memory. The procedure for this task isshown in Figure 3-2.

First, ICSP mode is entered. Then, the unique Applica-tion ID Word stored in executive memory is read. If theprogramming executive is resident, the Application IDWord is 0xBB, which means programming can resumeas normal. However, if the Application ID Word is not0xBB, the programming executive must be programmedto executive code memory using the method described inSection 6.0 “Programming the Programming Exec-utive to Memory”.

Section 5.0 “Device Programming – ICSP” describesthe ICSP programming method. Section 5.11 “Readingthe Application ID Word” describes the procedure forreading the Application ID Word in ICSP mode.

FIGURE 3-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE

3.3 Entering Enhanced ICSP Mode

As shown in Figure 3-3, entering Enhanced ICSP Program/Verify mode requires three steps:

1. The MCLR pin is briefly driven high then low.2. A 32-bit key sequence is clocked into PGD.

3. MCLR is then driven high within a specifiedperiod of time and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in the case of dsPIC33F/PIC24H devices. There is no minimum time require-ment for holding at VIH. After VIH is removed, an inter-val of at least P18 must elapse before presenting thekey sequence on PGD.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 0x4D434850 in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An intervaltime of at least P19 and P7 must elapse before present-ing data on PGD. Signals appearing on PGD before P7has elapsed will not be interpreted as valid.

On successful entry, the program memory can beaccessed and programmed in serial fashion. While inthe Program/Verify mode, all unused I/Os are placed inthe high-impedance state.

Is

Start

Enter ICSP™ Mode

Application ID0xBB?

Resident in Memory

Yes

No

Prog. Executive is

Application IDRead the

be ProgrammedProg. Executive must

from Address0x807F0

Finish



FIGURE 3-3: ENTERING ENHANCED ICSP™ MODE

3.4 Blank Check

The term “Blank Check” implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as a ‘1’.

The Device ID registers (0xFF0000:0xFF0002) can beignored by the Blank Check since this region storesdevice information that cannot be erased. The deviceConfiguration registers are also ignored by the BlankCheck. Additionally, all unimplemented memory spaceshould be ignored from the Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

3.5 Code Memory Programming

3.5.1 PROGRAMMING METHODOLOGY

Code memory is programmed with the PROGPcommand. PROGP programs one row of code memorystarting from the memory address specified in thecommand. The number of PROGP commands requiredto program a device depends on the number of writeblocks that must be programmed in the device.

A flowchart for programming code memory is shown inFigure 3-4. In this example, all 88K instruction words ofa dsPIC33F/PIC24H device are programmed. First, thenumber of commands to send (called ‘RemainingC-mds’ in the flowchart) is set to 1368 and the destinationaddress (called ‘BaseAddress’) is set to ‘0’. Next, onewrite block in the device is programmed with a PROGPcommand. Each PROGP command contains data forone row of code memory of the dsPIC33F/PIC24H.After the first command is processed successfully,‘RemainingCmds’ is decremented by ‘1’ and comparedwith ‘0’. Since there are more PROGP commands tosend, ‘BaseAddress’ is incremented by 0x80 to point tothe next row of memory.

On the second PROGP command, the second row isprogrammed. This process is repeated until the entiredevice is programmed..

MCLR

PGD

PGC

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 0x4D434850

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VIH VIH

Note: If a bootloader needs to be programmed,the bootloader code must not be pro-grammed into the first page of code mem-ory. For example, if a bootloader located ataddress 0x200 attempts to erase the firstpage, it would inadvertently erase itself.Instead, program the bootloader into thesecond page, e.g. 0x400.



FIGURE 3-4: FLOWCHART FOR PROGRAMMING CODE MEMORY

3.5.2 PROGRAMMING VERIFICATION

After code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared against the copy held inthe programmer’s buffer.

The READP command can be used to read back all theprogrammed code memory.

Alternatively, you can have the programmer performthe verification after the entire device is programmed,using a checksum computation.

3.5.3 CHECKSUM COMPUTATION

Only the Configuration registers are included in thechecksum computation. The Device ID and Unit ID arenot included in the checksum computation.

Table 3-2 shows how this 16-bit computation can bemade for each dsPIC33F and PIC24H device. Compu-tations for read code protection are shown bothenabled and disabled. The checksum values shownhere assume that the Configuration registers are alsoerased. However, when code protection is enabled,the value of the FGS register is assumed to be 0x5.

IsPROGP response

PASS?

IsRemainingCmds

‘0’?

BaseAddress = 0x0RemainingCmds = 1368

RemainingCmds =RemainingCmds – 1

BaseAddress =BaseAddress + 0x80

No

No

Yes

Yes

Start

FailureReport Error

Send PROGPCommand to Program

BaseAddress

Finish



TABLE 3-2: CHECKSUM COMPUTATION

DeviceRead CodeProtection

Checksum ComputationErasedValue

Value with0xAAAAAA at 0x0

and LastCode Address

dsPIC33FJ64GP206 Disabled CFGB + SUM(0:00ABFF) 0x03BC 0x01BE

Enabled CFGB 0x05BA 0x05BA











dsPIC33FJ128GP206 Disabled CFGB + SUM(0:0157FF) 0x01BC 0xFFBE


















Item Description:

SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)

CFGB = Configuration Block (masked)

= Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))

(for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202)

= Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))

(for all other devices)



dsPIC33FJ64MC506 Disabled CFGB + SUM(0:00ABFF) 0x03BC 0x01BE










dsPIC33FJ128MC506 Disabled CFGB + SUM(0:0157FF) 0x01BC 0xFFBE














PIC24HJ64GP206 Disabled CFGB + SUM(0:00ABFF) 0x03BC 0x01BE






TABLE 3-2: CHECKSUM COMPUTATION (CONTINUED)





Item Description:











PIC24HJ128GP206 Disabled CFGB + SUM(0:0157FF) 0x01BC 0xFFBE


















dsPIC33FJ12GP201 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E

Enabled CFGB 0x060A 0x060A

dsPIC33FJ12GP202 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E


dsPIC33FJ12MC201 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E


dsPIC33FJ12MC202 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E


PIC24HJ12GP201 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E


PIC24HJ12GP202 Disabled CFGB + SUM(0:001FFF) 0xD60C 0xD40E


TABLE 3-2: CHECKSUM COMPUTATION (CONTINUED)





Item Description:









3.6 Configuration Bits Programming

3.6.1 OVERVIEW

The dsPIC33F/PIC24H has Configuration bits storedin twelve 8-bit Configuration registers, aligned on evenconfiguration memory address boundaries. These bitscan be set or cleared to select various device configu-rations. There are three types of Configuration bits:system operation bits, code-protect bits and unit ID bits.The system operation bits determine the power-on set-tings for system level components, such as oscillatorand Watchdog Timer. The code-protect bits preventprogram memory from being read and written.

The register descriptions for the FBS, FSS, FGS,FOSCSEL, FOSC, FWDT, FPOR and FICD Configuration registers are shown in Table 3-3.

The Configuration register map is shown in Table 3-4..

Note: If any of the code-protect bits in FBS, FSSor FGS is clear, then the entire devicemust be erased before it can be reprogrammed.



TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION

Bit Field Register Description

RBS<1:0> FBS Boot Segment Data RAM Code Protection11 = No RAM is reserved for Boot Segment10 = Small-sized Boot RAM[128 bytes of RAM are reserved for Boot Segment]01 = Medium-sized Boot RAM[256 bytes of RAM are reserved for Boot Segment]00 = Large-sized Boot RAM[1024 bytes of RAM are reserved for Boot Segment]

[Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]

BSS<2:0> FBS Boot Segment Program Memory Code Protection111 = No Boot Segment110 = Standard security, Small-sized Boot Program Flash[Boot Segment ends at 0x0003FF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x0007FF in other all other devices.] 101 = Standard security, Medium-sized Boot Program Flash[Boot Segment ends at 0x0007FF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x001FFF in all other devices.] 100 = Standard security, Large-sized Boot Program Flash[Boot Segment ends at 0x000FFF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x003FFF in all other devices.] 011 = No Boot Segment010 = High security, Small-sized Boot Program Flash[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x0007FF in all other devices.]001 = High security, Medium-sized Boot Program Flash[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x001FFF in all other devices.]000 = High security, Large-sized Boot Program Flash[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.Boot Segment ends at 0x003FFF in all other devices.]

BWRP FBS Boot Segment Program Memory Write Protection 1 = Boot Segment program memory is not write-protected0 = Boot program memory is write-protected



RSS<1:0> FSS Secure Segment Data RAM Code Protection11 = No Data RAM is reserved for Secure Segment10 = Small-sized Secure RAM [(256 – N) bytes of RAM are reserved for Secure Segment in all other devices.]01 = Medium-sized Secure RAM[(2048 – N) bytes of RAM are reserved for Secure Segment in all other devices.]00 = Large-sized Secure RAM [(4096 – N) bytes of RAM are reserved for Secure Segment in all other devices.] where N = Number of bytes of RAM reserved for Boot Sector.

Note 1: This bit is Reserved in dsPIC33FJ12GP201/202,dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]

2: If the defined Boot Segment size is greater than or equal tothe defined Secure Segment, then the Secure Segment sizeselection has no effect and the Secure Segment is disabled.

SSS<2:0> FSS Secure Segment Program Memory Code Protection111 = No Secure Segment110 = Standard security, Small-sized Secure Program Flash [Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in other devices.]101 = Standard security, Medium-sized Secure Program Flash [Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in other devices.]100 = Standard security, Large-sized Secure Program Flash[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in other devices.]011 = No Secure Segment010 = High security, Small-sized Secure Program Flash [Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in other devices.]001 = High security, Medium-sized Secure Program Flash [Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in other devices.]000 = High security, Large-sized Secure Program Flash[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in other devices.]

[Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]

SWRP FSS Secure Segment Program Memory Write Protection 1 = Secure Segment program memory is not write-protected0 = Secure program memory is write-protected[Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]

TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)




GSS<1:0> FGS General Segment Code-Protect bit11 = Code protection is disabled10 = Standard security code protection is enabled0x = Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202. In all other devices, high security code protection is enabled.

GWRP FGS General Segment Write-Protect bit1 = General Segment program memory is not write-protected0 = General Segment program memory is write-protected

IESO FOSCSEL Two-speed Oscillator Start-Up Enable bit1 = Start up device with FRC, then automatically switch to the user-selected oscillator source when ready0 = Start up device with user-selected oscillator source

TEMP FOSCSEL Temperature Protection Enable bit1 = Temperature protection disabled0 = Temperature protection enabled

FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits111 = Internal Fast RC (FRC) oscillator110 = Reserved101 = LPRC oscillator100 = Secondary (LP) oscillator011 = Primary (XT, HS, EC) oscillator with PLL010 = Primary (XT, HS, EC) oscillator001 = Internal Fast RC (FRC) oscillator with PLL000 = Reserved

FCKSM<1:0> FOSC Clock Switching Mode bits1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

IOL1WAY FOSC Peripheral Pin Select Configuration1 = Allow only one reconfiguration0 = Allow multiple reconfigurations[Note: This bit is only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]

OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes)1 = OSC2 is clock output0 = OSC2 is general purpose digital I/O pin

POSCMD<1:0> FOSC Primary Oscillator Mode Select bits11 = Primary oscillator disabled10 = HS crystal oscillator mode01 = XT crystal oscillator mode00 = EC (external clock) mode

FWDTEN FWDT Watchdog Enable bit1 = Watchdog always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect)0 = Watchdog enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register)

WINDIS FWDT Watchdog Timer Window Enable bit1 = Watchdog Timer in Non-Window mode0 = Watchdog Timer in Window mode

WDTPRE FWDT Watchdog Timer Prescaler bit1 = 1:1280 = 1:32





WDTPOST FWDT Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384 . . .0001 = 1:20000 = 1:1

PWMPIN FPOR Motor Control PWM Module Pin mode1 = PWM module pins controlled by PORT register at device Reset (tri-stated)0 = PWM module pins controlled by PWM module at device Reset (configured as output pins)

HPOL FPOR Motor Control PWM High-side Polarity bit1 = PWM module high-side output pins have active-high output polarity0 = PWM module high-side output pins have active-low output polarity

LPOL FPOR Motor Control PWM Low-side Polarity bit1 = PWM module low-side output pins have active-high output polarity0 = PWM module low-side output pins have active-low output polarity

ALTI2C FPOR Alternate I2C™ pins1 = I2C mapped to SDA1/SCL1 pins0 = I2C mapped to ASDA1/SACL1 pins[Note: This bit is only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]

FPWRT<2:0> FPOR Power-on Reset Timer Value Select bits111 = PWRT = 128 ms110 = PWRT = 64 ms101 = PWRT = 32 ms100 = PWRT = 16 ms011 = PWRT = 8 ms010 = PWRT = 4 ms001 = PWRT = 2 ms000 = PWRT Disabled

BKBUG FICD Background Debug Enable bit1 = Device will reset in User mode0 = Device will reset in Debug mode

COE FICD Debugger/Emulator Enable bit1 = Device will reset in Operational mode0 = Device will reset in Clip-On Emulation mode

JTAGEN FICD JTAG Enable bit1 = JTAG enabled0 = JTAG disabled

ICS<1:0> FICD ICD Communication Channel Select bits11 = Communicate on PGC1/EMUC1 and PGD1/EMUD110 = Communicate on PGC2/EMUC2 and PGD2/EMUD201 = Communicate on PGC3/EMUC3 and PGD3/EMUD300 = Reserved, do not use

— All Unimplemented (read as ‘0’, write as ‘0’)





TABLE 3-4: dsPIC33F/PIC24H DEVICE CONFIGURATION REGISTER MAP

Note 1: On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX) and PIC24H devices, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).

2: These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as ‘0’).

3: In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices, these bits are reserved (read as ‘1’ and must be programmed as ‘1’).

3.6.2 PROGRAMMING METHODOLOGY

Configuration bits may be programmed a single byte ata time using the PROGC command. This commandspecifies the configuration data and Configurationregister address. When Configuration bits areprogrammed, any unimplemented bits must beprogrammed with a ‘0’ and any reserved bits must beprogrammed with a ‘1’.

Twelve PROGC commands are required to program allthe Configuration bits. A flowchart for Configuration bitprogramming is shown in Figure 3-5.

3.6.3 PROGRAMMING VERIFICATION

After the Configuration bits are programmed, thecontents of memory should be verified to ensure thatthe programming was successful. Verification requiresthe Configuration bits to be read back and comparedagainst the copy held in the programmer’s buffer. TheREADC command reads back the programmedConfiguration bits and verifies that the programmingwas successful.

Any unimplemented Configuration bits are read-onlyand read as ‘0’. The reserved bits are read-only andread as ‘1’.

3.6.4 CODEGUARD SECURITY CONFIGURATION BITS

The FBS, FSS and FGS Configuration registers arespecial Configuration registers that control the size andlevel of code protection for the Boot Segment, SecureSegment and General Segment, respectively. For eachsegment, two main forms of code protection areprovided. One form prevents code memory from beingwritten (write protection), while the other prevents codememory from being read (read protection).

BWRP, SWRP and GWRP bits control write protectionand BSS<2:0>, SSS<2:0> and GSS<1:0> bits controlsread protection. The Chip Erase ERASEB commandsets all the code protection bits to ‘1’, which allows thedevice to be programmed.

When write protection is enabled, any programmingoperation to code memory will fail. When read protec-tion is enabled, any read from code memory will causea ‘0x0’ to be read, regardless of the actual contents ofcode memory. Since the programming executivealways verifies what it programs, attempting to programcode memory with read protection enabled will alsoresult in failure.

It is imperative that all code protection bits are ‘1’ whilethe device is being programmed and verified. Only afterthe device is programmed and verified should any ofthe above bits be programmed to ‘0’.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0xF80000 FBS RBS<1:0>(3) — BSS<2:0> BWRP

0xF80002 FSS RSS<1:0>(3) — SSS<2:0>(3) SWRP(3)

0xF80004 FGS — GSS<1:0> GWRP

0xF80006 FOSCSEL IESO — TEMP — FNOSC<2:0>

0xF80008 FOSC FCKSM<1:0> IOL1WAY(2) — OSCIOFNC POSCMD<1:0>

0xF8000A FWDT FWDTEN WINDIS - WDTPRE WDTPOST<3:0>

0xF8000C FPOR PWMPIN(1) HPOL(1) LPOL(1) ALTI2C(2) — FPWRT<2:0>

0xF8000E FICD BKBUG COE JTAGEN — ICS<1:0>

0xF80010 FUID0 User Unit ID Byte 0




Note: If the General Code Segment Code-Protect bit (GCP) is programmed to ‘0’,code memory is code-protected andcan not be read. Code memory mustbe verified before enabling read protec-tion. See Section 3.6.4 “CodeGuardSecurity Configuration Bits” for moreinformation about code-protect Configura-tion bits.



In addition to code memory protection, a part of DataRAM can be configured to be accessible only by coderesident in the Boot Segment and/or Secure Segment.The sizes of these “reserved” sections are user-config-urable, using the RBS<1:0> and RSS<1:0> bits.

3.6.5 USER UNIT ID

The dsPIC33F/PIC24H devices provide four 8-bit Con-figuration registers (FUID0 through FUID3) for the userto store product-specific information, such as unit serialnumbers and other product manufacturing data.

FIGURE 3-5: CONFIGURATION BIT PROGRAMMING FLOW

3.7 Exiting Enhanced ICSP Mode

Exiting Program/Verify mode is done by removing VIH

from MCLR, as shown in Figure 3-6. The only require-ment for exit is that an interval P16 should elapsebetween the last clock and program signals on PGCand PGD before removing VIH.

FIGURE 3-6: EXITING ENHANCED ICSP™ MODE

Note: All bits in the FBS, FSS and FGS Configu-ration registers can only be programmedto a value of ‘0’. the ERASEB command isthe only way to reprogram code-protectbits from ON (‘0’) to OFF (‘1’).

Send PROGCCommand

ConfigAddress = 0xF80000

IsPROGC response

PASS?

No

Yes

No

FailureReport Error

Start

Finish

Yes

IsConfigAddress

0xF80018?

ConfigAddress =ConfigAddress + 2

MCLR

P16

PGD

PGD = Input

PGC

VDD

VIH

VIH

P17



4.0 THE PROGRAMMING EXECUTIVE

4.1 Programming Executive Communication

The programmer and programming executive have amaster-slave relationship, where the programmer isthe master programming device and the programmingexecutive is the slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the programming executive. In turn, theprogramming executive only sends one response tothe programmer after receiving and processing acommand. The programming executive command setis described in Section 4.2 “Programming ExecutiveCommands”. The response set is described inSection 4.3 “Programming Executive Responses”.

4.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The ICSP/Enhanced ICSP interface is a 2 wire SPIimplemented using the PGC and PGD pins. The PGCpin is used as a clock input pin and the clock sourcemust be provided by the programmer. The PGD pin isused for sending command data to and receivingresponse data from the programming executive. Allserial data is transmitted on the falling edge of PGCand latched on the rising edge of PGC. All data trans-missions are sent to the Most Significant bit (MSb) firstusing 16-bit mode (see Figure 4-1).

FIGURE 4-1: PROGRAMMING EXECUTIVE SERIAL TIMING

Since a 2 wire SPI is used, and data transmissions arebidirectional, a simple protocol is used to control thedirection of PGD. When the programmer completes acommand transmission, it releases the PGD line andallows the programming executive to drive this linehigh. The programming executive keeps the PGD linehigh to indicate that it is processing the command.

After the programming executive has processed thecommand, it brings PGD low for 15 μsec to indicate tothe programmer that the response is available to beclocked out. The programmer can begin to clock outthe response 23 μsec after PGD is brought low and itmust provide the necessary amount of clock pulses toreceive the entire response from the programmingexecutive.

After the entire response is clocked out, the program-mer should terminate the clock on PGC until it is timeto send another command to the programmingexecutive. This protocol is shown in Figure 4-2.

4.1.2 SPI RATE

In Enhanced ICSP mode, the dsPIC33F/PIC24H familydevices operate from the Fast Internal RC oscillator,which has a nominal frequency of 7.3728 MHz. Thisoscillator frequency yields an effective system clockfrequency of 1.8432 MHz. To ensure that the program-mer does not clock too fast, it is recommended that a 7.35 MHz clock be provided by the programmer.

4.1.3 TIME OUTS

The programming executive uses no Watchdog or timeout for transmitting responses to the programmer. If theprogrammer does not follow the flow controlmechanism using PGC as described in Section 4.1.1“Communication Interface and Protocol”, it ispossible that the programming executive will behaveunexpectedly while trying to send a response to theprogrammer. Since the programming executive has notime out, it is imperative that the programmer correctlyfollow the described communication protocol.

As a safety measure, the programmer should use thecommand time outs identified in Table 4-1. If thecommand time out expires, the programmer shouldreset the programming executive and startprogramming the device again.

PGC

PGD

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1B

P1A



FIGURE 4-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

4.2 Programming Executive Commands

The programming executive command set is shown inTable 4-1. This table contains the opcode, mnemonic,length, time out and description for each command.Functional details on each command are provided inthe command descriptions (Section 4.2.4 “CommandDescriptions”).

4.2.1 COMMAND FORMAT

All programming executive commands have a generalformat consisting of a 16-bit header and any requireddata for the command (see Figure 4-3). The 16-bitheader consists of a 4-bit opcode field, which is used toidentify the command, followed by a 12-bit commandlength field.

FIGURE 4-3: COMMAND FORMAT

The command opcode must match one of those in thecommand set. Any command that is received whichdoes not match the list in Table 4-1 will return a “NACK”response (see Section 5.3.1.1 “Opcode Field”).

The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The program-ming executive uses the command length field todetermine the number of words to read from the SPIport. If the value of this field is incorrect, the commandwill not be properly received by the programmingexecutive.

4.2.2 PACKED DATA FORMAT

When 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format shown in Figure 4-4. Thisformat minimizes traffic over the SPI and provides theprogramming executive with data that is properlyaligned for performing table write operations.

FIGURE 4-4: PACKED INSTRUCTION WORD FORMAT

4.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING

The programming executive will “NACK” allunsupported commands. Additionally, due to thememory constraints of the programming executive, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the programming executivewith valid command arguments or the programmingoperation may fail. Additional information on errorhandling is provided in Section 5.3.1.3 “QE_CodeField”.

1 2 15 16 1 2 15 16

PGC

PGD

PGC = Input PGC = Input (Idle)

Host TransmitsLast Command Word

PGD = Input PGD = Output

P8

1 2 15 16

MSB X X X LSB MSB X X X LSB MSB X X X LSB1 0

P9b

PGC = InputPGD = Output

P9a

Programming ExecutiveProcesses Command Host Clocks Out Response

8ns23 µs

15 12 11 0

Opcode Length

Command Data First Word (if required)

•

•

Command Data Last Word (if required)

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 can not be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word



TABLE 4-1: PROGRAMMING EXECUTIVE COMMAND SET

4.2.4 COMMAND DESCRIPTIONS

All commands supported by the programming executiveare described in Section 5.2.5 “SCHECK Command”through Section 4.2.12 “QVER Command”.

4.2.5 SCHECK COMMAND

The SCHECK command instructs the programmingexecutive to do nothing but generate a response. Thiscommand is used as a “Sanity Check” to verify that theprogramming executive is operational.

Expected Response (2 words):0x10000x0002

Opcode MnemonicLength

(16-bit words)Time Out Description

0x0 SCHECK 1 1 msec Sanity check.

0x1 READC 3 1 msec Read an 8-bit word from the specified Configuration register or Device ID register.

0x2 READP 4 1 msec/row Read ‘N’ 24-bit instruction words of code memory starting from the specified address.

0x3 RESERVED N/A N/A This command is reserved. It will return a NACK.

0x4 PROGC 4 5 msec Write an 8-bit word to the specified Configuration register.

0x5 PROGP 99 5 msec Program one row of code memory at the specified address, then verify.

0x6 PROGW 5 5 msec Program one instruction word of code memory at the specified address, then verify.




0xA QBLANK 2 TBD Query if the code memory is blank.

0xB QVER 1 1 msec Query the programming executive software version.

0xC RESERVED N/A N/A This command is reserved. It will return a NACK.

0xD RESERVED N/A N/A This command is reserved. It will return a NACK.

Legend: TBD = To Be Determined

Note: One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.

15 12 11 0

Opcode Length

Field Description

Opcode 0x0

Length 0x1

Note: This instruction is not required forprogramming, but is provided fordevelopment purposes only.



4.2.6 READC COMMAND

The READC command instructs the programming exec-utive to read N Configuration registers or Device IDregisters, starting from the 24-bit address specified byAddr_MSB and Addr_LS. This command can only beused to read 8-bit or 16-bit data.

When this command is used to read Configurationregisters, the upper byte in every data word returned bythe programming executive is 0x00 and the lower bytecontains the Configuration register value.

Expected Response (4 + 3 * (N – 1)/2 words for N odd):0x11002 + NConfiguration register or Device ID Register 1... Configuration register or Device ID Register N

4.2.7 READP COMMAND

The READP command instructs the programming exec-utive to read N 24-bit words of code memory, startingfrom the 24-bit address specified by Addr_MSB andAddr_LS. This command can only be used to read 24-bit data. All data returned in the response to this com-mand uses the packed data format described inSection 4.2.2 “Packed Data Format”.

Expected Response (2 + 3 * N/2 words for N even):0x12002 + 3 * N/2Least significant program memory word 1... Least significant data word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):0x12004 + 3 * (N – 1)/2Least significant program memory word 1... MSB of program memory word N (zero padded)

15 12 11 8 7 0

Opcode Length

N Addr_MSB

Addr_LS

Field Description

Opcode 0x1

Length 0x3

N Number of 8-bit Configuration registers or Device ID registers to read (max of 256)

Addr_MSB MSB of 24-bit source address

Addr_LS Least Significant 16 bits of 24-bit source address

Note: Reading unimplemented memory willcause the programming executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.

15 12 11 8 7 0

Opcode Length

N

Reserved Addr_MSB

Addr_LS

Field Description

Opcode 0x2

Length 0x4

N Number of 24-bit instructions to read (max of 32768)

Reserved 0x0

Addr_MSB MSB of 24-bit source address

Addr_LS Least Significant 16 bits of 24-bit source address

Note: Reading unimplemented memory willcause the programming executive toreset. Please ensure that only memorylocations present on a particular deviceare accessed.



4.2.8 PROGC COMMAND

The PROGC command instructs the programming exec-utive to program a single Configuration register, locatedat the specified memory address.

After the specified data word has been programmed tocode memory, the programming executive verifies theprogrammed data against the data in the command.


4.2.9 PROGP COMMAND

The PROGP command instructs the programming exec-utive to program one row of code memory(64 instruction words) to the specified memoryaddress. Programming begins with the row addressspecified in the command. The destination addressshould be a multiple of 0x80.

The data to program to memory, located in commandwords D_1 through D_96, must be arranged using thepacked instruction word format shown in Figure 4-4.

After all data has been programmed to code memory,the programming executive verifies the programmeddata against the data in the command.


15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

Data

Field Description

Opcode 0x4

Length 0x4

Reserved 0x0

Addr_MSB MSB of 24-bit destination address

Addr_LS Least Significant 16 bits of 24-bit destination address

Data 8-bit data word

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

D_1

D_2

...

D_N

Field Description

Opcode 0x5

Length 0x63

Reserved 0x0



D_1 16-bit data word 1


... 16-bit data word 3 through 95


Note: Refer to Table 2-2 for code memory sizeinformation.



4.2.10 PROGW COMMAND

The PROGW command instructs the programming exec-utive to program one word of code memory (3 bytes) tothe specified memory address.

After the word has been programmed to code memory,the programming executive verifies the programmeddata against the data in the command.


4.2.11 QBLANK COMMAND

The QBLANK command queries the programming exec-utive to determine if the contents of code memory areblank (contains all ‘1’s). The size of code memory tocheck must be specified in the command.

The Blank Check for code memory begins at 0x0 andadvances toward larger addresses for the specifiednumber of instruction words.

QBLANK returns a QE_Code of 0xF0 if the specifiedcode memory and code-protect bits are blank;otherwise, QBLANK returns a QE_Code of 0x0F.

Expected Response (2 words for blank device):0x1AF00x0002

Expected Response (2 words for non-blank device):0x1A0F0x0002

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

Data_LS

Reserved Data_MSB

Field Description

Opcode 0x6

Length 0x5

Reserved 0x0



Data_MSB MSB of 24-bit data

Data_LS Least Significant 16 bits of 24-bit data

15 12 11 0

Opcode Length

PSize

Field Description

Opcode 0xA

Length 0x2

PSize Length of program memory to check(in 24-bit words) +1, up to a max of 49152

Note: The QBLANK command does not checkthe system operation Configuration bitssince these bits are not set to ‘1’ when aChip Erase is performed.



4.2.12 QVER COMMAND

The QVER command queries the version of theprogramming executive software stored in testmemory. The “version.revision” information is returnedin the response’s QE_Code using a single byte with thefollowing format: main version in upper nibble andrevision in the lower nibble (i.e., 0x23 meansversion 2.3 of programming executive software).

Expected Response (2 words):0x1BMN (where “MN” stands for version M.N)0x0002

4.3 Programming Executive Responses

The programming executive sends a response to theprogrammer for each command that it receives. Theresponse indicates if the command was processedcorrectly. It includes any required response data orerror data.

The programming executive response set is shown inTable 4-2. This table contains the opcode, mnemonicand description for each response. The response formatis described in Section 4.3.1 “Response Format”.

TABLE 4-2: PROGRAMMING EXECUTIVE RESPONSE OPCODES

4.3.1 RESPONSE FORMAT

All programming executive responses have a generalformat consisting of a two-word header and anyrequired data for the command.

4.3.1.1 Opcode Field

The opcode is a 4-bit field in the first word of theresponse. The opcode indicates how the commandwas processed (see Table 4-2). If the command wasprocessed successfully, the response opcode is PASS.If there was an error in processing the command, theresponse opcode is FAIL and the QE_Code indicatesthe reason for the failure. If the command sent tothe programming executive is not identified, theprogramming executive returns a NACK response.

4.3.1.2 Last_Cmd Field

The Last_Cmd is a 4-bit field in the first word ofthe response and indicates the command that theprogramming executive processed. Since the program-ming executive can only process one command at atime, this field is technically not required. However, itcan be used to verify that the programming executivecorrectly received the command that the programmertransmitted.

15 12 11 0

Opcode Length

Field Description

Opcode 0xB

Length 0x1

Opcode Mnemonic Description

0x1 PASS Command successfully processed.

0x2 FAIL Command unsuccessfully processed.

0x3 NACK Command not known.

Field Description

Opcode Response opcode.

Last_Cmd Programmer command that generated the response.

QE_Code Query code or error code.

Length Response length in 16-bit words (includes 2 header words).

D_1 First 16-bit data word (if applicable).

D_N Last 16-bit data word (if applicable).

15 12 11 8 7 0

Opcode Last_Cmd QE_Code

Length

D_1 (if applicable)

...

D_N (if applicable)



4.3.1.3 QE_Code Field

The QE_Code is a byte in the first word of theresponse. This byte is used to return data for querycommands and error codes for all other commands.

When the programming executive processes one of thetwo query commands (QBLANK or QVER), the returnedopcode is always PASS and the QE_Code holds thequery response data. The format of the QE_Code forboth queries is shown in Table 4-3.

TABLE 4-3: QE_Code FOR QUERIES

When the programming executive processes anycommand other than a Query, the QE_Code repre-sents an error code. Supported error codes are shownin Table 4-4. If a command is successfully processed,the returned QE_Code is set to 0x0, which indicatesthat there was no error in the command processing. Ifthe verify of the programming for the PROGP or PROGCcommand fails, the QE_Code is set to 0x1. For all otherprogramming executive errors, the QE_Code is 0x2.

TABLE 4-4: QE_Code FOR NON-QUERY COMMANDS

4.3.1.4 Response Length

The response length indicates the length of theprogramming executive’s response in 16-bit words.This field includes the 2 words of the response header.

With the exception of the response for the READP command, the length of each response is only 2 words.

The response to the READP command uses the packedinstruction word format described in Section 4.2.2“Packed Data Format”. When reading an odd numberof program memory words (N odd), the response to theREADP command is (3 * (N + 1) / 2 + 2) words. Whenreading an even number of program memory words(N even), the response to the READP command is (3 *N / 2 + 2) words.

Query QE_Code

QBLANK 0x0F = Code memory is NOT blank0xF0 = Code memory is blank

QVER 0xMN, where programming executive software version = M.N(i.e., 0x32 means software version 3.2).

QE_Code Description

0x0 No error.

0x1 Verify failed.

0x2 Other error.



5.0 DEVICE PROGRAMMING – ICSP

ICSP mode is a special programming protocol thatallows you to read and write to dsPIC33F/PIC24Hdevice family memory. The ICSP mode is the mostdirect method used to program the device; note, how-ever, that Enhanced ICSP is faster. ICSP mode alsohas the ability to read the contents of executive mem-ory to determine if the programming executive ispresent. This capability is accomplished by applyingcontrol codes and instructions serially to the deviceusing pins PGC and PGD.

In ICSP mode, the system clock is taken from the PGCpin, regardless of the device’s oscillator Configurationbits. All instructions are shifted serially into an internalbuffer, then loaded into the instruction register andexecuted. No program fetching occurs from internalmemory. Instructions are fed in 24 bits at a time. PGDis used to shift data in, and PGC is used as both theserial shift clock and the CPU execution clock.

5.1 Overview of the Programming Process

Figure 5-1 shows the high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Bulk Erase the device. Next, the codememory is programmed, followed by the device Con-figuration registers. Code memory (including theConfiguration registers) is then verified to ensure thatprogramming was successful. Then, program thecode-protect Configuration bits, if required.

FIGURE 5-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

5.2 ICSP Operation

Upon entry into ICSP mode, the CPU is Idle. Executionof the CPU is governed by an internal state machine. A4-bit control code is clocked in using PGC and PGD andthis control code is used to command the CPU (seeTable 5-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device via the VISI register.

TABLE 5-1: CPU CONTROL CODES IN ICSP™ MODE

Note: During ICSP operation, the operatingfrequency of PGC must not exceed5 MHz.

4-Bit Control Code

Mnemonic Description

0000b SIX Shift in 24-bit instruction and execute.

0001b REGOUT Shift out the VISIregister.

0010b-1111b N/A Reserved.

Start

Perform BulkErase

Program Memory

Verify Program

Done

Enter ICSP™

Program Configuration Bits

Verify Configuration Bits

Exit ICSP



5.2.1 SIX SERIAL INSTRUCTION EXECUTION

The SIX control code allows execution of dsPIC33F/PIC24H Programming Specification assembly instruc-tions. When the SIX code is received, the CPU is sus-pended for 24 clock cycles, as the instruction is thenclocked into the internal buffer. Once the instruction isshifted in, the state machine allows it to be executed overthe next four clock cycles. While the received instructionis executed, the state machine simultaneously shifts inthe next 4-bit command (see Figure 5-2).

5.2.2 REGOUT SERIAL INSTRUCTION EXECUTION

The REGOUT control code allows for data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register out of the deviceover the PGD pin. After the REGOUT control code isreceived, the CPU is held Idle for 8 cycles. After theseeight cycles, an additional 16 cycles are required to clockthe data out (see Figure 5-3).

The REGOUT code is unique because the PGD pin isan input when the control code is transmitted to thedevice. However, after the control code is processed,the PGD pin becomes an output as the VISI register isshifted out.

FIGURE 5-2: SIX SERIAL EXECUTION

FIGURE 5-3: REGOUT SERIAL EXECUTION

Note 1: Coming out of Reset, the first 4-bit controlcode is always forced to SIX and a forcedNOP instruction is executed by the CPU.Five additional PGC clocks are neededon start-up, thereby resulting in a 9-bitSIX command instead of the normal 4-bitSIX command. After the forced SIX isclocked in, ICSP operation resumes asnormal (the next 24 clock cycles load thefirst instruction word to the CPU).

2: TBLRDH, TBLRDL, TBLWTH and TBLWTLinstructions must be followed by a NOPinstruction.

Note: Data is transmitted on the falling edge andlatched on the rising edge of PGC. For alldata transmissions, the Least Significantbit (LSb) is transmitted first.

P4

2 3 1 2 3 23 24 1 2 3 4

P1

PGC

P4a

PGD

24-Bit Instruction Fetch Execute 24-Bit Instruction,Execute PC – 1,

1 4

0 0 0 0

Fetch SIX Control Code Fetch Next Control Code

4 5 6 7 8 18 19 20 21 2217

LSB X X X X X X X X X X X X X X MSB

PGD = Input

P2

P3

P1B

P1A

5 6 7

0 0 0 00 0 0

Only for Program Memory Entry

8 9

0 0

1 2 3 4 1 2 7 8

PGC

P4

PGD

PGD = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0>

P5

PGD = Output

1 2 3 1 2 3 4

P4a

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGD = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0



5.3 Entering ICSP Mode

As shown in Figure 5-4, entering ICSP Program/Verifymode requires three steps:

1. MCLR is briefly driven high then low.2. A 32-bit key sequence is clocked into PGD.

3. MCLR is then driven high within a specifiedperiod of time and held.

The programming voltage applied to MCLR is VIH,which is essentially VDD in the case of dsPIC33F/PIC24H devices. There is no minimum time require-ment for holding at VIH. After VIH is removed, an inter-val of at least P18 must elapse before presenting thekey sequence on PGD.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 0x4D434851 in hexa-decimal). The device will enter Program/Verify mode onlyif the sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.

Once the key sequence is complete, VIH must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An interval ofat least time P19 and P7 must elapse before presentingdata on PGD. Signals appearing on PGD before P7has elapsed will not be interpreted as valid.

On successful entry, the program memory can beaccessed and programmed in serial fashion. Whilein ICSP mode, all unused I/Os are placed in thehigh-impedance state.

FIGURE 5-4: ENTERING ICSP™ MODE

5.4 Flash Memory Programming in ICSP Mode

5.4.1 PROGRAMMING OPERATIONS

Flash memory write and erase operations are controlledby the NVMCON register. Programming is performed bysetting NVMCON to select the type of erase operation(Table 5-2) or write operation (Table 5-3) and initiatingthe programming by setting the WR control bit (NVMCON<15>).

In ICSP mode, all programming operations are self-timed. There is an internal delay between the user set-ting the WR control bit and the automatic clearing of theWR control bit when the programming operation iscomplete. Please refer to Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements” forinformation about the delays associated with variousprogramming operations.

TABLE 5-2: NVMCON ERASE OPERATIONS

MCLR

PGD

PGC

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 0x4D434851

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 1

P7VIH VIH

NVMCONValue

Erase Operation

0x404F Erase all code memory, executive memory and Configuration registers (does not erase Unit ID or Device ID registers).

0x404D Erase General Segment and FGS Configuration register.

0x404C Erase Secure Segment and FSS Configuration register. This operation will also erase the General Segment and FGS Configuration register.

0x4042 Erase a page of code memory or executive memory.

0x4040 Erase a Configuration register byte.



TABLE 5-3: NVMCON WRITE OPERATIONS

5.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

The WR bit (NVMCON<15>) is used to start an erase orwrite cycle. Setting the WR bit initiates the programmingcycle.

All erase and write cycles are self-timed. The WR bitshould be polled to determine if the erase or write cyclehas been completed. Starting a programming cycle isperformed as follows:

BSET NVMCON, #WR

5.5 Erasing Program Memory

The procedure for erasing program memory (all of codememory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 0x404Fand then executing the programming cycle. For seg-ment erase operations, the NVMCON value should bemodified suitably, according to Table 5-2.

Figure 5-5 shows the ICSP programming process forBulk Erasing program memory. This process includesthe ICSP command code, which must be transmitted(for each instruction) Least Significant bit first, using thePGC and PGD pins (see Figure 5-2).

FIGURE 5-5: BULK ERASE FLOW

If a Segment Erase operation is required, Step 3 mustbe modified with the appropriate NVMCON value asper Table 5-2.

The ability to individually erase various segments is acritical component of the CodeGuard™ Security fea-tures on dsPIC33F/PIC24H devices. An individualcode segment may be erased without affecting othersegments. In addition, the Configuration register corre-sponding to the erased code segment also getserased. For example, the user might want to erase thecode in the General Segment without erasing a BootLoader located in Boot Segment.

The Secure Segment Erase command is used to erasethe Secure Segment and the FSS Configuration regis-ter. The General Segment Erase command is used toerase the General Segment and the FGS Configurationregister. This command is only effective if a BootSegment or Secure Segment has been enabled.

Before performing any segment erase operation, theprogrammer must first determine if the dsPIC33F/PIC24H device has defined a Boot Segment or SecureSegment, and ensure that a segment does not getoverwritten by operations on any other segment. Also,a Bulk Erase should not be performed if a Boot Segment or Secure Segment has been defined.

The BSS bit field in the FBS configuration register canbe read to determine whether a Boot Segment hasbeen defined. If a Boot Segment has already beendefined (and probably already been programmed), theuser must be warned about this fact. Similarly, the SSSbit field in the FSS configuration register can be read todetermine whether a Secure Segment has beendefined. If a Secure Segment has already been defined(and probably already been programmed), the usermust be warned about this fact.

A Bulk Erase operation is the recommended mecha-nism to allow a user to overwrite the Boot Segment (ifone chooses to do so).

In general, the segments and CodeGuard Security-related configuration registers should be programmedin the following order:

• FBS and Boot Segment

• FSS and Secure Segment• FGS and General Segment

NVMCONValue

Write Operation

0x4001 Program 1 row (64 instruction words) of code memory or executive memory.

0x4000 Write a Configuration register byte.

0x4003 Program a code memory word.

Note: Program memory must be erased beforewriting any data to program memory.

Start

Done

Set the WR bit to Initiate Erase

Write 0x404F to NVMCON SFR

Delay P11 + P10 Time

Note 1: The Boot Segment and FBS Configura-tion register can only be erased using aBulk Erase.

2: A Secure Segment Erase operation alsoerases the General Segment and FGSConfiguration register. This is true even ifSecure Segment is present on a devicebut not enabled.



TABLE 5-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY

5.6 Writing Code Memory

The procedure for writing code memory is similar to theprocedure for writing the Configuration registers,except that 64 instruction words are programmed at atime. To facilitate this operation, working registers,W0:W5, are used as temporary holding registers for thedata to be programmed.

Table 5-5 shows the ICSP programming details, includ-ing the serial pattern with the ICSP command code,which must be transmitted Least Significant bit firstusing the PGC and PGD pins (see Figure 5-2). In Step1, the Reset vector is exited. In Step 2, the NVMCONregister is initialized for programming of code memory.In Step 3, the 24-bit starting destination address forprogramming is loaded into the TBLPAG register andW7 register. The upper byte of the starting destinationaddress is stored in TBLPAG and the lower 16 bits ofthe destination address are stored in W7.

To minimize the programming time, the same packedinstruction format that the programming executive usesis utilized (Figure 4-4). In Step 4, four packed instruc-tion words are stored in working registers, W0:W5,using the MOV instruction and the read pointer, W6, isinitialized. The contents of W0:W5 holding the packedinstruction word data are shown in Figure 5-6. In Step5, eight TBLWT instructions are used to copy the datafrom W0:W5 to the write latches of code memory. Since

code memory is programmed 64 instruction words at atime, Steps 4 and 5 are repeated 16 times to load all thewrite latches (Step 6).

After the write latches are loaded, programming isinitiated by writing to the NVMCON register in Steps 7and 8. In Step 9, the internal PC is reset to 0x200. This isa precautionary measure to prevent the PC from incre-menting into unimplemented memory when largedevices are being programmed. Lastly, in Step 10, Steps3-9 are repeated until all of code memory is programmed.

FIGURE 5-6: PACKED INSTRUCTION WORDS IN W0:W5

Command(Binary)

Data(Hex)

Description

Step 1: Exit the Reset vector.

0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Set the NVMCON to erase all program memory.

00000000

2404FA883B0A

MOV #0x404F, W10MOV W10, NVMCON

Step 3: Initiate the erase cycle.

000000000000

A8E761000000000000

BSET NVMCON, #WR NOPNOP

Step 4: Wait for Bulk Erase operation to complete and make sure WR bit is clear.

-

0000000000000001

-

807600887840000000<VISI>

Externally time ‘P11’ msec (see Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”) to allow suffi-cient time for the Bulk Erase operation to complete.

MOV NVMCON, W0MOV W0, VISINOPClock out contents of VISI register. Repeat until the WR bit is clear.

15 8 7 0

W0 LSW0W1 MSB1 MSB0W2 LSW1W3 LSW2W4 MSB3 MSB2W5 LSW3



TABLE 5-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORYCommand

(Binary)Data(Hex) Description


0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Set the NVMCON to program 64 instruction words.

00000000

24001A883B0A

MOV #0x4001, W10MOV W10, NVMCON

Step 3: Initialize the write pointer (W7) for TBLWT instruction.

000000000000

200xx08801902xxxx7

MOV #<DestinationAddress23:16>, W0MOV W0, TBLPAGMOV #<DestinationAddress15:0>, W7

Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.

000000000000000000000000

2xxxx02xxxx12xxxx22xxxx32xxxx42xxxx5

MOV #<LSW0>, W0MOV #<MSB1:MSB0>, W1MOV #<LSW1>, W2MOV #<LSW2>, W3MOV #<MSB3:MSB2>, W4MOV #<LSW3>, W5

Step 5: Set the read pointer (W6) and load the (next set of) write latches.

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

CLR W6NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B[W6++], [W7++] NOPNOPTBLWTH.B[W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOP NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B[W6++], [W7++] NOP NOPTBLWTH.B[W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOPNOP

Step 6: Repeat steps 4-5 sixteen times to load the write latches for 64 instructions.

Step 7: Initiate the write cycle.

000000000000

A8E761000000000000

BSET NVMCON, #WR NOPNOP

Step 8: Wait for Row Program operation to complete and make sure WR bit is clear.



FIGURE 5-7: PROGRAM CODE MEMORY FLOW

-

0000000000000001

-

807600887840000000<VISI>

Externally time ‘P13’ msec (see Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”) to allow suffi-cient time for the Row Program operation to complete.


Step 9: Reset device internal PC.

00000000

040200000000

GOTO 0x200 NOP

Step 10: Repeat steps 3-9 until all code memory is programmed.

TABLE 5-5: SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

Start Write Sequence

Alllocations

done?

No

Done

Start

Yes

Load 2 Bytesto Write

Buffer at <Addr>

Allbytes

written?

No

Yes

and Poll for WR bitto be cleared

N = 1LoopCount = 0

ConfigureDevice for

Writes

N = 1LoopCount =

LoopCount + 1

N = N + 1



5.7 Writing Configuration Memory

The 8-bit Configuration registers are programmable, oneregister at a time. The default programming values rec-ommended for the Configuration registers are shown inTable 5-6 and Table 5-7. The recommended defaultFOSCSEL value is 0x07, which selects the FRC clockoscillator setting.

The FBS, FSS and FGS Configuration registers arespecial since they enable code protection for thedevice. For security purposes, once any bit in theseregisters is programmed to ‘0’ (to enable code protec-tion), it can only be set back to ‘1’ by performing a BulkErase as described in Section 5.5 “Erasing ProgramMemory”. Programming any of these bits from a ‘0’ to‘1’ is not possible, but they may be programmed from a‘1’ to a ‘0’ to enable code protection.

Table 5-8 shows the ICSP programming details for clear-ing the Configuration registers. In Step 1, the Reset vec-tor is exited. In Step 2, the write pointer (W7) is loadedwith 0x0000, which is the original destination address (inTBLPAG, 0xF8 of program memory). In Step 3, theNVMCON is set to program one Configuration register.In Step 4, the TBLPAG register is initialized to 0xF8 forwriting to the Configuration registers. In Step 5, the valueto write to each Configuration register is loaded to W0.In Step 6, the Configuration register data is written to thewrite latch using the TBLWTL instruction. In Steps 7 and8, the programming cycle is initiated. In Step 9, the inter-nal PC is set to 0x200 as a safety measure to prevent thePC from incrementing into unimplemented memory.Lastly, Steps 4-9 are repeated until all twelveConfiguration registers are written.

TABLE 5-6: DEFAULT CONFIGURATION REGISTER VALUES FOR dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 AND PIC24HJ12GP201/202

TABLE 5-7: DEFAULT CONFIGURATION REGISTER VALUES FOR ALL OTHER DEVICES

Address Name Default Value

0xF80000 FBS 0xCF

0xF80002 FSS 0xFF

0xF80004 FGS 0x07

0xF80006 FOSCSEL 0xA7

0xF80008 FOSC 0xE7

0xF8000A FWDT 0xDF

0xF8000C FPOR 0xF7

0xF8000E FICD 0xE3

0xF80010 FUID0 0xFF

0xF80012 FUID1 0xFF

0xF80014 FUID2 0xFF

0xF80016 FUID3 0xFF

Address Name Default Value

0xF80000 FBS 0xCF

0xF80002 FSS 0xCF

0xF80004 FGS 0x07

0xF80006 FOSCSEL 0xA7

0xF80008 FOSC 0xC7

0xF8000A FWDT 0xDF

0xF8000C FPOR 0xE7

0xF8000E FICD 0xE3

0xF80010 FUID0 0xFF

0xF80012 FUID1 0xFF

0xF80014 FUID2 0xFF

0xF80016 FUID3 0xFF



TABLE 5-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS

Command(Binary)

Data(Hex)

Description


0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Initialize the write pointer (W7) for the TBLWT instruction.

0000 200007 MOV #0x0000, W7

Step 3: Set the NVMCON register to program one Configuration register.

00000000

24000A883B0A

MOV #0x4000, W10MOV W10, NVMCON

Step 4: Initialize the TBLPAG register.

00000000

200F80880190

MOV #0xF8, W0MOV W0, TBLPAG

Step 5: Load the Configuration register data to W6.

0000 2xxxx0 MOV #<CONFIG_VALUE>, W0

Step 6: Write the Configuration register data to the write latch and increment the write pointer.

000000000000

BB1B96000000000000

TBLWTL W0, [W7++]NOPNOP

Step 7: Initiate the write cycle.

000000000000

A8E761000000000000

BSET NVMCON, #WRNOPNOP

Step 8: Wait for the Configuration Register Write operation to complete and make sure WR bit is clear.

-

0000000000000001

-

807600887840000000<VISI>

Externally time ‘P20’ msec (see Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”) to allow suffi-cient time for the Configuration Register Write operation to complete.MOV, NVMCON, W0MOV W0, VISINOPClock out contents of VISI register. Repeat until the WR bit is clear.


00000000

040200000000

GOTO 0x200NOP

Step 10: Repeat steps 5-9 until all twelve Configuration registers are written.



5.8 Reading Code Memory

Reading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.

Table 5-9 shows the ICSP programming details forreading code memory. In Step 1, the Reset vector isexited. In Step 2, the 24-bit starting source address forreading is loaded into the TBLPAG register and W6register. The upper byte of the starting source addressis stored in TBLPAG and the lower 16 bits of the sourceaddress are stored in W6.

To minimize the reading time, the packed instructionword format that was utilized for writing is also used forreading (see Figure 5-6). In Step 3, the write pointer,W7, is initialized. In Step 4, two instruction words areread from code memory and clocked out of the device,through the VISI register, using the REGOUT command.Step 4 is repeated until the desired amount of codememory is read.

TABLE 5-9: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY

Command(Binary)

Data(Hex)

Description

Step 1: Exit Reset vector.

0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRD instruction.

000000000000

200xx08801902xxxx6

MOV #<SourceAddress23:16>, W0MOV W0, TBLPAGMOV #<SourceAddress15:0>, W6

Step 3: Initialize the write pointer (W7) to point to the VISI register.

00000000

207847000000

MOV #VISI, W7 NOP

Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command.

00000000000000010000000000000001

BA1B96000000000000<VISI>BA9BB6000000000000<VISI>

TBLRDL [W6], [W7] NOPNOPClock out contents of VISI registerTBLRDH [W6++], [W7] NOPNOPClock out contents of VISI register

Step 5: Repeat step 4 until all desired code memory is read.


00000000

040200000000

GOTO 0x200 NOP



5.9 Reading Configuration Memory

The procedure for reading configuration memory issimilar to the procedure for reading code memory,except that 16-bit data words are read (with the upperbyte read being all ‘0’s) instead of 24-bit words. Sincethere are twelve Configuration registers, they are readone register at a time.

Table 5-10 shows the ICSP programming details forreading all of configuration memory. Note that theTBLPAG register is hard coded to 0xF8 (the upper byteaddress of configuration memory) and the read pointer,W6, is initialized to 0x0000.

TABLE 5-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY

Command(Binary)

Data(Hex)

Description


0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Initialize TBLPAG, the read pointer (W6) and the write pointer (W7) for TBLRD instruction.

00000000000000000000

200F80880190EB0300207847000000

MOV #0xF8, W0MOV W0, TBLPAGCLR W6MOV #VISI, W7NOP

Step 3: Read the Configuration register and write it to the VISI register (located at 0x784) and clock out the VISI register using the REGOUT command.

0000000000000001

BA0BB6000000000000<VISI>

TBLRDL [W6++], [W7] NOP NOPClock out contents of VISI register

Step 4: Repeat step 3 twelve times to read all the Configuration registers.


00000000

040200000000

GOTO 0x200 NOP



5.10 Verify Code Memory and Configuration Word

The verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration registers areverified with the rest of the code.

The verify process is shown in the flowchart inFigure 5-8. Memory reads occur a single byte at a time,so two bytes must be read to compare against the wordin the programmer’s buffer. Refer to Section 5.8“Reading Code Memory” for implementation detailsof reading code memory.

FIGURE 5-8: VERIFY CODE MEMORY FLOW

5.11 Reading the Application ID Word

The Application ID Word is stored at address 0x8007F0in executive code memory. To read this memorylocation, you must use the SIX control code to movethis program memory location to the VISI register.Then, the REGOUT control code must be used to clockthe contents of the VISI register out of the device. Thecorresponding control and instruction codes that mustbe serially transmitted to the device to perform thisoperation are shown in Table 5-11.

After the programmer has clocked out the ApplicationID Word, it must be inspected. If the application ID hasthe value 0xBB, the programming executive is residentin memory and the device can be programmed usingthe mechanism described in Section 3.0 “DeviceProgramming – Enhanced ICSP”. However, if theapplication ID has any other value, the programmingexecutive is not resident in memory; it must be loadedto memory before the device can be programmed. Theprocedure for loading the programming executive tomemory is described in Section 6.0 “Programmingthe Programming Executive to Memory”.

5.12 Exiting ICSP Mode

Exiting Program/Verify mode is done by removing VIH

from MCLR, as shown in Figure 5-9. The only require-ment for exit is that an interval P16 should elapsebetween the last clock and program signals on PGCand PGD before removing VIH.

FIGURE 5-9: EXITING ICSP™ MODE

Note: Because the Configuration registersinclude the device code protection bit,code memory should be verified immedi-ately after writing if code protection isenabled. This is because the device willnot be readable or verifiable if a deviceReset occurs after the code-protect bit inthe FGS Configuration register has beencleared.

Read Low Byte

Read High Byte

DoesWord = Expect

Data?

Failure,ReportError

Allcode memory

verified?

No

Yes

No

Set TBLPTR = 0

Start

Yes

Done

with Post-Increment

with Post-Increment

MCLR

P16

PGD

PGD = Input

PGC

VDD

VIH

VIH

P17



TABLE 5-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD

Command(Binary)

Data(Hex)

Description


0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP


00000000000000000000000000000000

200800880190205FE0207841000000BA0890000000000000

MOV #0x80, W0 MOV W0, TBLPAGMOV #0x5BE, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOP

Step 3: Output the VISI register using the REGOUT command.

0001 <VISI> Clock out contents of the VISI register



6.0 PROGRAMMING THE PROGRAMMING EXECUTIVE TO MEMORY

6.1 Overview

If it is determined that the programming executive is notpresent in executive memory (as described inSection 3.2 “Confirming the Presence of the Pro-gramming Executive”), it must be programmed intoexecutive memory using ICSP, as described inSection 5.0 “Device Programming – ICSP”.

Storing the programming executive to executivememory is similar to normal programming of codememory. Namely, the executive memory must first beerased, and then the programming executive must beprogrammed 64 words at a time. This control flow issummarized in Table 6-1.

TABLE 6-1: PROGRAMMING THE PROGRAMMING EXECUTIVE

Command(Binary)

Data(Hex)

Description

Step 1: Exit Reset vector and erase executive memory.

0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP

Step 2: Initialize the NVMCON to erase a page of executive memory.

00000000

24072A883B0A

MOV #0x4042, W10 MOV W10, NVMCON

Step 3: Initiate the erase cycle, wait for erase to complete and make sure WR bit is clear.

000000000000-

0000000000000001

A8E761000000000000

-

807600887840000000<VISI>

BSET NVMCON, #15 NOPNOPExternally time ‘P12’ msec (see Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”) to allow suffi-cient time for the Page Erase operation to complete.


Step 4: Repeat Step 3 four times to erase all four pages of executive memory.

Step 5: Initialize the NVMCON to program 64 instruction words.

00000000

24001A883B0A

MOV #0x4001, W10 MOV W10, NVMCON

Step 6: Initialize TBLPAG and the write pointer (W7).

0000000000000000

200800880190EB0380000000

MOV #0x80, W0 MOV W0, TBLPAG CLR W7 NOP



Step 7: Load W0:W5 with the next 4 words of packed programming executive code and initialize W6 for programming. Programming starts from the base of executive memory (0x800000) using W6 as a read pointer and W7 as a write pointer.

000000000000000000000000

2<LSW0>02<MSB1:MSB0>12<LSW1>22<LSW2>32<MSB3:MSB2>42<LSW3>5

MOV #<LSW0>, W0 MOV #<MSB1:MSB0>, W1 MOV #<LSW1>, W2 MOV #<LSW2>, W3 MOV #<MSB3:MSB2>, W4 MOV #<LSW3>, W5

Step 8: Set the read pointer (W6) and load the (next four write) latches.

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0300000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB1BB6000000000000

CLR W6NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B[W6++], [W7++] NOPNOPTBLWTH.B[W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOPNOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B[W6++], [W7++] NOPNOPTBLWTH.B[W6++], [++W7] NOPNOPTBLWTL [W6++], [W7++] NOPNOP

Step 9: Repeat Steps 7-8 sixteen times to load the write latches for the 64 instructions.

Step 10: Initiate the programming cycle.

000000000000

A8E761000000000000

BSET NVMCON, #15 NOPNOP

Step 11: Wait for the Row Program operation to complete.

-

0000000000000001

-

807600887840000000<VISI>

Externally time ‘P13’ msec (see Section TABLE 8-1: “AC/DC Characteristics and Timing Requirements”) to allow suffi-cient time for the Page Erase operation to complete.


TABLE 6-1: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)

Command(Binary)

Data(Hex)

Description



Step 12: Reset the device internal PC.

00000000

040200000000

GOTO 0x200 NOP

Step 13: Repeat Steps 7-12 until all 32 rows of executive memory have been programmed.

TABLE 6-1: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)

Command(Binary)

Data(Hex)

Description



6.2 Programming Verification

After the programming executive has beenprogrammed to executive memory using ICSP, it mustbe verified. Verification is performed by reading out thecontents of executive memory and comparing it withthe image of the programming executive stored in theprogrammer.

Reading the contents of executive memory can beperformed using the same technique described inSection 5.8 “Reading Code Memory”. A procedurefor reading executive memory is shown in Table 6-2.Note that in Step 2, the TBLPAG register is set to 0x80,such that executive memory may be read.

TABLE 6-2: READING EXECUTIVE MEMORY

Command(Binary)

Data(Hex)

Description


0000000000000000

000000000000040200000000

NOPNOPGOTO 0x200NOP


000000000000

200800880190EB0300

MOV #0x80, W0 MOV W0, TBLPAGCLR W6

Step 3: Initialize the write pointer (W7) to point to the VISI register.

0000 207847 MOV #VISI, W7

Step 4: Read and clock out the contents of the next two locations of executive memory through the VISI register using the REGOUT command.

000000000000000000010000000000000001

000000BA1B96000000000000<VISI>BA9BB6000000000000<VISI>

NOPTBLRDL [W6], [W7] NOPNOPClock out contents of VISI registerTBLRDH [W6++], [W7] NOPNOPClock out contents of VISI register

Step 5: Reset the device internal PC.

00000000

040200000000

GOTO 0x200 NOP

Step 6: Repeat Steps 4-5 until all 2048 instruction words of executive memory are read.



7.0 DEVICE ID

The device ID region of memory can be used todetermine mask, variant and manufacturinginformation about the chip. The device ID region is2 x 16-bits and it can be read using the READCcommand. This region of memory is read-only and canalso be read when code protection is enabled.

Table 7-1 shows the device ID for each device, Table 7-2shows the Device ID registers and Table 7-3 describesthe bit field of each register.

TABLE 7-1: DEVICE IDs Device DEVID DEVREV

dsPIC33FJ64GP206 0xC1 0x3000

dsPIC33FJ64GP306 0xCD 0x3000

dsPIC33FJ64GP310 0xCF 0x3000

dsPIC33FJ64GP706 0xD5 0x3000




dsPIC33FJ128GP306 0xE5 0x3000

dsPIC33FJ128GP310 0xE7 0x3000

dsPIC33FJ128GP706 0xED 0x3000

dsPIC33FJ128GP708 0xEE 0x3000

dsPIC33FJ128GP710 0xEF 0x3000

dsPIC33FJ256GP506 0xF5 0x3000

dsPIC33FJ256GP510 0xF7 0x3000

dsPIC33FJ256GP710 0xFF 0x3000

dsPIC33FJ64MC506 0x89 0x3000

dsPIC33FJ64MC508 0x8A 0x3000

dsPIC33FJ64MC510 0x8B 0x3000

dsPIC33FJ64MC706 0x91 0x3000

dsPIC33FJ64MC710 0x97 0x3000

dsPIC33FJ128MC506 0xA1 0x3000



dsPIC33FJ128MC708 0xAE 0x3000

dsPIC33FJ128MC710 0xAF 0x3000

dsPIC33FJ256MC510 0xB7 0x3000

dsPIC33FJ256MC710 0xBF 0x3000

PIC24HJ64GP206 0x41 0x3000

PIC24HJ64GP210 0x47 0x3000

PIC24HJ64GP506 0x49 0x3000

PIC24HJ64GP510 0x4B 0x3000

PIC24HJ128GP206 0x5D 0x3000

PIC24HJ128GP210 0x5F 0x3000

PIC24HJ128GP306 0x65 0x3000

PIC24HJ128GP310 0x67 0x3000

PIC24HJ128GP506 0x61 0x3000

PIC24HJ128GP510 0x63 0x3000

PIC24HJ256GP206 0x71 0x3000

PIC24HJ256GP210 0x73 0x3000

PIC24HJ256GP610 0x7B 0x3000

dsPIC33FJ12GP201 0x802 0x3000

dsPIC33FJ12GP202 0x803 0x3000

dsPIC33FJ12MC201 0x800 0x3000

dsPIC33FJ12MC202 0x801 0x3000

PIC24HJ12GP201 0x80A 0x3000

PIC24HJ12GP202 0x80B 0x3000



TABLE 7-2: dsPIC33F/PIC24H PROGRAMMING SPECIFICATION DEVICE ID REGISTERS

TABLE 7-3: DEVICE ID BITS DESCRIPTION

Address NameBit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0xFF0000 DEVID MASK<9:0> VARIANT<5:0>

0xFF0002 DEVREV PROC<3:0> REV<5:0> DOT<5:0>


MASK<9:0> DEVID Encodes the MASKSET ID of the device.

VARIANT<5:0> DEVID Encodes the VARIANT derived from MASKSET of the device.

PROC<3:0> DEVREV Encodes the process of the device.

REV<5:0> DEVREV Encodes the major revision number of the device.

DOT<5:0> DEVREV Encodes the minor revision number of the device.



8.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS

Table 8-1 lists AC/DC characteristics and timingrequirements.

TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS

Standard Operating ConditionsOperating Temperature: –40°C-85°C. Programming at 25°C is recommended.

Param No.

Symbol Characteristic Min Max Units Conditions

D111 VDD Supply Voltage During Programming VDDCORE 3.60 V Normal programming(1)

D112 IPP Programming Current on MCLR — 5 μA

D113 IDDP Supply Current During Programming — 2 mA

D031 VIL Input Low Voltage VSS 0.2 VDD V

D041 VIH Input High Voltage 0.8 VDD VDD V

D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 3.6V

D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 3.6V

D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications

D013 CF Filter Capacitor Value on VCAP 1 10 μF Required for controller core

P1 TPGC Serial Clock (PGC) Period 136 — ns

P1A TPGCL Serial Clock (PGC) Low Time 40 — ns

P1B TPGCH Serial Clock (PGC) High Time 40 — ns

P2 TSET1 Input Data Setup Time to Serial Clock ↓ 15 — ns

P3 THLD1 Input Data Hold Time from PGC ↓ 15 — ns

P4 TDLY1 Delay between 4-bit Command and Command Operand

40 — ns

P4A TDLY1A Delay between Command Operand and Next 4-bit Command

40 — ns

P5 TDLY2 Delay between Last PGC ↓ of Command to First PGC ↑ of Read of Data Word

20 — ns

P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns

P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms

P8 TDLY3 Delay between Last PGC ↓ of Command Byte to PGD ↑ by Programming Executive

12 — μs

P9a TDLY4 Programming Executive Command Processing Time

10 — μs

P9b TDLY5 Delay between PGD ↓ by Programming Executive to PGD Released by Programming Executive

15 23 μs

P10 TDLY6 PGC Low Time After Programming 400 — ns

P11 TDLY7 Bulk Erase Time 200 — ms

P12 TDLY8 Page Erase Time 20 — ms

P13 TDLY9 Row Programming Time 1.5 — ms

P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 μs

P15 TVALID Data Out Valid from PGC ↑ 10 — ns

P16 TDLY10 Delay between Last PGC ↓ and MCLR ↓ 0 — s

P17 THLD3 MCLR ↓ to VDD ↓ — 100 ns

Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always bewithin ±0.3V of VDD and VSS, respectively.



P18 TKEY1 Delay from First MCLR ↓ to First PGC ↑ for Key Sequence on PGD

40 — ns

P19 TKEY2 Delay from Last PGC ↓ for Key Sequence on PGD to Second MCLR ↑

25 — ns

P20 TDLY11 Maximum Wait Time for Configuration Register Programming

25 ms

TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)

Standard Operating ConditionsOperating Temperature: –40°C-85°C. Programming at 25°C is recommended.

Param No.

Symbol Characteristic Min Max Units Conditions

Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always bewithin ±0.3V of VDD and VSS, respectively.



NOTES:



APPENDIX A: REVISION HISTORY

Revision C (June 2006)

• Added code protection Configuration register descriptions

• Added information about Unit ID• Added ERASES, ERASEG and ERASEC

programming executive commands• Added checksum computation equation

Revision D (March 2007)

• Added information specific to the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices in sev-eral sections, including pinout diagrams, program memory sizes and Device ID values

• Added specific checksum computations for all dsPIC33F and PIC24H devices

• Updated ICSP bulk/page erase and row/byte pro-gram code examples to show externally timed operation (waiting for specific delay periods)

• Added the P20 timing characteristic• Updated timing characteristics and references to

the timing characteristics• Updated the ICSP code examples



NOTES:


Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.


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