237
Spring 2011 CSCI 565 - Compiler Design Pedro Diniz [email protected] Data-Flow Analysis Copyright 2011, Pedro C. Diniz, all rights reserved. Students enrolled in the Compilers class at the University of Southern California have explicit permission to make copies of these materials for their personal use. Overview Available Expressions Problem and Iterative Data-Flow Formulation

Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz [email protected] • Overview of Control-Flow Analysis • DU Chains

  • Upload
    others

  • View
    28

  • Download
    0

Embed Size (px)

Citation preview

Page 1: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected]

Data-Flow Analysis

Copyright 2011, Pedro C. Diniz, all rights reserved. Students enrolled in the Compilers class at the University of Southern California have explicit permission to make copies of these materials for their personal use.

Overview Available Expressions Problem and

Iterative Data-Flow Formulation

Page 2: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 2

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 3: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 3

Control Flow of a Program

•  Forms a Graph

•  A Very Large Graph •  Create Basic Blocks •  A Control-Flow Graph (CFG) connects basic blocks

Page 4: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 4

Control Flow Graph (CFG) •  Control-Flow Graph G = <N, E> •  Nodes(N): Basic Blocks •  Edges(E): (x,y) ∈ E iff first instruction in the basic

block y follows the last instruction in the basic block x

Page 5: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 5

Identifying Recursive Structures Loops

•  Identify back edges •  Find the nodes and edges in the loop

given by the back edge •  Other than the back edge

–  Incoming edges only to the basic block with the back edge head

–  one outgoing edge from the basic block with the tail of the back edge

•  How do I find the back edges?

bb1

bb2

bb4 bb3

bb5

bb6

Page 6: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 6

Computing Dominators •  Algorithm

–  Make dominator set of the entry node as itself –  Make dominator set of the remainder nodes include all the nodes –  Visit the nodes in any order –  Make dominator set of the current node as the intersection of the

dominator sets of the predecessor nodes and the current node –  Repeat until no change

Page 7: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 7

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

nodes to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 8: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 8

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

nodes to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

bb1 bb2 bb3 bb4 bb5 bb6

Page 9: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 9

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

nodes to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

Page 10: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 10

Computing Dominators

bb1

bb2

bb4 bb3

bb5

bb6

{bb1}

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

Page 11: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 11

Computing Dominators

bb1

bb2

bb4 bb3

bb5

bb6

{bb1}

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 12: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 12

Computing Dominators

bb1

bb2

bb4 bb3

bb5

bb6

{bb1}

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 13: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 13

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2

bb1 bb2 bb3 bb4 bb5 bb6

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 14: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 14

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 15: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 15

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb4 bb5 bb6

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 16: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 16

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 17: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 17

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 18: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 18

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 19: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 19

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb4 bb5 bb6

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 20: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 20

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 21: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 21

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 22: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 22

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 23: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 23

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 24: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 24

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 25: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 25

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb3 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 26: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 26

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 27: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 27

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb3 bb5 bb6

bb1 bb2 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 28: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 28

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 29: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 29

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 30: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 30

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

•  Algorithm –  Make dominator set of the entry node

as itself –  Make dominator set of the remainder

node to include all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node as the intersection of the dominator sets of the predecessor nodes and the current node

–  Repeat until no change

Page 31: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 31

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 32: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 32

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 33: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 33

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 34: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 34

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 35: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 35

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 36: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 36

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 37: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 37

Computing Dominators

bb2

bb4 bb3

bb5

bb6

{bb1} bb1

•  Algorithm –  Make dominator set of the entry node

has itself –  Make dominator set of the rest have

all the nodes –  Visit the nodes in any order –  Make dominator set of the current

node intersection of the dominator sets of the predecessor nodes + the current node

–  Repeat until no change bb1 bb2 bb4

bb1 bb2 bb3

bb1 bb2

bb1 bb2 bb5 bb6

bb1 bb2 bb5

Page 38: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 38

Computing Dominators •  What we just witness was an Iterative

Data-Flow Analysis Algorithm in Action –  Initialize all the nodes to a given value –  Visit nodes in some order –  Calculate the node’s value –  Repeat until no value changes (fixed-point computation)

Page 39: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 39

Data-Flow Analysis •  Local Analysis

–  Analyze the effect of each instruction in each Basic Block –  Compose effects of instructions to derive information from beginning

of basic block to each instruction

•  Data-Flow Analysis –  Iteratively propagate basic block information over the control-flow

graph until no changes –  Calculate the final value at the beginning of the basic block

•  Local Propagation –  propagate the information from the beginning of the basic block to

each instruction

Page 40: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 40

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 41: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 41

Example: Available Expression •  An Expression is Available if and only if

–  All paths of execution reaching the current point passes through the point where the expression was defined

–  No variable used in the expression was modified between the definition point and the current point

Page 42: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 42

Example: Available Expression

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

Page 43: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 43

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

YES!

Page 44: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 44

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

YES!

Page 45: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 45

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

NO!

Page 46: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 46

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

NO!

Page 47: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 47

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

NO!

Page 48: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 48

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

YES!

Page 49: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 49

Is the Expression Available?

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

YES!

Page 50: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 50

Use of Available Expressions

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

Page 51: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 51

Use of Available Expressions

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

Page 52: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 52

Use of Available Expressions

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

Page 53: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 53

Use of Available Expressions

a = b + c d = e + f f = a + c

g = f

j = a + b + c + d

b = a + d h = c + f

Page 54: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 54

Use of Available Expressions

a = b + c d = e + f f = a + c

g = f

j = a + b + c + d

b = a + d h = c + f

Page 55: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 55

Use of Available Expressions

a = b + c d = e + f f = a + c

g = f

j = a + c + b + d

b = a + d h = c + f

Page 56: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 56

Use of Available Expressions

a = b + c d = e + f f = a + c

g = f

j = f + b + d

b = a + d h = c + f

Page 57: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 57

Use of Available Expressions

a = b + c d = e + f f = a + c

g = f

j = f + b + d

b = a + d h = c + f

Page 58: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 58

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 59: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 59

Algorithm for Available Expression •  Assign a Number to each Expression

Page 60: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 60

Example: Available Expression

a = b + c d = e + f f = a + c

g = a + c

j = a + b + c + d

b = a + d h = c + f

Page 61: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 61

Example: Available Expression

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Page 62: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 62

Gen and Kill Sets •  Gen Set

–  If a basic block (or instruction) defines the expression then the expression number is in the Gen Set for that basic block (or instruction)

•  Kill Set –  If a basic block (or instruction) redefines a variable in the expression

then that expression number is in the kill set for that basic block (or instruction)

–  Expression is thus not valid after that basic block (or instruction)

Page 63: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 63

Algorithm for Available Expression •  Assign a Number to each Expression •  Calculate Gen and Kill set for each instruction

Page 64: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 64

Gen and Kill Sets a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Page 65: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 65

Gen and Kill Sets

a = b + c 1

d = e + f 2

f = a + c 3

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Page 66: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 66

Gen and Kill Sets

a = b + c 1 gen = { b + c } kill = { any expr with a }

d = e + f 2 gen = { e + f } kill = { any expr with d }

f = a + c 3 gen = { a + c } kill = { any expr with f }

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Page 67: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 67

Gen and Kill Sets

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Page 68: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 68

Algorithm for Available Expression •  Assign a Number to each Expression •  Calculate Gen and Kill sets for each instruction •  Calculate Aggregate Gen and Kill sets for each basic

block

Page 69: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 69

Aggregate Gen and Kill Sets

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

•  Propagate all the Gen and Kill sets from top of the basic block to the bottom of the basic block

Page 70: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 70

Aggregate Gen Set

OutGEN =

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InGEN set

OutGEN set

Page 71: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 71

Aggregate Gen Set •  The Gen set in the current

expression should be in the OutGEN Set

OutGEN = gen

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InGEN set

OutGEN set

Page 72: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 72

Aggregate Gen Set •  The Gen set in the current

expression should be in the OutGEN Set

•  Any expression in the InGEN Set that is not killed should be in the OutGEN Set

OutGEN = gen ∪ (InGEN - kill)

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InGEN set

OutGEN set

Page 73: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 73

Aggregate Gen Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

Page 74: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 74

Aggregate Gen Set

OutGEN = gen ∪ (InGEN - kill)

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

Page 75: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 75

Aggregate Gen Set

OutGEN = { 1 } ∪ ({ } - { 3,4,5,7})

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

Page 76: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 76

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

Page 77: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 77

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = gen ∪ (InGEN - kill)

Page 78: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 78

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 2 } ∪ ({ 1 } - { 5,7 })

Page 79: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 79

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 }

Page 80: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 80

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 } InGEN = { 1, 2 }

OutGEN = gen ∪ (InGEN - kill)

Page 81: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 81

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 } InGEN = { 1, 2 }

OutGEN = { 3 } ∪ ({1, 2} - {2, 6})

Page 82: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 82

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 } InGEN = { 1, 2 }

OutGEN = { 1, 3 }

Page 83: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 83

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 } InGEN = { 1, 2 }

OutGEN = { 1, 3 }

Page 84: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 84

Aggregate Gen Set

OutGEN = { 1 }

InGEN = { }

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

InGEN = { 1 }

OutGEN = { 1, 2 } InGEN = { 1, 2 }

OutGEN = { 1, 3 }

GE

N =

{ 1,

3 }

Page 85: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 85

Aggregate Kill Set

OutKILL =

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InKILL set

OutKILL set

Page 86: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 86

Aggregate Kill Set •  The kill set in the current

expression should be in the OutKILL set

OutKILL = kill

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InKILL set

OutKILL set

Page 87: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 87

Aggregate Kill Set •  The kill set in the current

expression should be in the OutKILL set

•  Any set in the InKILL should be in OutKILL

OutKILL = kill ∪ InKILL

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

InKILL set

OutKILL set

Page 88: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 88

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

Page 89: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 89

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = kill ∪ InKILL

InKILL = { }

Page 90: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 90

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 } ∪ { }

InKILL = { }

Page 91: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 91

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

Page 92: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 92

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = kill ∪ InKILL

InKILL = { 3, 4, 5, 7 }

Page 93: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 93

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = { 5, 7 } ∪ { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

Page 94: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 94

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

Page 95: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 95

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

OutKILL = kill ∪ InKILL

InKILL = { 3, 4, 5, 7 }

Page 96: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 96

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

OutKILL = { 2, 6 } ∪ { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

Page 97: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 97

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

OutKILL = { 3, 4, 5, 7 }

InKILL = { }

OutKILL = { 3, 4, 5, 7 }

InKILL = { 3, 4, 5, 7 }

OutKILL = { 2, 3, 4, 5, 6, 7 }

InKILL = { 3, 4, 5, 7 }

Page 98: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 98

Aggregate Kill Set

a = b + c 1

gen = { 1 } kill = { 3, 4, 5, 7 }

d = e + f 2 gen = { 2 } kill = { 5, 7 }

f = a + c 3 gen = { 3 } kill = { 2, 6 }

KIL

L =

{ 2, 3

, 4, 5

, 6, 7

}

Page 99: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 99

Aggregate Gen and Kill Sets a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

Page 100: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 100

Algorithm for Available Expression •  Assign a Number to each Expression •  Calculate Gen and Kill Sets for each instruction •  Calculate Aggregate Gen and Kill Sets for each basic

block •  Initialize available set at each basic block to be the

entire set

Page 101: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 101

Aggregate Gen and Kill Sets IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

Page 102: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 102

Algorithm for Available Expression •  Assign a Number to each Expression •  Calculate Gen and Kill sets for each instruction •  Calculate Aggregate Gen and Kill sets for each basic

block •  Initialize available set at each basic block to be the

entire set •  Iteratively propagate available expression set over the

CFG

Page 103: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 103

Propagate Available Expression Set

OUT =

gen = { … } kill = { ... }

IN set

OUT set

Page 104: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 104

•  If the expression is generated (in the gen set) then it is available at the end –  should in the OUT set

OUT = gen

gen = { … } kill = { ... }

IN set

OUT set

Propagate Available Expression Set

Page 105: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 105

•  If the expression is generated (in the gen set) then it is available at the end –  should in the OUT set

•  Any expression available at the input (in the IN set) and not killed should be available at the end

OUT = gen ∪ (IN - kill)

gen = { … } kill = { ... }

IN set

OUT set

Propagate Available Expression Set

Page 106: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 106

OUT = gen ∪ (IN - kill)

IN set

IN =

Propagate Available Expression Set

Page 107: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 107

•  Expression is available only if it is available in All Input Paths

OUT = gen ∪ (IN - kill) IN = ∩ OUT

Propagate Available Expression Set

IN set

Page 108: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 108

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

Page 109: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 109

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1,2,3,4,5,6,7}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

Page 110: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 110

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

Page 111: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 111

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

Page 112: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 112

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1, 3}

OUT = {1,2,3,4,5,6,7}

Page 113: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 113

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1, 3}

OUT = {1, 3, 4}

Page 114: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 114

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1,2,3,4,5,6,7}

IN = {1, 3}

OUT = {1, 3, 4}

Page 115: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 115

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 116: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 116

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 117: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 117

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1,2,3,4,5,6,7}

OUT = {1,2,3,4,5,6,7}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 118: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 118

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {1,2,3,4,5,6,7}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 119: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 119

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 120: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 120

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 121: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 121

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 122: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 122

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 123: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 123

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = {1, 3, 4}

IN = {1, 3}

OUT = {1, 3, 4}

Page 124: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 124

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {1, 3, 4, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 125: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 125

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 126: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 126

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = {1, 3}

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 127: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 127

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 128: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 128

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 129: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 129

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 130: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 130

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 131: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 131

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 132: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 132

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 133: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 133

Aggregate Gen and Kill Sets

OUT = gen ∪ (IN - kill)

IN = ∩ OUT IN = { }

OUT = {1, 3}

a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1, 3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5, 6 } Kill = { 1, 7 }

Gen = { 7 } Kill = { }

IN = { 3 }

OUT = {3, 5, 6}

OUT = {3, 7}

IN = { 3 }

IN = {1, 3}

OUT = {1, 3, 4}

Page 134: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 134

Algorithm for Available Expression •  Assign a Number to each Expression •  Calculate Gen and Kill Sets for each Instruction •  Calculate aggregate Gen and Kill Sets for each basic

block •  Initialize Available Set at each basic block to be the

entire set •  Iteratively propagate available expression set over the

CFG •  Propagate within the basic block

Page 135: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 135

Propagate within the Basic Block •  Start with the IN set of available

expressions •  Linearly propagate down the

basic block –  same as data-flow step –  single pass since no back edges

OUT = gen ∪ (IN - kill)

a = b + c 1 gen = { 1 } kill = { 3, 4, 5, 7 }

IN set

OUT set

Page 136: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 136

Available Expressions

ae = { } a = b + c 1 ae = { 1 } d = e + f 2 ae = { 1, 2 } f = a + c 3 ae = { 1, 3 }

ae = { 1, 3 } g = a + c 4 ae = { 1, 3, 4 }

ae = { 3 } j = a + b + c + d 7 ae = { 3, 7 }

ae = { 3 } b = a + d 5 ae = { 3, 5 } h = c + f 6 ae = { 3, 5, 6 }

Page 137: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 137

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 138: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 138

Practical Issues: Bit Sets •  Assign a bit to each element of the set

–  Union ⇒ bit OR –  Intersection ⇒ bit AND –  Subtraction ⇒ bit NEGATE and AND

•  Fast implementation –  32 elements packed to each word –  AND and OR are single instructions

Page 139: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 139

Kill Set vs. Preserve Set •  Kill Sets

– OUT = gen ∪ (IN - kill) – Using bit vectors: OUT = gen ∨ (IN - kill) –  Subtraction ⇒ bit NEGATE and AND

– OUT = gen ∨ (IN ∧ ¬ kill)

•  Preserve Sets –  Used in other formulations of the Problem –  PRSV = Entire Set - KILL

– OUT = gen ∪ (IN ∩ prsv) – OUT = gen ∨ (IN ∧ prsv)

Page 140: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 140

Aggregate Gen and Kill Sets a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1,3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5,6 } Kill = { 1,7 }

Gen = { 7 } Kill = { }

Page 141: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 141

Aggregate Gen and Kill Sets a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

Gen = { 1,3} Kill = { 2,3,4,5,6,7 }

Gen = { 4 } Kill = { }

Gen = { 5,6 } Kill = { 1,7 }

Gen = { 7 } Kill = { }

7 bits per set required

Page 142: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 142

Aggregate Gen and Kill Sets a = b + c 1 d = e + f 2 f = a + c 3

g = a + c 4

j = a + b + c + d 7

b = a + d 5 h = c + f 6

7 bits per set required Gen = 1010000 Kill = 0111111

Gen = 0001000 Kill = 0000000

Gen = 0000110 Kill = 1000001

Gen = 0000001 Kill = 0000000

Page 143: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 143

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 144: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 144

Formulating an Iterative Data-Flow Analysis Problem

•  Problem Independent –  Calculate Gen and Kill Sets for each Basic Block –  Iterative Propagation of Information until Convergence –  Propagation of Information within the Basic Block

Page 145: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 145

Formulating an Iterative Data-Flow Analysis Problem

•  Lattice –  Abstract quantities over which the analysis will operate

example: sets of available expressions

•  Flow Functions –  How each control-flow and computational construct affects the

abstract quantities Example: the OUT equation for each statement

Page 146: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 146

Lattice •  A Lattice L consists of

–  A Set of Values

–  Two operations meet( ∧ ) and join ( ∨ )

–  A top value (T) and a bottom value (⊥)

Page 147: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 147

Lattice •  Example: the Lattice for the Reaching Definition

Problem when there are only 3 definitions

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

Page 148: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 148

Meet and Join Operations •  Meet and Join forms a closure

–  For all a, b ∈ L there exist a unique c and d ∈ L such that a ∧ b = c a ∨ b = d

•  Meet and Join are commutative –  a ∧ b = b ∧ a a ∨ b = b ∨ a

•  Meet and Join are associative –  (a ∧ b) ∧ c = b ∧ (a ∧ c) (a ∨ b) ∨ c = b ∨ (a ∨ c)

•  There exist a unique top element (T) and bottom element (⊥) in L such that –  a ∧ ⊥ = ⊥ a ∨ T = T

Page 149: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 149

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∧ { d2, d3 } = ???

Page 150: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 150

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∧ { d2, d3 } = ???

Page 151: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 151

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∧ { d2, d3 } = { d2 }

Page 152: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 152

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∨ { d3 } = ???

Page 153: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 153

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∨ { d3 } = ???

Page 154: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 154

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∨ { d3 } = ???

Page 155: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 155

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∨ { d3 } = ???

Page 156: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 156

Meet and Join Operations

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

{ d1, d2 } ∨ { d3 } = { d1, d2, d3}

Page 157: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 157

Meet and Join Operations

•  Meet Operation: Greatest Lower Bound - GLB({x,y}) –  Typically Set Intersection –  Follow the lines downwards from the two elements in the lattice until

they meet at a single unique element

•  Join Operation: Lowest Upper Bound - LUB({x,y}) –  Typically Set Union –  There is a unique element in the lattice from where there is a

downwards path (with no shared segment) to both elements

Page 158: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 158

Partial Order •  Define a ⊆ b if and only if a ∧ b = b •  Properties

–  Reflexive: a ⊆ a –  Antisymmetric: a ⊆ b and b ⊆ a ⇒ a = b –  Transitive: a ⊆ b and b ⊆ c ⇒ a ⊆ c

Page 159: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 159

Partial Order •  Define a ⊆ b if and only if a ∧ b = b •  Properties

–  a ⊆ b ⇒ there exit a path from b to a

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

Page 160: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 160

Lattice Height •  The height of the lattice is the longest ascending

chain in it –  (T, a, b, c, …, ⊥)

Page 161: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 161

Lattice Height •  The height of the lattice is the longest ascending

chain in it –  (T, a, b, c, …, ⊥)

–  Height is (T, {d2,d3}, {d3}, ⊥) = 4

{ d1, d2 }

{ d2, d3 }

{ d1 }

{ d3 }

⊥ = { }

T = { d1, d2, d3 }

{ d1, d3 } { d2 }

Page 162: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 162

Flow Functions •  Example: OUT = f(IN) •  f: L → L where L is a lattice •  Properties

–  Monotone: ∀a,b ∈ L a ⊆ b ⇒ f(a) ⊆ f(b)

•  Fixed Point –  A fixed point is an element a ∈L such that f(a) = a

Page 163: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 163

Intuition about Termination •  Data-flow analysis starts assuming most optimistic

values (T) •  Each stage applies a flow function

–  Vnew ⊆ Vprev –  Moves downwards in the lattice

•  Until stable (values don’t change) –  A fixed point is reached at every basic block

•  Lattice has a finite height ⇒ should terminate

Page 164: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 164

Dataflow Analysis Framework

•  A dataflow analysis framework consists of: –  A lattice (L, ⊆, ∩, ⊥) where:

•  L is the dataflow information •  ⊆ is the ordering relation •  ∩ is the merge operation (GLB)

•  ⊥ is the bottom element

–  Transfer functions Fn : L → L for each CFG node n

–  Boundary dataflow information d0 •  Before CFG entry node for a forward analysis •  After CFG exit node for a backward analysis

Page 165: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 165

Dataflow Equations

•  Forward Data-Flow Analysis:

in[n0] = d0, where n0 = CFG entry node out[n] = Fn (in[n]), for all n in[n] = ∩ {out[n’] | n’∈ pred(n)}, for all n

•  Backward Data-Flow Analysis:

out[n0] = d0, where n0 = CFG exit node in[n] = Fn (out[n]), for all n out[n] = ∩ {in[n’] | n’∈ succ(n)}, for all n

Page 166: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 166

Solving the Data-Flow Equations •  The Constraints (Forward Analysis):

in[n0] = d0, where n0 = CFG entry node out[n] = Fn (in[n]), for all n in[n] = ∩ {out[n’] | n’∈ pred(n)}, for all n

•  Solution = the set of all in[n], out[n] for all n’s, such that all Constraints are satisfied

•  Fixed-Point Algorithm to Solve Constraints: –  Initialize in[n0]=d0

–  Initialize everything else to ⊥ –  Repeatedly enforce Constraints –  Stop when Dataflow Solution

Page 167: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 167

Worklist Algorithm (Forward) in[n0] = d0

in[n] = ⊥, for all n ≠ n0

out[n] = ⊥, for all n

worklist = {n0}

while ( worklist ≠ ∅ ) Remove a node n from the worklist out[n] = Fn(in[n])

for each successor n’ : in[n’] = in[n’] ∩ out[n] - distributivity at work if (in[n’] has changed) add n’ to the worklist

Page 168: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 168

An Implementation void analyzeForward(Method m, DataflowInfo d0) { result.put(m.getCFG().getEntryNode(), d0); Stack<CFGNode> worklist = new Stack<CFGNode>(); while (!worlist.isEmpty()) { CFGNode n = worklist.pop(); DataflowInfo in = result.get(n); DataflowInfo out = transferFunction(n,in); for (CFGNode succ : n.getSuccessors()) if (merge(succ, out))

worklist.add(succ); } }

Page 169: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 169

An Implementation boolean merge(CFGNode n, DataflowInfo d) { DataflowInfo info = result.get(n); if (info == null) { result.put(n, d.clone()); return true; } return info.meet(d); }

Page 170: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 170

Correctness •  Correctness of the worklist algorithm:

–  At the end, all dataflow equations are satisfied

•  Argument: –  Loop maintains the invariant that the constraints

in[n] = ∩ {out[n’] | n’∈ pred(n)} out[n] = Fn(in[n])

hold for all the nodes n not in the worklist –  At the end, worklist is empty

Page 171: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 171

Transfer Functions •  Transfer functions are required to be monotonic:

F : L → L is monotonic if x ⊆ y implies F(x) ⊆ F(y)

•  Distributivity: function F : L → L is distributive if F(x ∩ y) = F(x) ∩ F(y)

•  Property: F is monotonic iff F(x ∩ y) ⊆ F(x) ∩ F(y) - any distributive function is monotonic

Page 172: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 172

Termination •  Do these Algorithms Terminate?

•  Observation: at each iteration, information increases in the lattice ink+1[n] ⊆ ink[n] and outk+1[n] ⊆ outk[n]

•  Proof by Induction: –  Induction basis: true, because we start with bottom element, which is less

than everything –  Induction step: use monotonicity of transfer functions and join operation

•  Information forms a chain: in1[n] ⊆ in2[n] ⊆ in3[n] …

Page 173: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 173

Chains in Lattices •  A chain in a lattice L is a totally ordered subset S of L:

x ⊆ y or y ⊆ x for any x, y ∈ S

•  In other words: Elements in a totally ordered subset S can be indexed to form an descending sequence:

x1 ⊆ x2 ⊆ x3 ⊆ …

•  Height of a lattice = size of its largest chain •  Lattice with finite height: only has finite chains

Page 174: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 174

Termination •  In the iterative algorithm, for each node n:

{in1[n], in2[n], …} is a chain in the lattice

•  If lattice has finite height then there is a number k such that ini[n] = ini+1[n], for all i ≥ k and all n

•  If ini[n] = ini+1[n] then also outi[n] = outi+1[n] •  Algorithm terminates in at most k*N iterations, where N is the number of

CFG nodes

•  To summarize: dataflow analysis terminates if 1. Transfer functions are monotonic 2. Lattice has finite height

Page 175: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 175

•  The iterative algorithm computes a solution of the system of dataflow equations

•  … is the solution unique?

•  No, dataflow equations may have multiple solutions !

•  Example: Live Variables Equations: I1 = I2-{y} I3 = (I4-{x}) ∨ {y} I2 = I1 ∨ I3 I4 = {x}

Solution 1: I1={ }, I2={y}, I3={y}, I4={x} Solution 2: I1={x}, I2={x,y}, I3={y}, I4={x}

Multiple Solutions

x = y

y = 1 I1

I2

I3

I4

Page 176: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 176

Safety and Precision •  Safety: any solution that satisfies the dataflow equations is safe •  Precision: a solution to an analysis problem is more precise if

it less conservative

•  Live Variables Analysis Problem: –  Solution is more precise if the sets of live variables are smaller –  Solution which reports that all variables are live at each point is safe,

but is too imprecise

•  In the lattice framework: d1 is more precise than d2 if d1 is higher in the lattice than d2: d2 ⊆ d1

Page 177: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 177

Maximal Fixed Point Solution (MFP) •  Claim:

Among all the solutions to the system of dataflow equations, the iterative solution is the most precise

•  Intuition: –  We start with the top element at each program point (i.e. most precise

information) –  Then refine the information at each iteration to satisfy the dataflow

equations –  Final result will be the closest to the top

•  Iterative solution for dataflow equations is called Maximal Fixed Point solution (MFP)

•  For any Fixed-Point (FP) solution of the equations: FP ⊆ MFP

Page 178: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 178

Meet Over Paths Solution (MOP) •  Is MFP the best solution to the Analysis Problem?

•  Another approach: consider a lattice framework, but use a different way to compute the solution –  Let G be the control flow graph with start node n0 –  For each path pk=[n0, n1, …, nk] from entry to node nk:

in[pk] = Fnk-1 ( … (Fn1(Fn0(d0)))) –  Compute solution as

in[n] = ∨ { in[pk] | all paths pk from n0 to nk}

•  This solution is the Meet Over Paths solution (MOP)

Page 179: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 179

MFP versus MOP •  Precision: can prove that MOP solution is always more precise

than MFP

MFP ⊆ MOP

•  Why not use MOP? •  MOP is intractable in practice

1. Exponential number of paths: for a program consisting of a sequence of N if statements, there will 2N paths in the control flow graph

2. Infinite number of paths: for loops in the CFG

Page 180: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 180

Importance of Distributivity

•  Property: if transfer functions are distributive, then the solution to the dataflow equations is identical to the meet-over-paths solution

MFP = MOP •  For distributive transfer functions, can compute the intractable

MOP solution using the iterative fixed-point algorithm

Page 181: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 181

Can We Do Better Than MOP? •  Is MOP the best solution to the analysis problem?

•  MOP computes solution for all path in the CFG •  There may be paths which will

never occur in any execution •  So MOP is conservative

•  IDEAL = solution which takes into account only paths which occur in some execution

•  This is the best solution –  but it is undecidable

x = 1 x = 2

y = y+2

if (c)

if (c)

y = x+1

Page 182: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 182

Summary •  Data-Flow Analysis

–  Sets up system of equations –  Iteratively computes MFP –  Terminates because transfer functions are monotonic and lattice has

finite height

•  Other possible solutions: FP, MOP, IDEAL •  All are safe solutions, but some are more precise:

FP ⊆ MFP ⊆ MOP ⊆ IDEAL •  MFP = MOP if distributive transfer functions

•  MOP and IDEAL are intractable •  Compilers use dataflow analysis and MFP

Page 183: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 183

Outline •  Overview of Control-Flow Analysis •  Available Expressions •  Algorithm for Calculating Available Expressions •  Practical Issues: Bit sets •  Formulating a Data-Flow Analysis Problem •  DU chains •  SSA form

Page 184: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 184

Def-Use and Use-Def Chains

•  Def-Use (DU) Chain –  Connects a definition of each variable vk to all the possible

uses of that variable –  A definition of vk at point p reaches point q if there is a path

from p to q where vk is not redefined.

•  Use-Def (UD) Chain –  Connects a use of a variable vk to all the possible definitions

of that variable

Page 185: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 185

DU-Chain Data-Flow Problem Formulation

•  Lattice: The set of Definitions –  Bit-vector format: a bit for each variable definition in the procedure –  Label the definitions in the input program as d1,vk, d2,vk, …

•  Flow Direction: Forward Flow •  Flow Functions:

–  Gen(n) = { di,…, di,n | where di,vk = 1 for definition di,vk in n not killed inside the same basic block by a subsequent definition*}

–  Kill(n) = { di,…, di,n | where di,vk = 1 iff variable vk is defined in n} –  OUT(n) = Gen(n) ∪ (IN(n) – Kill(n))

–  IN(n) = ∪ OUT(p) for all predecessors nodes p of node n

* This is the notion of downwards exposed definition

Page 186: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected]

Gen and Kill Functions

•  Gen = Downwards Exposed Definitions –  Dual to Upwards Exposed Reads (see Live Variables Analysis) –  Can be computed on a Forward pass of the Basic Block

•  Keep a list of variables defined in the block •  Remove and keep only the last definition as you go along

186

k = … 1

i = … 2

j = … 3

i = i + … 4

BBn

Gen(n) = { d1, d3 , d4 } Kill(n) = { d1, d2, d3, d4, … }

Page 187: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 187

DU Example entry

k = false i = 1 j = 2

j = j * 2 k = true i = i + 1 print j i = i + 1

k

exit

i < n

Page 188: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 188

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

Page 189: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 189

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

Page 190: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 190

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { } IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 191: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 191

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { } IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 192: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 192

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { } IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 193: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 193

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 194: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 194

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 195: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 195

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 196: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 196

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 197: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 197

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { }

OUT = { } OUT = { } OUT = { } IN = { }

Page 198: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 198

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { }

OUT = { 4, 5, 6 } OUT = { } OUT = { } IN = { }

Page 199: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 199

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { }

OUT = { 4, 5, 6 } OUT = { } OUT = { } IN = { }

Page 200: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 200

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { } OUT = { } IN = { }

Page 201: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 201

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { } OUT = { } IN = { }

Page 202: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 202

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { } IN = { }

Page 203: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 203

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { } IN = { }

Page 204: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 204

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { }

Page 205: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 205

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 206: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 206

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 207: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 207

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 208: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 208

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 209: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 209

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 210: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 210

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 211: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 211

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 212: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 212

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 213: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 213

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 214: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 214

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 215: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 215

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 216: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 216

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 7 } IN = { 1, 2, 3, 7 }

Page 217: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 217

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 7 }

Page 218: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 218

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 219: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 219

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 220: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 220

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 221: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 221

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 222: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 222

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 223: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 223

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 224: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 224

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 225: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 225

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 } OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

Page 226: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected]

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6

print j i = i + 1 7

k

exit

i < n

gen ={ 1, 2, 3 } kill = { 4,5,6,7 }

gen ={ 4,5,6 } kill = { 1,2,3,7 }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ } kill = { }

gen ={ 7 } kill = { 2,6 }

OUT = { 1, 2, 3 } IN = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { }

OUT = { 1, 2, 3, 4, 5, 6 }

OUT = IN = { 1, 2, 3, 4, 5, 6 }

OUT = { 4, 5, 6 }

OUT = { 1, 2, 3, 4, 5, 6 } OUT = { 1, 3, 4, 5, 7 } IN = { 1, 2, 3, 4, 5, 6, 7 }

IN= { 1, 2, 3, 4, 5, 6 }

Page 227: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected]

DU Example entry

k = false 1 i = 1 2 j = 2 3

j = j * 2 4 k = true 5 i = i + 1 6 print j i = i + 1 7

k

exit

i < n IN = { 1, 2, 3, 4, 5, 6 }

IN = { }

IN = { 1, 2, 3, 4, 5, 6 }

IN = { 1, 2, 3, 4, 5, 6 }

IN = { 1, 2, 3, 4, 5, 6, 7 }

IN = { 1, 2, 3, 4, 5, 6 }

IN = { 1, 2, 3, 4, 5, 6 }

Page 228: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 228

DU Chains •  At each use of a variable, indicates all its possible

definitions (and thus its points) –  Very Useful Information –  Used in Many Optimizations

•  Information can be Incorporate in the representation –  SSA From

Page 229: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 229

Outline •  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form

Page 230: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 230

Static Single Assignment (SSA) Form

•  Each definition has a unique variable name –  Original name + a version number

•  Each use refers to a definition by name

•  What about multiple possible definitions? –  Add special merge nodes so that there can be only a single definition

(Φ functions)

Page 231: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 231

a = 1 b = a + 2 c = a + b a = a + 1 d = a + b

Static Single Assignment (SSA) Form

Page 232: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 232

a = 1 b = a + 2 c = a + b a = a + 1 d = a + b

a1 = 1 b1 = a1 + 2 c1 = a1 + b1 a2 = a1 + 1 d1 = a2 + b1

Static Single Assignment (SSA) Form

Page 233: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 233

a = 1 c = a + 2

b = 1 c = b + 2

d = a + b + c

Static Single Assignment (SSA) Form

Page 234: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected]

a = 1 c = a + 2

b = 1 c = b + 2

d = a + b + c

a1 = 1 c1 = a1 + 2

b1 = 1 c2 = b1 + 2

c3 = Φ(c1, c2) d1 = a1 + b1 + c3

Static Single Assignment (SSA) Form

Page 235: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 235

DU Example entry

k = false i = 1 j = 2

j = j * 2 k = true i = i + 1 print j i = i + 1

k

exit

i < n

Page 236: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 236

DU Example entry

k1 = false i1 = 1 j1 = 2

j2 = j3 * 2 k2 = true i2 = i3 + 1 print j3 i4 = i3 + 1

k3

i5 = Φ(i3, i4) exit

i3 = Φ(i1, i2) j3 = Φ(j1, j2) k3 = Φ(k1, k2) i1 < n

Page 237: Data-Flow Analysis · Data-Flow Analysis • Data-Flow Analysis . CSCI 565 - Compiler Design Spring 2011 Pedro Diniz pedro@isi.edu • Overview of Control-Flow Analysis • DU Chains

Spring 2011 CSCI 565 - Compiler Design

Pedro Diniz [email protected] 237

Summary

•  Overview of Control-Flow Analysis •  Available Expressions Data-Flow Analysis Problem •  Algorithm for Computing Available Expressions •  Practical Issues: Bit Sets •  Formulating a Data-Flow Analysis Problem •  DU Chains •  SSA Form