DASP hardware design: Outline Microelectronic ... · PDF fileMicroelectronic systems solutions using field programmable and application specific integrated circuits ... Example projects

Institute of Applied Microelectronics and Computer Science

University of Rostock, Dept. of Electrical Engineering and Information Technology

Institute of Applied Microelectronics & Computer Science

Dept. of EE & Information TechnologyUniversity of Rostock

DASP hardware design:DASP hardware design:Microelectronic implementationMicroelectronic implementation

prospectivesprospectives

Dirk TimmermannDirk TimmermannDirk Timmermann



OutlineOutline

� Our institute: resources and services� Requirements of D(A)SP HW design� System design flow� Example projects



Research environmentResearch environment

Bauing.-wesen

AllgemeineElektrotechnik

AE

GerätesystemSchaltungst.

GS

InformatikElektrotechnik

u. Informations- technik

Masch.bauSchiffstechn.

Angew. Mikro- elektronik u.

Datentechnik MD

ElektrischeEnergietechnik

EE

MedizinMathem.-Naturwiss.

Ingenieur-wiss.

Wirtsch.-u.Sozial-

wiss.

Technische Bildung i.G.

Theo-logie

Philo-sophie

Agrar-wiss.

Automat.-technik

AT

Nachrichten-technik/Inform.elektronik NT

Universität Rostock Jura

Fach-bereiche

Institute

Fakultäten



Department Department EE & ITEE & IT� Staff: 60 researchers funded by government, 37

researchers by external grants, > 2 Mio DM/year� Industry, EU, Government (DFG, BMBF), State

� 2 independent research institutes (11researchers)

� Communication lab (COMLAB) for our state M-V� > 20 technology spin-offs 1992-1997� Studies and degrees:

� Diploma degree EE� Teacher for EE and Work/Commerce/Technology� Special course Media Technology (in cooperation w. Dept. of CS)� Diploma degree Information Technology / Technical CS (in coop.

w. Dept. Of CS) with B.Sc. and M.Sc. degree� Aiding in the following studies: Wirtschaftsingenieur, Informatik,

Maschinenbau, Biosystemtechnik, Technomathematik



Ressources ofRessources of Institute MD Institute MD

� Staff� 3 professors:

� Timmermann, Pfüller, third chair is currently open

� 6 full time researchers� 3-6 researchers funded by research grants� 3 laboratory staff, about 15 students (working towards diploma

degree)

� Equipment� 3 labs (Integrated Systems, Real Time Systems, Software), 15 Sun

workstations, > 20 PC, 6 industry-PCs� Aptix Rapid-Prototyping System� Various measurement and developments systems� Complete software packages for chip design, HW oriented software

development, real time systems



Working fieldsWorking fields

� Research and education in the following areas:

AppliedMicroelectronics

Realtime processing systems

Embeddedsoftware technology



Research atResearch at Institute MD Institute MD

Object oriented SW development for embedded systems

High level VLSI synthesis

Efficient mapping of complex system algorithms on dedicated VLSI architectures

New computer arithmetic algorithms

Interactive microcontroller programming

Appliedmicroelectronics

Realtimeprocessing systems

Embeddedsoftwaretechnology

Field buses

Object oriented realtime programming with hard realtime constraints

Embedded computers

Dependability of distributed systems



Reference projectsReference projects (I) (I)

� Microelectronic systems solutions using field programmableand application specific integrated circuits

� Very Large Scale Integrated Electronics for the first commercial artificial liver� User specific microcontrollers (RISC4, RUN4) and Java processors� Realtime colour image processor� 650 MHz programmable frequency divider @ 3,3 V in 0.35 micron CMOS

� realtime scheduling coprocessor� Intellectual Property Cores for DSP und cryptography

� i.e. CORDIC, DES, RUN4 4b microcontroller



Reference projectsReference projects (II) (II)

� Hardware oriented software development and embeddedsystems

� Java Virtual Machine (JVM) for 8051 and smartcards� FLEXS: Cross-Development for microcontrollers with in-circuit-emulation

capabilities� MEDIAS: Distributed networked multimedia education system



ReferenceReference projectsprojects (III) (III)

� Realtime systems

� EVASCAN: Tool for specification, development support, rapid prototyping,and evaluation of complex realtime systems

� Improved scheduling algorithms

� OPC (open process control) for embedded systems



Current researchCurrent research

� Communication� RF, wireless

� CMOS - high frequency applications

in the RF domain

� Mobile, portable systems, battery powered

� design for lowest power consumption on all levels of chip design

� Embedded internet, cryptography, spontaneous networking

� Embedded realtime systems



VLSIVLSI system servicessystem services

� Design of digital systems from concept to algorithm,architecure, and circuit design

� Goals: Short development time, full verification, moderndevelopment tools and design flow, target technology ASICor FPGA

� Available tools and CAD� Design-Entry: VHDL, Schematic� Simulation and synthesis: Synopsys� Technology mapping: XILINX (FPGA), Cadence (ASIC)� Realtime Rapid Prototyping: Aptix MP3C up to 4 Mio. gates

� Multi-FPGA partitioning: PL-Architect

� Our services in the DASP-project� Standard DASP HW realization in ASIC or FPGA, offering DASP IP-cores� Providing CAD support for customer designs� Rapid prototyping and microelectronic prototyping of customer DASP designs



Requirements of D(A)SP HW designRequirements of D(A)SP HW design

� Embedding DASP functionality in IP-cores� Full verification� Complete design flow� Rapid prototyping



DesignDesign complexity complexity

� „Design gap“� System complexity is growing

faster than designersproductivity

�� Improved CAD, Reuse ofcomponents(Design Re-Use, IP)

1

10

100

1.000

10.000

100.000

1.000.000

10.000.000

1981 2009Ja hr

in T

au

sen

d

10

100

1.000

10.000

100.000

1.000.000Logiktrans./Chip

Trans./PM

58%/

Ja hr

21%/

Ja hr



IPIP libraries libraries

� Separation of function andcommunication

Source: UC Berkeley



IPIP**--CoresCores

� „Systems on Chip“ feasible by reusing existent and fullyproved components (cores)

� Hard Core: Fixed layout for a given technology(bullet proof function but not flexible)

� Soft Core: Synthesizable model in a given hardwaredescription language(flexible but will it do what you want ?)

� Interface standards are necessary

� Examples: RUN4, DES, CORDIC, scheduling coprocessor

*)*) IP - IP - Intellectual PropertyIntellectual Property



VerificationVerification� Complex simulations result in ever

increasing verification time� Example:

� Realtime is 50 MHz, 1 instruction /clock cycle

� Simulation time of machineinstructions of a µP in RTL-VHDL oncommon workstations:about 50 instr. / s = 50 Hz simulationrate

� 1 minute realtime = 1,9 yearssimulation time

verification

design & implementation

other

48%

� Approach: verification using reconfigurable HW,about 10 MHz „simulation“ frequency= 5 min.simulation only



SystemSystemdesigndesign

System specification

HW/SWpartitioning

Hardware Software

Existingcomponents

New HWdevelopment

RAM

System integration

I/O µP...ASIC FPGA

SW integration

Existingcomponents

New SWdevelopment

HW integration

PCB R a p i d S y s t e m P r o t o t y p i n g

Emulation



HardwareHardwaredesigndesign

Design-Compiler(Synopsys)

FPGA Place&Route(XILINX / Actel)

ASIC layout(Cadence)

FPGA ASIC

Simulation(Synopsys etc.)

Back annotation

designgoalsmet?

go onchangedesign

y n

BehavioralCompiler(Synopsys)

Protocol Compiler(Synopsys)

COSSAP(Synopsys)

Hardware speci f icat ion

Behavioral VHDL

RTL-VHDL + .db RTL-VHDL

Testbenches

Schematic Entry(XILINX/Cadence)

Gate-level netlist

Bit File Layout File

Multi-FPGAPartition.

(PL-Architect)

RTL-VHDL + Timing

ASIC/FPGA Emulat.(Aptix)

IP Soft-Cores

IP Hard-Cores

Smartmodels

Code



HW/SWHW/SWRapidRapidSystemSystemPrototypingPrototyping

ASIC and System - Em ulation / M ulti-FPGA Partition ing

Top netlist FPGAnetlist

Hierarchical multi-FPGApartitioning(PL-Architect)

Gate-level netlist

FPGAPlace&Route

(Xilinx/Actel)

System em ulation / rapid prototyping / ASIC em ulation

FPGAInterconnectchip

FPGAnetlist

FPGAPlace&Route

(Xilinx/Actel)

FPGA

FPGAnetlist

FPGAPlace&Route

(Xilinx/Actel)

FPGAExistingHW

System PCB

FPGA ASICExisting

HW

Code



HW/SW - Rapid HW/SW - Rapid PrototypingPrototyping



Reconfigurable systemReconfigurable system



Prototyping, 4 Prototyping, 4 MioMio . . Gates,Gates, 30 MHz 30 MHz



Example projectsExample projects

� Best results need improvements on all levels ofdesign� Algorithms see CORDIC� Architectures see CORDIC� Mapping of architecture to technology see TSPC� Circuit design to fully exploit the technology chosen see TSPC



CORDIC: CORDIC: algorithmalgorithm

� Idea: 2-dimensional vector rotation by iterations

� �

� �

1...,,1,0

2

2

,1

,1

,1

��

��

��

�

�

�

�

�

Nizz

xyy

ymxx

imiii

iimS

iii

iimS

iii

��

�

�

�m,i

�i = ��sign(zi) for zi � 0 (i.e. rotation)-sign(xi yi) for yi � 0 (i.e. vectoring).

zn � 0 (rotation) yn � 0 (vectoring)

m = -1 xn = k-1(x0cosh(z0)+y0sinh(z0))

yn= k-1(x0cosh(z0)+y0sinh(z0))

xn = k-1 x20 - y

20

zn = z0+tanh-1(y0/x0)

m = 0 xn = x0yn = x0 z0 + y0

xn = x0zn = z0 + y0 / x0

m = 1 xn = k1 (x0 cos(z0)-y0 sin(z0))

yn= k1 (y0 cos(z0)+x0 sin(z0))

xn = k1 x20 + y

20

zn = z0+tan-1 (y0/x0)

� Result: universal arithmetic method for DSP

=

��tanh-1(2-S(-1,i))for m=-1

tan-1(2-S(1,i)) for m=1

2-S(0,i) for m=0



CORDIC: CORDIC: behaviorbehavior

� High throughput independent of wordlength nwhen using redundant arithmetic in a fullypipelined architecture

� However, verycostly chip area ~3n2

i�

NYNX

0Y0X 0Z

adde rs andregis ters

NZ

niterations



CORDIC CORDIC arithmetic corearithmetic core

� Extremely fast usingredundant algorithm

� 50%less area due to newalgorithm & architecture

� Availability: Soft Core in VHDL Hard Core for XILINX FPGA

� Performance for Virtex 1000-5: 66 MHz / external 15 Bit 36% of CLBs used no optimized mapping to XILINX technology !

i�

NYNX

0Y0X 0Z

( registers only,no adders )



CORDIC CORDIC arithmetic corearithmetic core : : comparisoncomparison

NewNew architecture architecture

PreviouslyPreviously best best architecture architecture



TrueTrue Single Phase Single Phase Clock Clock vsvs.. StaticStatic CMOS CMOS

A

BD

Q��

��

��

��

+ Lower latency time �� increased throughput Less transistorsonly one clock wire to routeIntegration of logic and pipeline registersIdeally suited for pipelined systems, i.e. DSP

- Dynamic circuit technique�� f > f min�� sensitive to technology and parasitics

No advantage in circuits with great combinatorical depth No standard cell library available �� develop your own library

�� Integrating TSPC logic into standard design flow



TSPC-TSPC-DesignflowDesignflow

MPR =MicroPipelineReorganizer



TSPCTSPC potentials potentials

0

100

200

300400

500

600

700

0,20,40,60,81

Technologie [µm]T

aktfr

eque

nz [M

Hz]

Pentium

Alpha

Fully static logic

Dynamic TSPC logic

� Our test circuits: 650 MHz frequ. divider, 0.35 µm, 3.3 V

� Commercial application: µP



TSPCTSPC weaknessweakness

Clock systemsimulation of theAlpha processor

Diagram ofrelative clockskew in ps

[Quelle: DEC]



Need more informationNeed more information ? ?

� Ask for info package (CD and brochure, german only)

� Internet: www-md.e-technik.uni-rostock.de

� Direct contact

� Office phone +49 (0)381 498 -3529, fax -3601

� Prof. Timmermann Email [email protected]

� Prof. Pfüller Email [email protected]



SeeSee you you in in WarnemuendeWarnemuende ! !

Location of Institute MD

Documents

DASP hardware design: Outline Microelectronic ... · PDF fileMicroelectronic systems solutions using field programmable and application specific integrated circuits ... Example projects