DARPA’S Microsystems Technology Office

DARPA’SMicrosystems Technology Office

DARPA’SMicrosystems Technology Office

An Overview

Approved for Public Release, Unlimited Distribution case #4892

Dr. Robert ReussFormer Pgm Mgr

Reuss BioReuss Bio

• DARPA Program Manager from 2001 to 2006.

• Responsible for research in large area electronics and organic photovoltaics, as well as conventional microelectronics device and design efforts.

• Twenty years in technology and research management positions with Motorola with focus on development of materials/processes fo r electronic components

• U.S. government as a research and development manag er for seven years

Approved for Public Release, Unlimited Distribution case #4892 Page 2

• Research Faculty member at the University of Colora do for three years.

• Ph.D. in Chemistry from Drexel University in 1971.

• Elected to Motorola’s Science Advisory Board

• Member of the Electrochemical Society, Materials Re search Society, Society for Information Display, IEEE

• Published over 50 papers and awarded 13 U.S. patent s.

• Interests lie in the area of application of materia ls and electrochemistry technologies for advanced microelectronic applicati ons and microsystems integration as well as large area electronics.

OverviewOverview

• DARPA Overview• DARPA New Start Process• MTO Overview

Caveat: Information is the Opinion of the author an d is not official DoD position

3

• MTO Overview• Examples of MTO Programs

– Cmpd Semiconductors, MEMS, High Power– Low Cost, ULP & Reconfigurable Logic– Macroelectronic Form Factor

• Summary

Who Do We Work For?

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The DARPA Mission

• Solve National-level problems • Enable Operational Dominance• High -Risk, High -Payoff

Technical Innovation in Support of National Securit yTechnical Innovation in Support of National Securit yPrevent Technological SurprisePrevent Technological Surprise

5

• High -Risk, High -Payoff Technology Development and Exploitation

Approved for Public Release, Distribution Unlimited

Global Hawk

MEMSTMR

UCAV

20002000

Vela HotelSaturn

GroundSurveillance Radar

ATACMS

19601960

19701970

DARPA Accomplishments

6

Taurus LaunchVehicle

MALD

Predator

Uncooled IR

BAT

JSF

19901990

M-16 Rifle JSTARS

ArpanetStealth Fighter

Sea Shadow

19801980

GPS

Ideas to ProgramsIdeas to Programs

7

What Makes a DARPA PMWhat Makes a DARPA PM

• Idea Generator• Technical Expert• Entrepreneur (quasi VC)• Passion for Drive Leading Edge Technology• National Service

8

• National Service

DARPA Hires Program Managers for their Program Idea s

… if you have interest, formulate your program ideas along the lines of the following charts and contact the Office Director

Review:A good program plan should answer

the questions below

Review:A good program plan should answer

the questions below

PRIMARY• What are you trying to accomplish? KISS!• How is it done now, and with what limitations? Challenges!• What is truly new in your approach which will remov e current

limitations and improve performance? How much will performance improve? 10X better; DARPA-hard

Heilmier’s Catechism

9

• If successful, what difference will it make? IMPACT• What are the mid-term, final exams or full scale ap plications

required to prove your hypothesis? When will they b e done?• Metrics & Capabilities driven, not knowledge driven (NSF, XORs)• May address system or component level advances

SECONDARY • How could this transition to the end user? (usually DoD) • How much will it cost? Programs funded via BAA or seedling. But, not requi rements driven.

Develop solutions that DOD does not yet know that i t needs.

E-3 AWACSAirborne Early Warning

FLTSAT

Secure Comm:

Low power, high fidelity,

reconfigurable transceiversSpace Based RADAR

Ultra stable clock, LO, low power electronics

RC-135V Rivet JointUltra Broadband receivers

Tier II+ UAVGlobal Hawk

Space-Time Adaptive Processing:

Complex mission specific circuits

SIGINTE-2C Hawkeye

GMTI, SAR, STAP, HISRadiation hard electronics;Broadband, high efficiency

sensors

Microsystems Components Driving Platform Innovation

Microsystems Components Driving Platform Innovation

10

Aegis Cruiser

StandardMissile

rf/IR seeker

Small Unit OperationsMobile power sources

Towed Sonar Array

Complex mission specific circuits

and algorithms

Covert sensing

Power constrained operations:

Adaptable

Low Power Sensors

Shipboard Radar

High power, high efficiency amplifiers

Chemical biological

threat detection;

High PD, low PDFA

sensors

Cooperative engagement:

High dynamic range rf links


Responding to Changing ThreatsResponding to Changing Threats

Integrated Microsytems driving platform capability for the

Integrated Microsytems driving platform capability for the

11

platform capability for the warfighter

platform capability for the warfighter

Integrated Microsystem Integrated Microsystem

12Approved for Public Release, Distribution Unlimited

Five Frontiers of Integrated Microsystem

Five Frontiers of Integrated Microsystem

Electronics

13

MEMS/NEMS

Photonics

Electronics


Develop, demonstrate and transition the key solid s tate technologies that enable dominant system concepts a nd capabilities for the Department of Defense

Pushing the limits of scaling and integration

Microsystems for spectral exploitation and sensor dominance

DARPA/MTO MissionDARPA/MTO Mission

14

Systems that intelligently interact with the environment

Tools that enable scaleable and affordable access to leading edge components

DoD Access to Winning Microsystem Technology

Classes of MicrosystemsClasses of Microsystems

• Intelligent: High level of autonomy with the ability to reason and learn with time

• Adaptable: Some degree of autonomy to self optimize, test, or monitor. Able to change mode of operation.

Incr

easi

ng C

apab

ility

Incr

easi

ng C

apab

ility

15

• Reconfigurable: Predefined, deterministic set of operating parameters that can be selected externally.

• Static: Fabricated to design specifications with fixed performance.

Incr

easi

ng C

apab

ility

Incr

easi

ng C

apab

ility

Wide Bandgap MaterialsWide Bandgap Materials

A new class of solid state power switching transistors employing SiC

• 75 mm diameter conducting, low defect, SiC substrates

• 15 KV and 50A power bipolar switches • 50 kHz high power switching and prototype

circuits

– High Power Electronics

A Novel SiCPower Switch Capable of 10kV-100A

(Sharon Beermann-Curtin)

16

of 10kV-100A

RF applications and capabilities GaN. • High power (> 1KW/cm2) electronic

integration assemblies

- RF/Microwave/Millimeter-wave Technology

Clockwise from top-right: X-band T/R Module, Q-band SSPA, Wideband HPA

MEMSMEMS

Micromechanical devices able to operate under adverse conditions:

• Large temperature fluctuations

• High power throughputs• High G-forges• Corrosive substances

HERMIT(Harsh Environment Robust

Micromechanical Technology)

Package Substrate With Seal Ring and RF Lines

(Amit Lal)

17

Titanium MEMS Mirror Array for Harsh Environments

Examples of RF MEMS in Development Under This Program

RF MIP(RF MEMS Improvement Program)

Improve the value of RF MEMS for DoD applications

• Extended lifetimes• More inexpensive packaging

techniques • Enhanced RF Performance

Micro - Power and CoolingMicro - Power and Cooling

MPG(Micro Power Generation)

Generating power at the micro scale to enable standalone micro sensors and actuators with wireless communication functions.

• Better than 10X energy density over current batteries

• Fuel processing• Energy conversion to electricity• Thermal and exhaust management

(Sharon Beermann-Curtin)

18

Microscale cryogenic coolers with minimal power requirements for targeted device cooling to increase performance and sensitivity of electronics, sensors, etc.

• Thermal and exhaust management

Clockwise from top: Rotor and housing for MEMS engine, Swiss roll heat exchanger for fuel cell, Piezoelectric membrane generator

Notional design of micro cryostat based on optical cooling

MCC(Micro Cryogenic Cooling)

Dennis Polla

DOD Electronics ResearchScaling and Density Challenges

DOD Electronics ResearchScaling and Density Challenges

• Dealing with variation & (soon) high defect rates

• Alternatives to lithography based fabrication

• Interfaces for hybrid technology

19

• Interfaces for hybrid technology

• EDA tools

• Reconfigurability to offset design & fabrication co st

Industry CollaborationIndustry Collaboration

20

Exploiting the 3 rd DimensionExploiting the 3 rd Dimension

--- Sensor Array

--- Interconnect & Cooling

--- Logic


--- Memory


--- RF Circuits


--- Power Scavenger / Storage


Vertically Interconnected

21

3D Micro-ElectromagneticRF Systems (3D-MERFS)

(John Evans)

Active layer

Dense FET layer

Interposer layer

Active layer

Aperture layer

Interposer layer

Motherboard layer

Passive 3-D RF matching networks

Embedded cooling

Switch network

Hard-Wired Interconnects

DD

AA AA RR

D D RR AA DD A A

DDDDRR AA RR

DDR R

Scalable Microsystems for Affordable Reconfigurable

Transceivers (SMART)(Mark Rosker)

3D Electronics(Dan Radack)

InterconnectsArchitecture

Vertically Interconnected Sensor Arrays (VISA)

(Ray Balcerek)

Why Does DARPA Need to Worry?Grand Challenge # 1


22



23

Exploiting Commercial TechnologyExploiting Commercial Technology

24

TEAM Key DemonstrationsTEAM Key Demonstrations

DoD Applications forEW, Radar, and SatCom

Not shown

25

Advanced Electronics SWaP PayoffAdvanced Electronics SWaP Payoff

26

Design Costs Outpacing Fab

Increases

• Masks sets -> $1M

Source: IC Insights, 1/2003

27

Hardware Design Cost

Software Design Cost

• Masks sets -> $1M• Design costs -> $60M

Technology development needs to focus on reducing design costs –new DARPA program!

Source: IBS, Analysis of the Relationship Between EDA Expenditures and

Competitive Positioning of IC Vendors


Moore’s Law is not the Problem (or is the problem!)

Moore’s Law is not the Problem (or is the problem!)Lo

g S

cale

950K

1,500K

2,400K

3,800K

6,100KGates/cm 2

Moore’s Law(59% CAGR)

9,700K

Productivity Gap

Fabricable

Designable

28

We can fabricate it, we just can’t design it!• Gap growing between best-possible custom chip and a chieved performance• 10-100x now, 1-3,000x for end-of-the-roadmap CMOS

500nm1995

350nm1996

250nm1997

200nm1998

150nm1999

130nm2001

[ Source: Sematech, Gartner Dataquest, VLSI Technology, Xilinx ]

90nm2003

125K160K

200K250K

300K375K600K

950K

Average Cell-basedDesign Start(25% CAGR)

475K

Designable


Signal Processing OptionsSignal Processing Options

29

Mission Specific Processing (MSP)Mission Specific Processing (MSP)

•Program Objective:• Performance of custom design in an affordable

standard cell ASIC flow to significantly improve complex chip performance for military signal processing missions and positive impact on design time.

• Goals:• 10x improvement in power-delay-area over

comparable standard cell design.• Demonstrate

beneficial custom techniques that are

10x

102x

103x

104x

DSP

FPGAASIC (std cell)

Per

form

ance

(G

ops/

Wat

t)

Custom

Complex, 50M Transistor Chip Design Completed

Chip design run at IBM fab.

– beneficial custom techniques that are compatible with traditional synthesized ASIC design flow.

– Improved design flow for incorporating high performance mission optimized cells.

– Insertion of MSP advances in processor testbed for mini-radar applications.

• Develop and make available to the DoD community, a comprehensive, highly optimized, ASIC cell library of key, militarily significant, kernel functions.

• Advantages via publication/presentations.• Transfer Real-time Test Bed, Radar Simulator,

and Design Methodology to AFRL.

1x

1x 10x 102x 103x 104xRelative Time

DSP

GPP

Per

form

ance

(G

ops/

Wat

t)

MSP Exceeds 20X PDA ProductMSP Exceeds 20X PDA Product

DSP DSP

Control

Sensor ASIC WITHOUT MSP Sensor ASIC WITH MSP

Control

MSPMSP

31

POWER-DELAY-AREA Product 21.7X BETTER

Boeing Sensor ASIC(200 GOPS/Watt)

Equivalent Array of 120 Tiger SHARC DSPs (<0.4 GOPS/Watt)

VS.


Clockless Logic, Analysis, Synthesis and Systems (CLASS)

Clockless Logic, Analysis, Synthesis and Systems (CLASS)

102x

103x

104x

FPGAASIC

Custom

Per

form

ance

(G

ops/

Wat

t)

CLASS goal: Reduce ASIC design time. � Program Goals:- Demonstrate cost and performance

advantages of asynchronous/clockless design

- Overcome inertia and enable automated design of async ICs

- Make clockless design available ASAP to DoD.

• Technical Challenges:

1x

10x

1x 10x 102x 103x 104xDevelopment Cost

DSP

GPP

FPGA

Per

form

ance

(G

ops/

Wat

t)

• Technical Challenges:– Develop and validate tools and

methods for design and fabrication of highly complex asynchronous system-on-a chip capability well beyond today’s synchronous designs.

– Demonstrate the advantages of clockless design in terms of design effort, improved energy utilization, reduced EMI and tolerance to voltage and process variation.

– Provide a true “apples-to-apples” comparison of a clocked versus clockless large integrated circuit in silicon.

10X Design Cost Reduction with Automated Clockless Tools

Why Clockless?

Clockless technology will enable very complex SoC d esigns by overcoming approaching limits of clocked design

� Timing Closure� Noise/EMI� IP Reuse

� Power Management � Limited Available EDA Tools� Device Variation

• Multi-rate behaviorCircuits are data driven not clock driven. Local handshaking.

• Low Noise and Low EMI

33

• Low Noise and Low EMIThe lack of synchronized switching spreads the demand on the power rails over the frequency spectrum

• Power ManagementThe circuits are data driven and only consume power when doing useful workMatch power supply to required data rateLow latency recovery from sleep mode

• Delay InsensitiveAgility and reconfigurability enabled with no timing closure issues to break the functionalityHigher levels of integration by simple accretionDesigns easily ported to new materials and run at the speed enabled by the new technology


CLASS Program: Military Impact of Benefits of Clockless Technology

Clockless Low Noise= Higher Accuracy

Clockless Low Power

Clockless Design= Lower power= Low noise/EMI= Low latency= Data Driven= Multi-Rate

Clockless Low Noise/EMI

= Easier integration= Lower Bit Error Rate= Lower power

Enabling Future DoD MissionEnabling Future DoD Mission--Critical DeeplyCritical Deeply--Integrated SoCIntegrated SoC

Clockless Low Power/ Multi-Rate

= Lower power or faster= More secure

Clockless Data Driven/Multi-Rate

= Efficient Single/Multi-Port Architecture

Clockless Low Power and Data Driven

= More efficient use of available energy

= Lower current spikes

Clockless Design= 2-4X Longer Battery Life= 10X Lower EMI= Higher Performance= Reduced Cost/Time to Market

Embedded Configurable High Performance Processing of Signals (ECHiPPS)

Embedded Configurable High Performance Processing of Signals (ECHiPPS)

10.0

100

1000

Per

form

ance

(G

OP

/SE

C/W

att)

ASICs

Std CellFull Custom

ECHiPPS Goals:• Advantages of reconfigurability

� Design-time flexibility� In mission reconfiguration� Greater efficiency of on-chip

resources

ECHiPPS Technology

Accomplishments (reflected in image)

0 3 6 9 12 15 180.10

1.00

Development Time (months)

Per

form

ance

(G

OP

/SE

C/W

att)

mProcessors

Programmable LogicFPGAs/CPLDs

resources• Low power , high performance

efficiency, close to ASICs

Revolutionary multi-core chip design and programming environment

HyperX Compared with Current Signal FPGA/DSP Processing Technology

HyperX Compared with Current Signal FPGA/DSP Processing Technology

Energy (pJ) per Mathematical OP [for FIR and FFT fu nctions](all data memory movement encompassed in an OP)

9,22310,000

100,000

• 10x better computational efficiency• 100x better energy efficiency

HyperX Comparison with Current Signal FPGA/DSP Processing TechnologyE

nerg

y (p

J) p

er O

p (F

IR a

nd F

FT

)

Energy Per Mathematical OP for FIR and FFT Kernels

11

310 322 343477

1

10

100

1,000

Hyper64 (90nm) C64X+ (90nm) Blackfin (90nm) Stratix II (90nm) Virtex-4 (90nm) P4 (90nm)

HyperX

Ene

rgy

(pJ)

per

Op

(FIR

and

FF

T)

OFW Helmet Sensors Image Processing Functions and Requirements **

Task Memory Requirements

Processing Requirements

Video compression: 2 displays of 1280x1024, 60Hz

2x64 Mbit 2x 40 GOPS

Aided Target Detection: 640x480 8 bit gray

3.4 MB 110 MOPS

Camouflage Detection: 10 targets max, 640x480

2MB 28 MOPS (plus scene change

37**Prepared by DRS Optronics, Inc.

A compact, lightweight and very low power (< ¼ W) processor technology is required that offers 100’s of GFLOPs of processing capability to enable incorporation of the necessary processing functionality into the OFW Helmet or into a belt-mounted computer.

10 targets max, 640x480 8-bit gray

scene change detection)

Booby Trap Detection: 640x480 8 bit gray

2MB 110 MOPS

Image Registration and Fusion: 640-480, 8 bit gray

180MB 6 GOPS

Total Processing (assuming 4 sensors and video compression implemented in hardware)

92 GOPS


ImpactWhy HyperX = Revolutionary Performance

ImpactWhy HyperX = Revolutionary Performance

Versus FPGA Technology: �10x Computational Efficiency

(computational efficiency =time to process algorithm)

�100x Energy Efficiency(energy efficiency = power * processing

time)SAR- ATR Missile Platform

Required Electronics not currently realizable in a field systemtime)

ImplementationPeak Power(W)

Efficiency(msec per image)

Energy Efficiency(W*sec)

HyperX .96 4.38 .00420

Actual SAR platform (30 PowerPCs) 141 2000 282

PowerPC platform matching HyperX throughput (128 PowerPCs)

601.6 4.894 2.94423

realizable in a field systemSignal and Image Processing (SIP) Algorithms Includes

– FFT, Convolution & FIR, Scalar Multiplication, Translation & Rotation, Matrix Multiplication Gaussian Elimination

PROCESSING ALGORITHMS WITH CO-DESIGN OF ELECTRONICS (PACE)

PROCESSING ALGORITHMS WITH CO-DESIGN OF ELECTRONICS (PACE)

PROGRAM DESCRIPTION� Methodology/tools for rapid development of customized on-

chip signal processing algorithms for demanding military applications on multiple hardware fabrics simultaneously.

� Realistic power/performance estimates for simultaneous co-optimizing both algorithm and hardware resources.

� FPGA-based TeraOp/sec prototyping platform for real-time exploration of algorithms and system-level verification of complex digital and RF chips.

� Automated design flow for “chip in a day” generation of variety of custom IC solutions.

algorithm 1

algorithm 2

algorithm 3

algorithm 4

algorithm 5

algorithm 6

1 Algorithm Definition

ASIC Micro Architecture

Design/Synthesis

Physical Design

Algorithm Exploration

Place and Route

Algorithm Design Entry

HDL Translation

Synthesis

Simulation

After PACE:

PACE

Before PACE: 12 months, 1 algorithm

TECHNICAL DETAILS

�Dedicated hardware-based, real-time, EMULATION (not SW simulation) platform for 1000X faster, accurate implementation, search and verification of design space with optimized design provided for direct IC implementation.

�HW-aware design method allows algorithm performance to be rapidly evaluated on multiple platforms to yield optimum combination of algorithm and HW.

�Single system-level description for multiple HW implementations which improves design efficiency reliability and testability.

PAYOFF

�PACE reduces algorithm and hardware exploration from months or years to weeks with emphasis on optimal utilization of COTS where feasible .

�PACE allows economical and timely access to the most advanced System-on-Chip solutions specifically for DoD signal processing needs.

�Prototype systems developed as design drivers relevant to DoD needs.

� Close coupling with DoD for requirements, specification and tech transfer.

After PACE: 1 week many algorithms

PerspectivesPerspectives

• information acquisition is central to most modern military electronic systems, including sensor networks

• acquisition is increasingly the engineering bottleneck

• growing body of research on the role of DSP in • growing body of research on the role of DSP in addressing the bottleneck; underlying circuits taken as given

• focus should be on acquisition architecture as a whole (RF/ADC/DSP) with a total-system view

• intelligent analog/digital co-design, exploiting technology advances and scaling characteristics

• requires broader view of signal processing

Ultimate GoalsUltimate Goals

• develop and evaluate alternative information acquisition architectures

• emphasis on enabling algorithms that take into account underlying circuit into account underlying circuit technologies

• approach via case study method; ultimately distill into suite of broader competitive architectures

• identify best vehicle for proof of concept demonstration

Energy Starved Electronics: Wide Dynamic Range in Energy Consumption and

Performance

Energy Starved Electronics: Wide Dynamic Range in Energy Consumption and

Performance

−6

10−4

10−2

100

Nor

mal

ized

I D

Subthreshold Operation: Low performance, minimumenergy, long operation life

Normal Operation, Strong Inversion : fast, high-energy, high performance

Unite the regions

From EETimes Feb. 2005“A paper from MIT may introduce a whole new metric: lowest operating voltage. By aggressive use of voltage-frequency scaling, subthreshold circuit operation and supply voltage dithering, the team was able to keep an adder circuit operating over the full range from 1.1 V to under 300 mV. This appears to be the lowest reported operating voltage for a digital circuit at the conference.”

42

Requirements for SuccessfulUltra Low-voltage Operation:• Architectures, circuits and devices to reduce power consumption by >100X yet mitigate throughput loss in deep sub-threshold operation• Reliable operation with highly variable device components• Wide-dynamic voltage range capability to allow high performance operation when needed

0 0.2 0.4 0.6 0.8 110

−8

10−6

Normalized VGS

conference.”

1 E -1 1 1 E -1 0 1 E -9

1 E -7

1 E -6

1 E -5

1 E -4

1 E -3

Tot

al P

ower

(W

)

D e la y (se c )

Vdd = 1.0V

30x delay penalty

300x powersavings

2.2µWVdd = 0.3V

700µW


VLSI ApplicationsVLSI Applications

PO

WE

RUltralow power applications: medical, space, specific sensor network etc.

Portable

General purpose computing: internet server, database server, real-time jobs etc.

• Different applications have different power-perform ance demands• Scaling affects all applications in different ways

PERFORMANCE

Portable applications: mobile computing, wireless, multimedia etc .

Power Reduction with Sub-threshold Operation Optimization

Power Reduction with Sub-threshold Operation Optimization

Power

Sub-threshold

Operation

Device

Power Ceiling

Ultra Dynamic Voltage Scaling

Conventionaloperation

44

Dev/Ckt/Arch Optimization is needed to achieve target throughput using sub -threshold logic

Throughput

Device Optimization

Circuit/Architecture Optimization

Duty Cycle & Sizing

Parallelism


Achieving Ultra-Low PowerAchieving Ultra-Low Power

Logic and Library Parallelism for Performance • Build a custom

standard cell library to address issues specific to sub-Vtoperation such as device variation.

• Sizing transistors in each cell considering energy and variation

• Digital Backend of high performance mixed signal circuits needs to operate with a fixed input of 500 MSPS.

• Voltage scaling results in an energy reduction of 86% but [parallelism is required to maintain throughput at the minimum energy point.

• Circuit techniques are being developed to overcome issues from clock skew and jitter, as well as analyzing the effect of parallelism

BLB

RWL

RBLWLBL

VVDD

New sub-V t bitcell

Dynamic Power Monitoring

0.3

0.8

1.3

1.8

2.3

2.8

0.2 0.3 0.4 0.5

Ene

rgy/

Ope

ratio

n (p

J)

N=1N=2N=5N=10

• Min energy is function of data workload.

• 2.2X improvement in energy consumed can be obtained by dynamically tracking the min

as well as analyzing the effect of parallelism on matching and thermal noise.

Error Resilient Architectures.• Algorithm-Based Fault Tolerance to detect and correct “soft” errors in sub-Vtcircuits

• Reduce frequency and re-compute if error occurs

FDSOI Energy Starved Electronic Devices

FDSOI Energy Starved Electronic Devices

Need Transistor Region of Operation

1.E-12

1.E-10

1.E-08

1.E-06

1.E-04

1.E-02

Dra

in C

urre

nt (

A)

SubthresholdRegion

Strong InversionRegion

W/L = 8µµµµm/180 nm, n-channel CMOS, V DS=50mV

FastPower Hungry

Weak InversionRegion

SlowerPower Savings

SlowMinimum Energy Operation

Vth

BULK

FDSOI

• Future battle field proliferated with unattended se nsors– Ground, aerial, networked, isolated– Provides force multiplication

• Requirements for the electronics in these sensors– Long endurance, Lightweight(minimal batteries), Inexpensive– Significant digital logic for multiple functions

• COTS solutions not targeted for energy efficiency– ITRS driven by performance, not efficiency– Utilize “strong inversion” process technologies

• Lower power solutions are possible– Develop processes , circuits and architectures for ultra-low power subthreshold device operation

• FDSOI is enabler to reduce power, maximize performa nce beyond

46

Goals / Approach

Highest Clock Frequency Possible

HighPerformance

CircuitsLow PowerCircuits

Subthreshold Operation

Strong Inversion Operation

SubthresholdCircuits

100KHz 1MHz 10MHz 100MHz 1GHz 10GHz

Ene

rgy/

Ope

ratio

n (p

J) 1E-4

1E-5

1E-6

1E-7

1E-8

1E-9

1E-3

kT (Room Temperature)

1.E-120 0.5 1 1.5

Gate Voltage (V)

• FDSOI is enabler to reduce power, maximize performa nce beyond capability of any other technology

• FDSOI fabrication process tuned for subthreshold o peration– Device structure/capacitances optimized sub-Vth

– nmos/pmos transistor off-current equalized• Circuits and Libraries optimized for subthreshold o peration

– Digital logic blocks– Memory– Mixed-signal circuits

• Architectures for ultra-low power (ULP)– Clever low voltage algorithms to maximize data reduction– Parallelization to reduce clock speed / dynamic clock– Robust circuits to minimize effects of process variation

• Use Continuous Video Sensor application as technolo gy driver


Power Reduction Opportunities for Continuous Video Sensor

Power Reduction Opportunities for Continuous Video Sensor

Video Sensor (Camera + Comm Module) Links to UAV

Exfiltration Platform

Camera Data Compression

RFFEC &

Camera module

Comm module10

20

15

25

GenerationThinningCompressionCamera ClockTransfer/StoragePacketize/CodeModulationAmplification

Results of a Detailed System Study to Assess Technology Opportunities and System Payoff

Ene

rgy

/ Sou

rce

Bit

(nJ)

47

RFModule

FEC &Control

Comm module

• Unattended imager scenario• 3 frames / sec

• 1 Mpixel / frame (1024x1024)• 10 bits / pixel

– 100:1 data thinning• 3 frames / event• 100 events / hour• 33% of pixels active / event

– 5:1 JPEG compression• Uplink scenario (3 times per day)

– 330 Mbytes / 8 hours

• Link parameters– 15 GHz carrier frequency– 100 km range– 8-ary FSK (non-orthogonal) – 10 Mbps burst rate– Turbocoding

0

5

COTS Standard ASIC

ULP Technology

Technology FPGAs, avail. MMICs

Standard cell designs

Subthreshold process/design

Lifetime* 6 days 35 days 130 days

* 100 W-hr battery

Ultra-low power technology will enable surveillance of 260,000 images / day for over 4 months!

Ene

rgy

/ Sou

rce

Bit

(nJ)


Ultra-Low -Voltage MSP430Ultra-Low -Voltage MSP430

Problem• Increased circuit variability at low VDDGoal• Demonstrate ULV MSP430

microcontroller in 65nm CMOS

Results• Verified functionality down to 300mV• 10x lower energy compared to

commercial MSP430• Winner of ISSCC 2008 Jack Kilby

Award for Outstanding Student PaperDC-DC

converterCore logic

102

103

Ene

rgy/

cloc

k cy

cle

(pJ)

75°C

25°C 27.2pJue

n

er

dd

r

trl

Technical Approach• Variation-aware cell library and timing

methodology• Sub-Vt 8T SRAM with peripheral circuit

assists• Integrated DC-DC converter with high

efficiency while supplying microwatts

128Kb SRAM array

0.3 0.4 0.5 0.610

1

10

VDD

(V)

Ene

rgy/

cloc

k cy

cle

(pJ)

25°C

0°C

Se

qu

-ce

Ad Ct

Da

ta

Ctr

l

JT

AG

Press coverage at ISSCC 08“MIT, TI debut energy-efficient microchip”

Ultra-Dynamic Voltage Scalable (U -DVS) SRAM

Ultra-Dynamic Voltage Scalable (U -DVS) SRAM

• SRAM design for a very large voltage range:

– Low V DD operation – Energy efficient– High V DD operation – High

performance

• Reconfigurable assist circuits :– provide robust operation in sub-

threshold

Measured Performance and Leakage Power

RESULTS

Voltage Range: 0.25V – 1.2V

Performance: 20kHz – 200MHz

Leakage Power Savings: > 50X

Capacity: 64kbit by using dense 8T cells

threshold– turned off at high V DD to prevent

power overheads & performance penalties

64kbit 8T U-DVS SRAM in 65nm

Energy-Area TradeoffEnergy-Area Tradeoff

Energy-Area Tradeoff for Digital Baseband Processor

5

6

7

8

Nor

mal

ized

Bas

eban

d P

roce

ssor

E

nerg

y 6x

0

1

2

3

4

1 10 100 1000

Normalized Baseband Processor Area

Nor

mal

ized

Bas

eban

d P

roce

ssor

E

nerg

y

This Design

6x

10x

Flexible, Printed Electronics Is Flexible, Printed Electronics Is

• More than Moore!– Device/circuit technology not driven by need for sm allest

possible dimensions, but rather cost and/or form fa ctor (Nominal features in > 1-10 um regime)

• Bigger is Better!– Electronics (ideally printed) spread over area/volu me to – Electronics (ideally printed) spread over area/volu me to

conserve space/weight or achieve enhanced functiona lity

• Flexible even Better!– Electronics fabricated on substrate that allows sha ping to

surface or increased ruggedness against mechanical damage (foldable/rollable)


Why Flexible, Printed Electronics?Why Flexible, Printed Electronics?

• Not all systems benefit from scaling– Displays– Sensors– Human I/O

• Microelectronics is not always the best solution• Microelectronics is not always the best solution– Too costly– Too small– Too fragile

• FPE possible solution, but...– Material/device characteristics must be adequate– Manufacturing process must be (much) cheaper– Application and processing must be for large area– Substrate must provide novel form factor (flexible, lightweight)


Comparison of FPE & Microelectronics

100

1000

10

Tran

sist

ors/

cm

2

106

108

Sensor Arrays

Wearable Electronics

Materials & Devices

Achieve

MMIC

Computer Chips

Single Crystal SiliconSubstrate = siliconMobility = 400-1000Ft > 50GHzFeature Size = 0.1umDensity > 107/cm2

Cost = $5-10/cm2

High CostHigh Performance

Transistor Covered Area (cm 2)

.1

1

10

Tran

sist

ors/

cm

10 100 1000 10,000

104

1

Achieve performance

targets

PDA ScreenComputer Screens

Flat Panel TV

Photovoltaic

Amorphous Si TFTsSubstrate = Glass/plasticMobility < 10Feature Size > 1umDensity < 104/cm2

Ft < 50 MHzCost = $0.1-0.25/cm2

Processes & Substrates

Maintain fabrication

cost structure

Low CostLow Performan ce

Flexible Integrated Communications DeviceFlexible Integrated Communications Device

Flexible PV:Some Key Applications

Flexible PV:Some Key Applications

Large Area, DistributedFlexible Electronics Technology

Large Area, DistributedFlexible Electronics Technology

Sensor Actuator Array (RF, light, mechanical)

TFT Active Electronics Layer

Energy Storage Layer

Recharge LayerAPPLICATIONS:adaptive surfaces

Goal• Integrated electronics distributed over large surface are to provide sensor areas that interact/respond to environment.• Reduce weight and cost.• Increase reliability and flexibility. Challenges• Thin film transistors/circuits with adequate mixed signal performance.• Cost effective fabrication methods.• Exemplar applications to drive and focus further development.

56

adaptive surfacessensor arrays

displaysphotovoltaics

distributed diagnostics

TFT devices/process candidates for >100 MHz

operation in development.

Initial application drivers identified.

further development.


“to detect blast eventsthat can cause

traumatic brain injury (TBI)”DARPA funded project

source: MicroVision

PARC Printed Blast Sensor TapePARC Printed Blast Sensor Tape

Pressure, acoustic, acceleration, light, temperature sensor integration

Readout electronics and memory (data storage for 7 days)

Printing/lamination processes for low cost (target ~<$1)

challenges

• light• temperature• pressure wave

accelerationexplosion

disposable blast dosimeter tape


Sentry TapeSentry TapeFallujah Lesson Learned

Over five US battalions to retake the city (with 2 added battalions providing cordon)

Defending force ~3,000

House to house clearing operations– Lengthy, enemy would often re-infiltrate once frien dly

forces moved past (hide sites, tunnels, etc.)

– Limited situational awareness of enemy and/or egres s routes

All current deployable sensor All current deployable sensor systems are large, heavy, and systems are large, heavy, and expensive AND relegated to expensive AND relegated to support operations at Company support operations at Company level and above.level and above.

Courtesy of G Duchak

– Ambush potential high when returning back to area thought cleared

– Manpower intensive to maintain rigorous force protection

– Two to four marines out of a 12-13 Marine squad dedicated to maintaining security of cleared buildi ng or area.

Squad level force protection (intrusion detection) currently done by teams of people

– Manpower intensive

– Squads are usually 13 people or less

– Typically ~4 on watch continuously/(24/7) requireme nt

There are NO lightweight, lowThere are NO lightweight, low--cost, disposable systems that cost, disposable systems that support the warfighter at support the warfighter at Platoon and Squad levelPlatoon and Squad level

Sentry tape isn't about taking the building it’s ab out Sentry tape isn't about taking the building it’s ab out notnottaking the building taking the building twicetwice . How could such a capability be . How could such a capability be

useful in commercial world?useful in commercial world?

Structural and Aero Structural and Aero State SensingState Sensing

Structural and Aero Structural and Aero State SensingState Sensing

• Structural and Aerodynamic State Sensing Enables Self-training– Allows Operation of UAV at

Flight Vehicle Envelope Limit• Controlled Fatigue with Extended

Airframe Life• Provides Load Alleviation from

Damage or Ballistic Impact and Gust Loads

• Simplified Certification Process

The Living Airframe

• Simplified Certification Process– Weapons and Stores

Certification– Reduced Factor of Safety

• Aircraft will learn to “Fly by Feel”

Structural State Monitoring– Strain– Temperature– Impact

Distributed Aero Sensing• Sense Pressure

– Position of Stagnation Point– Chord Surface Pressure

• Sense Flow Shear

T Duenas, NextGen AeronauticsFTA Conference 2010

Electronics Manufacturing for ARDECElectronics Manufacturing for ARDEC

• US electronics parts supply base is diminishing

– Along with parts manufacturing know-how

– Obsolescence • Unique DoD requirements

– Harsh environment

Large Area Electronicsfor Munitions

5/16/2010

DISTRIBUTION STATEMENT EDistribution authorized to DoD components only; Critical Technology, Premature

Dissemination; 16 May 2010. Other requests for this document shall be referred to US

Army ARDEC (AMSRD-AAR-EMB), Picatinny Arsenal, NJ 07806. 60

– Harsh environment– 20 year shelf life– High reliability– Energetics– EMI/EMP/Rad hardening

• Solution– Adapt and enhance new

nanotechnology based manufacturing technology

Electronic Time Fuze

Mortar XM784

(60 mm mortar

shown)

Wearable Electronics

SENSORS/ MEASUREMENTS

Headband EEG and Oximetry

Acoustic(Voice Stress and Content Analysis)

Dead Reckoning Module(3-Axis Accelerometer, GPS,Magnetometer, Altimeter)

3

2

1

Predict

Significant

PHYSIOLOGICALCONSEQUENCES OF CONCERN

Hypothermia

Hyperthermia

Hypoxia

Metabolic Fatigue

Vigilance Lapses

“Tool Kit” to Understand Warfighter Physiology

CURRENT

2

1

4

3

Warfighter Physiological Warfighter Physiological Status MonitoringStatus Monitoring

Magnetometer, Altimeter)

EKG, EMG, andThoracic Impedance Cardiography

Body Core and Skin Temperature

Near-Infrared (or Other) Technology*Tissue pH, Glucose, and Lactate

Wrist-Worn Actigraph

Boot-to-Boot Impedance*

Foot Contact (Weight/Locomotion)

Wireless Inter-Module Communication

9

8

7

6

5

4

10

Significant

Performance

Degradation

and

Impending

Casualty

Vigilance Lapses

Dehydration

Psychological Stress

Inadequate Restorative Sleep

Desynchronization ofCircadian Functions

Jolt, Blast, and RepeatedImpact Exposure

Toxic Substance Exposure

Specifications for Minimal Sensor Setto Predict Warfighter Physiology

FUTURE

* Concept

5

6

9

8

10

8

7

Reed Hoyt, Ph.D.

USARIEM

[email protected]

Smart Medical Tape for Continuous Warfighter Monitoring

Smart Medical Tape for Continuous Warfighter Monitoring

• Medical Tape - Smart Band-Aid, Combat Medical Care , and/or Exposure Monitoring

• Sensor Tape BAA– Provide in situ monitoring– Provides vitals during patient transport– Low-Cost, Flexible, Disposable, Wearable and

High Performance with Printed ElectronicsDARPA WNaNDARPA WNaN

Could be used as communicator

Significant advantage for first responders as wellMajor commercial interest in this capability for c ivilian applications

Courtesy of G Duchak

He stopped by the man in front of

me, pressed the button on his belt

that gave readings on his physicals.

"Fall out!"

The Future

"But, Sarge, it’s just a cold. The

Surgeon said — "

Robert Heinlein

Starship Troopers

1959

Urban Warfare ApplicationsUrban Warfare Applications

The urban arena generates serious communications problems due to multipath. Multiple antennas and transmitters can minimize these effects.

Flexible electronics multi-transmitter/antenna array hung on wall to provide infrastructure for unit communications.

Flexible electronics also provides spatial diversity for the individual soldier

With smart antennas, communications to forward units can also be improved by reducing multipath losses and using active beamforming

to increase gain toward higher headquarters while nulling out jammers and lowering signal

levels toward the enemy. Improved Forward

Unit Comms

65

for the individual soldier with radio embedded into the uniform. Flexible electronics “smart” antenna-transceiver

deployed as needed

Electronic Scanned Array and transmitters

Processor and display electronics

Foldable “pup tent” radar for alerting and cueing, mortar locating

Large aperture is a must!!

Thru the Wall Imaging


s

Sensor Craft

ISISJ-UCAS

Applications of Large Area Arrays

Air/Ground Surveillance

Missile Defense

Global Hawk SAR/GMTI

Unmanned Rotorcraft

Foliage Penetration GMTI

Space Based

Radar

Air Defense


Research Opportunities in Printed Electronics

Research Opportunities in Printed Electronics

Higher performance TFTs will enable control and

Higher Performance Enables Higher Performance Enables More ApplicationsMore Applicationswill enable control and

compute functions andRF in the 10s-100s of

MHz range.

More ApplicationsMore Applications

FPE: Creating the Technology FPE: Creating the Technology P

erfo

rman

ce (

log

Ft)

Si ICsTraditional Electronics

Thrust

Performance Driven

CompoundSemiconductors

Nanobundle TFT Technology

Impact

High Performance CapabilityMultifunctional StructuresCost Effective Technology

Possible System Form FactorsHigh Low

Per

form

ance

(lo

g F

αTFTs on Glass

DisplayIndustry(Cost Driven)

TFTs on Plastic

ImpactInexpensive pervasive electronics on large-area flexible surfaces can benefit applications where existing solutions are limited by space, weight, or cost constraints

Conformable, foldable, rollableLightweightCost Effective


THANK YOU

Bob Reuss14937 E. Sierra Madre Dr.Fountain Hills, AZ 85268

(480) 816-5559(480) 544-5409 (cell)

[email protected]

Documents

DARPA’S Microsystems Technology Office