DAQ/Trigger System proposalDAQ/Trigger System proposalfor the Angra Neutrino Detectorfor the Angra Neutrino Detector

Herman Lima Jr Herman Lima Jr

(18 May 2006)(18 May 2006)

Centro Brasileiro de Pesquisas FísicasCentro Brasileiro de Pesquisas Físicas

ScenarioScenario

• Neutrino detectionNeutrino detection• 128 PMTs• Data Acquisition and Trigger per channel• 150 s (max) window per event

• VETOVETO• 110 scintillators• Only Trigger

• CalibrationCalibration• VEM (Vertical Muon) • 60 channels (from the top and bottom VETO scintillators)• X&Y position decoding on top and bottom planes

Neutrino detection - block diagramNeutrino detection - block diagram

Analog-to-Digitalconversion

Signalconditioning

Buffers

Triggerlogic

Controllogic

VME bus

250 MSPSsample rate

10-bit resolution

2 ms

leading-edgediscriminators

high-speedFPGA(s)

PMT

integrated on the PMT base

Neutrino detection - buffersNeutrino detection - buffers

Signalconditioning

VME bus

PMT

ADC250MHz

front buffer

2 s

Controllogic

long buffer

2 ms

GPSreceiver

GPS Antenna

VETO

Triggerlogic

Neutrino detection - event timing Neutrino detection - event timing

Trigger_1 (positron) Trigger_2 (neutron)

150s event window

1st pulseto

long buffer(2s)

2nd pulseto

long buffer(2s)

4s window

verifying VETO

Long buffer capacity (per PMT channel):

ordinary situation: (1 event = 2 pulses) 4 s 500 events unusual situation: (1 event = 4 pulses) 8 s 250 events

Neutrino detection - buffer timing Neutrino detection - buffer timing Trigger_1 (positron)

clock

sample N

ADC out

trigger reg

4ns

t1

N

front buffer out N-500

t2=t1+20ns t3 start of transfer to long buffer

N-5 N+495

t4 end of transfer

2s

Neutrino detection - devicesNeutrino detection - devices

• Analog-to-Digital converter AD9230 250 MSPS 12 bits DNL = 0.3 LSB INL = 0.5 LSB 425 mW @ 250 MSPS

• FIFO (long buffer) IDT72T20128 524,288 x 10 250 MHz

• FPGA (logic) Stratix II – EP2S15 12,480 LUTs 419,328 bits RAM 275 MHz FIFO

Neutrino detection - module Neutrino detection - module

• standard: VME 6U

• one module:

16 ADC input channels @ 250 MHz

buffer size per channel = 524 s

• 128 PMT channels => 8 modules required

• dedicated lines on P2 to receive VETO

• interrupt requests to indicate ‘almost full’

condition

• control / status registers (e.g.: number of

events in a buffer)

ADC FPGA BUFFER

(16cm x 23cm)

front panel

P1

P2

VME bus

VETO system - block diagramVETO system - block diagram

FPGA

Signal Conditioning

Triggerlogic and control

VME bus

scintillator

Leading-edgediscrimination

front-endelectronics

VETO system - logicVETO system - logic

FPGA

TOPplane

trigger signals(LVDS)

BOTTOMplane

X(top) = X(bottom) ?

Y(top) = Y(bottom) ?

AROUNDvolume

scintillators

VEM flag

Any logic other flags

VETO system - moduleVETO system - module

FPGA

(16cm x 23cm)

front panel

P1

P2

LVD

S in

put

chan

nels

• Standard: VME 6U

• One module:

2 connectors on the front panel

68 LVDS input channels (total)

• LVDS receivers to reduce I/O pins in FPGA

• 110 scintillators 2 modules required

• 26 input channels free for new ideas

LVDSreceivers

LVDSreceivers

VME bus

DAQ/Trigger system - integrationDAQ/Trigger system - integration

VME bus

Analog-to-Digitalconversion

Signalconditioning

Buffers

Triggerlogic

Controllogic

128 PMTs

Signal Conditioning

Triggerlogic and control

110 scintillators

Leading-edgediscrimination

VETOVETONeutrino detectionNeutrino detection

DAQ/Trigger system - cost estimationDAQ/Trigger system - cost estimation

item part number descriptionunit qty total

(US$)   (US$)

1 AD9230BCPZ-250 ADC, 12 bits, 250 MSPS 77.00 128 9856.00

2 IDT72T20128L4BB FIFO, 524288 x 10 101.00 64 6464.00

3 EP2S15F484C5 FPGA Stratix II 243.59 64 15589.76

4 EP2C5F256C7 FPGA Cyclone II 25.00 10 250.00

5 Orcad Unison Ultra Suite CAD tool for system design 10130.71 1 10130.71

6 Quartus II CAD tool for logic design 3726.93 1 3726.93

7 Crate VME 6U + power supply   8300.00 1 8300.00

8 PCB manufacturing   1500.00 10 15000.00

      24104.23   69317.40

Included: 1 crate VME 6U, CAD tools, complex devices, PCB costs for 10 modules

Raw estimation !

Not included: other devices, cables, assembling, quality control of PCB ...

14

That’s all for now.Thanks.