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DAQ+trigger operationduring 2008 run
D. NicolòUniversity of Pisa & INFN, Pisa
April 20, 2023 2
Outlook
• DAQ– Data throughput & storage– Additional features– The slow control & alarms
• Trigger– Selection criteria– Efficiency & background rejection– Rates & Livetime
• DRS system– DRS2/3 performances– DRS4 design
• Improvements for 2009 run
DAQ+Trigger operation
DAQ
Data throughput and storage• Event & data rate
– 6.5 ev/s, ~9 MB/s (@normal run)– max. 30 ev/s (limited by VME readout & DRS2 calibration) current %Live ~ 80%
• Data write to online disk– 2000 events/run ~3 GB file size (smaller for calibration runs)
– occupancy ~ 1 TB/d 100 TB/y (to be offline suppressed x3) – Disk available with 2TB capability
• buffer for 2 days
• Data storage & monitoring– Lazy Logger process to
• automatic copy to offline cluster ( total 100 TB HD)
– gzip Midas data files (x0.5 compression)– Offline histos available soon afterwards (~ 10 min after Run stop)
April 20, 2023 DAQ+Trigger operation 4
Offlinecheck: an example
April 20, 2023 DAQ+Trigger operation 5
DAQ features• Automatic stop
– Maximum event number completion data size
• Run batch to be started from shell– Runsubmit xml script– Run parameters (#events, trigger operation, …)
loaded to the online database (ODB)
• System running smoothly • Major troubles
– Event “mismatch”– FE hangs up– FE still busy at run start
April 20, 2023 DAQ+Trigger operation 6
MSCB slow control
April 20, 2023 DAQ+Trigger operation 7
• 13 Ethernet “Submasters”• 8 SCS-2000 units each with up
to 64 I/O• Control of detector behaviour• Newly added features
• Separator HV• Beam shutter (beam on-off)
• Data recorder in the MIDAS history files available through the WEB page
• Alarm generation in the case of failures
Trigger
PSI - Jul. 18th, 2007 9
Selection criteriaQTHQTL
MeV
DWW
DWN
-energy e+- direction e+- timing
trig.# name conditions
0 MEG QSUM > QTH && D < DN && |T| < TWN
1 MEG-Q QSUM > QTL && D < DN && |T| < TWN
2 MEG-D QSUM > QTH && D < DW && |T| < TWN
3 MEG-T QSUM > QTH && D < DN && |T| < TWW
4 RD-narrow QSUM > QTL && |T| < TWN
5 RD-wide QSUM > QTL && |T| < TWW
April 20, 2023 11
On-line Eγ resolution
σ = 3.8%
45 MeV threshold
(@4 from signal)
55 MeV γ-line from π0-decay
April 20, 2023 12
Eγ efficiency• Obtained from the ratio SH(Eγ)/SL(Eγ) off-line energy spectra normalizated by using proton
current info
DAQ+Trigger operation
Threshold smearing mainly due to on-line energy resolution
ε 99%
0.5
counts
/s/M
eV FWHM = 9,4%
at 45 MeV
April 20, 2023 13
Δteγ efficiency
|ΔT (LXe-TC)| < 10 ns
Spectrum expected to be flat (accidental background)
σ(ΔT) = (3.8±0.1) ns εΔT ~ 99% (σt = 2.5 ns on each)
DAQ+Trigger operation
B(p,)C
(background free!)
Δt (ns)
–online –offline
TRG type 0
signal
April 20, 2023 14
e+-γ direction
- γ-position by max PMT in LXe
- e+-position by charge asymmetry in TC
(TC fibers not included yet)
– association LUT based on MC
Cross-check with the data (Radiative Decay sample)
a) Search for e+ “good quality” track candidates
(χ2, matched extrapolation to TC)
b) Track a backward hypothetical γ from decay vertex;
c) γ hit position LXe PMT index;
d) LXe PMT index search for e+-hit on TC in the LUT
DAQ+Trigger operation
Work in progress
DRS
DRS in 2008
• DRS2– All analog channels equipped
• 848 LXe PMTs• 60 TC PMTs• 1728 DC (anode + vernier)• 0.5 – 1.6 GHz sampling speed
– Voltage non-linearity calibration in FE– Temperature dependence 1.4%/oC
• DRS3– 4 cards available
• NIM TC DTD outputs
– Voltage linearity (0 : 1 V)– Ghost pulse problem to be fixed in DRS4
April 20, 2023 DAQ+Trigger operation 16
DRS2 linearity• Cell-dependent non-linear response function applied• Differential linearity restored at 2%
April 20, 2023 DAQ+Trigger operation 17
TRG amplitude
DR
S
am
plit
ud
e
Timing• Test done by splitting the same TC pulse to 2 channels of
the same chip
• Plot of (t0-t1)/2
negligible with respect to detector resolutionDifferent domino waves running on different chips
chip-to-chip timing needs calibration critical issue
April 20, 2023 DAQ+Trigger operation 18
rms = 6.6 psrms = 9.4 ps
DRS2 DRS3
DRS4 design• Same VME board as former versions• New mezzanine card
– Single ended differential input (common-noise suppression)
– Memory doubled • (up to 3.2 GHz sampling or 2x wider time window)
– All domino waves running synchronously (ref. CLK jitter < 10 ps)
– New DC supply at 2.5 V • compatibility with FPGA LVDS ref. CLK
April 20, 2023 DAQ+Trigger operation 19
Sept. 9th, 2008 MEG weekly meeting 20
DRS4 Schedule
• Add special clock chip for in-situ calibration• First prototype DRS4 mezzanine board end of February• Extend mezzanine firmware: Store calibration in
EEPROM, channel cascading (needed for 3.2 GSPS operation), in-situ timing calibration
• Test in area (March) with cosmics• Start mass production: 5-6 weeks ( end of May)• Deploy DRS4 boards in area: June• Use July as contingency
Further improvements in 2009
• Hardware– Test of the electronics chain by injecting a test pulse
from splitter output
• DAQ– No calibration needed for DRS4 DAQ speed-up
• Max. rate 30 50 ev/s, %Live 80% 90%
– Reduce dead time (6.5%) due to Start/Stop procedure• Subrun
– Fix residual troubles
• Trigger– Optimization of dynamic range
• might be a concern if LXe light yield increases
• DRS4
April 20, 2023 DAQ+Trigger operation 21
Backup slides
April 20, 2023 23
System overview
5 crates
DRSDRS
DRSDRS
DRSDRS
Hit registers
TriggerTrigger
Trigger
4 crates
20 MHz clock
clockstartstopsync
Trigger signalEvent numberTrigger type
Trigger
BusyError
Ancillarysystem
E5 area ‘cave’
PC (Linux)
PC (Linux)PC (Linux)PC (Linux)PC (Linux)
PC (Linux)
PC (Linux)PC (Linux)PC (Linux)
Front-End PCs
Run startRun stopTrigger config
MasterPC (Linux)
GigabitEthernet
On-line farm
PC (Linux)PC (Linux)PC (Linux)
storage
PC (Linux)
Event builder
DAQ+Trigger operation
DAQ scheme
April 20, 2023 DAQ+Trigger operation 24
TRG1 TRG2 TRG3 TRG9 DRS4 DRS5 DRS6 DRS7 DRS8
trigger & trigger type & event # LSB
busy
internal trigger & busy
SYSTEM01 SYSTEM02 SYSTEM03 SYSTEM04 SYSTEM05 SYSTEM06 SYSTEM07 SYSTEM08 SYSTEM09
Event Builder
SYSTEM
Logger
start sequencestop sequence
25
Event “mismatch”
TRG1 TRG2 TRG3 TRG9 DRS4 DRS5 DRS6 DRS7 DRS8
SYSTEM01 SYSTEM02 SYSTEM03 SYSTEM04 SYSTEM05 SYSTEM06 SYSTEM07 SYSTEM08 SYSTEM09
52 52 52 52 52 52 52 52 5252 52 52 52 52 51 52 52 52
HW event #SW serial #
50 50 50 50 50 50 50 50 5050 50 50 50 50 50 50 50 50
HW event #SW serial #
51 51 51 51 51 51 51 5151 51 51 51 51 51 51 51
HW event #SW serial #
Run stopped, error message returned by Event Builder
. . . 14 boards
14 x 48Type1Type1
Type116
4
Inner face(216 PMTs)
2 boards
. . . 5+4+2 boards
9 x 48
Type1Type1
Type116
4
Side faceslat. (144x2 PMTs) 4x1 back (216 PMTs) 4x1u/d (54x2 PMTs) 4x1
1 board
Bars(30x2 PMTs)
Fibers(512 APDs) 8x1
1 board
1 board
2 x48
Type2
Type2
Type2
Type2
Type2
. . . 8 boards
9 x 48Type1Type1
Type116
4
4 boards
1 x 48
Type1Type1
16
4
16Wires
64 channels
2 x48
2 x48
Type1
16NaI+pre-shower16 channels
The trigger tree
Type2
4 x 48
Type1
16CR counters32 channels Type1
16
1 board
2 boards
STARTSTOPCLKSYNC
Synchronous operation at 100 MHz
LXe
TC
DC
Aux
1 board
Rate monitor
April 20, 2023 DAQ+Trigger operation 27