D8042D SPEC - Power Mospowermos.com/Uploads/download/IC/D8042D SPEC.pdf · SR CV Mo ycle by the nce voltag is flowing the transf quation fo diode forw inding to 42D nics Limited wermos.com

REV：A0_J 2015-12-15

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REV：A0_J 2015-12-15

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REV：A0_J 2015-12-15

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REV：A0_J 2015-12-15

Electric

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REV：A0_J 2015-12-15

On-Chip

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REV：A0_J 2015-12-15

PERAT

D8042

Side Regu

high level

applicatio

System S

Before

allows a la

flowing th

voltage D

begins sw

hold-up ca

takes the

TION DE

2D is a hig

ulation (QR

protection

ns.

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e the IC st

arge value

rough the

C bus. Wh

witching an

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ESCRIP

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n features m

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startup res

hen VDD re

d the IC op

ontinues to

VDD volta

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ance, mult

ower switch

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sistor charg

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o supply VD

ge.

6

ti mode, hig

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uitable for

umes only

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urrent is in

DD before

Fig. 1

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minimize th

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n voltage o

creased to

the auxilia

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rated Quas

recision CV

all power c

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he power l

p capacitor

of 12V (typ

o be 0.8mA

ary winding

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si Resonan

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converter

cally 3uA) w

oss and th

r from the h

pical), D804

A (typical).

g of the tran

042D


nt Primary

rol with

which

he current

high

42D

The

nsformer

REV：A0_J 2015-12-15

Once

operating

power los

Quasi Re

In Prim

winding d

timing wa

(QR) trigg

sample/ho

Error Amp

(QR-CVM

the QR-CV

trimmed to

During

for Cable

demagnet

“demagne

voltage; R

Ns and Na

D8042D e

current is

ss.

esonant PS

mary Side

uring the t

veform of

ger signal i

old (S&H) c

plifier (EA)

M) for CV re

VM bock, w

o 2V with h

g the CV s

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tization pro

etization pl

R1 and R2

a are seco

enters very

reduced to

SR CV Mo

Regulation

ransfer of

CV sampli

n D8042D

circuit capt

. The outp

egulation. A

which is de

high accur

ampling pr

mpensation

ocess, as s

ateau”, wh

is the resis

ondary wind

y low frequ

o be 500uA

odulation (

n (PSR) co

transforme

ng signal,

. When the

tures the e

ut of EA is

A valley is

etermined

acy.

rocess, an

(CDC). Th

shown in F

here Vo an

stor divide

ding and a

7

ency FM (

A typically,

(QR-CVM)

ontrol, the

er energy t

demagnet

e CV samp

error signa

s sent to th

selected to

by the load

Fig. 2

internal va

hus, there

Fig.2. Fig.2

d VF is the

r connecte

auxiliary wi

Frequency

which hel

)

output volt

to the seco

tization sig

pling proce

l and ampl

e Quasi Re

o trigger ne

d. The inter

ariable cur

is a step a

2 also illust

e output vo

ed from the

nding resp

Powe

y Modulatio

ps to redu

tage is sen

ondary. Fig

nal (DEM)

ess is over,

lifies it thro

esonant P

ew PWM c

rnal refere

rent source

at FB pin in

rates the e

oltage and

e auxiliary w

pectively.

D80


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ce the stan

nsed on the

g.2 illustrate

) and quas

, the intern

ough the in

SR CV Mo

cycle by the

nce voltag

e is flowing

n the transf

equation fo

diode forw

winding to

042D


the

ndby

e auxiliary

es the

i-resonant

nal

nternal

odulator

e output of

e for EA is

g to FB pin

former

or

ward

FB Pin,

f

s

n

REV：A0_J 2015-12-15

WhenEA output

PSR Con

Timing

regulation

increased

Ipp(max),

Refer

demagnet

average o

output cur

regulation

IC operate

output vol

keep VDD

In D80

average o

n heavy loat will switch

stant Cur

g informat

n of the sec

d in CV reg

as shown

ring to Fig

tization tim

output curr

rrent is sho

n reference

es in pulse

ltage at or

D above the

042D, the

output curr

ad conditioh to CC Mo

rent Modu

ion at the F

condary av

gulation and

in Fig.3.

.3 above, t

me (Tdem),

ent Iout. Ig

own in Fig.

e in the Prim

e frequency

below the

e UVLO tu

ratio betwe

ent can be

n, the Modode autom

ulation (PS

FB pin and

verage cur

d approach

the primary

, and switc

gnoring lea

.3. When t

mary Side

y modulatio

voltage re

urn-off thre

een Tdem

e expresse

8

de Selectormatically.

SR-CCM)

d current in

rent. The c

hing CC re

Fig.3

y peak cur

ching perio

akage indu

he average

Constant C

on (PFM) m

egulation ta

shold.

and Tsw i

d as:

r (as shown

nformation

control law

egulation th

rrent, trans

d (Tsw) de

ctance effe

e output cu

Current Mo

mode to co

arget as lon

n CC mod

Powe

n in “Block

at the CS

w dictates th

he primary

former turn

etermines t

ects, the e

urrent Iout

odulator (P

ontrol the o

ng as the a

e is 4/7. Th

D80


k Diagram”)

pin allow a

hat as pow

y peak curr

ns ratio, se

the second

quation for

reaches th

PSR-CCM)

output curr

auxiliary w

herefore, t

042D


) based on

accurate

wer is

ent is at

econdary

dary

r average

he

) block, the

rent at any

inding can

he

n

e

REV：A0_J 2015-12-15

In the

N----T

Rcs---

Multi Mod

To me

consumpt

adopted in

Aroun

conditions

efficiency

power red

Programm

In sm

a cable w

voltage. In

(modulate

proportion

Pout. The

from full lo

resistance

programm

equation a

The turn ra

- the sensi

de Contro

eet the tigh

tion, a hyb

n D8042D

nd the full l

s, the IC op

. When the

duction. In

mable Cab

art phone

ire which c

n D8042D,

ed by CDC

nal to the s

erefore, the

oading to z

e of R1 and

med. The p

above,

tio of prima

ng resistor

ol in CV Mo

ht requirem

rid of frequ

which is s

oad, the sy

perates in

e system is

this way, t

ble Drop C

charger ap

can cause

, an offset

block, as

switching p

e drop due

zero loadin

d R2 (as s

percentage

ary side wi

r connecte

ode

ment of ave

uency mod

shown in th

ystem ope

FM+AM m

s near zero

the no-load

Compensa

pplication,

several pe

voltage is

shown in F

period, thus

the cable

ng, the offs

hown in Fi

of maximu

9

inding to s

ed between

eraged sys

dulation (FM

he Fig 4.

rates in FM

mode to ach

o loading, t

d consump

Fig. 4

ation (CDC

the battery

ercentages

generated

Fig.5) flowi

s, it is inve

loss can b

set voltage

g.), the ca

um compe

econdary s

n the powe

stem efficie

M) and am

M mode. W

hieve exce

the IC ope

ption can b

4

C) in CV M

y is always

s of voltage

d at FB pin

ng into the

rsely propo

be compen

at FB pin w

ble loss co

ensation is

Powe

side windin

er BJT emit

ency and n

mplitude mo

When norm

ellent regul

rates in FM

e less than

Mode

s connecte

e drop on t

by an inte

e resistor d

ortional to

sated. As t

will increas

ompensatio

given by

D80


ng.

tter to GND

o load pow

odulation (A

mal to light l

ation and h

M again for

n 70mW.

d to the ad

the actual b

rnal curren

ivider. The

the output

the load de

se. By adju

on can be

042D


D.

wer

AM) is

load

high

r standby

dapter with

battery

nt source

e current is

t power

ecreases

usting the

h

s

REV：A0_J 2015-12-15

For ex

given by:

Optimize

In D80

requireme

On Chip T

When

temperatu

Audio No

As me

frequency

voltage m

CS peak v

loading to

xample, R1

d Dynami

042D, the

ents.

Thermal S

n the IC tem

ure drops t

oise Free O

entioned a

y modulatio

modulation.

voltage mo

o zero load

1=3K Ω ,

c Respon

dynamic re

Shutdown

mperature

to 140 ℃,

Operation

bove, the m

on. An inte

In D8042D

odulation a

ing.

R2=18K

se

esponse p

(OTP)

is over 155

IC will rest

multi-mode

rnal curren

D, the optim

algorithm c

10

Ω , The p

Fig. 5

erformanc

5 ℃, the I

tart.

e CV contr

nt source f

mized com

can provide

percentage

5

ce is optimi

C shuts do

rol with a h

flowing to C

mbination o

e audio noi

Powe

e of maximu

ized to me

own. Only w

hybrid of FM

CS pin rea

of frequenc

se free op

D80


um compe

et USB ch

when the I

M and AM

lizes CS p

cy modulati

eration fro

042D


ensation is

arge

IC

provides

eak

ion and

om full

REV：A0_J 2015-12-15

Dynamic

D8042

BJT base

according

based cur

Fig.6

Short Loa

In D80

UVP (0.65

In D80

Protection

VDD Ove

When

cause VD

restart up

damage.

BJT Base

2D drives a

drive curr

g to the pow

rrent. Spec

ad Protect

042D, the

5V typically

042D, whe

n (SLP) mo

er Voltage

n VDD volta

DD fall dow

again. An

e Drive

a power BJ

ent ranges

wer supply

cifically, the

tion (SLP)

output is s

y) after an

en sensed

ode, in whi

Protectio

age is high

wn to be low

internal 28

JT with dyn

s from 12m

y load chan

e base cur

)

sampled on

internal bl

FB voltage

ch the IC w

n (OVP) a

her than 26

wer than V

8V (typical

11

namic bas

mA to 35mA

nge. The h

rrent is rela

Fig.6

n FB pin an

anking tim

e is below

will enter in

nd Zener

6.5V (typica

DD_OFF (

l) zener cla

e drive con

A (typical),

igher the o

ated to CS

nd then co

me (10ms ty

0.6V, the I

nto auto re

Clamp

al), the IC

(typical 6.5

amp is inte

Powe

ntrol to opt

and is dyn

output pow

peak volta

mpared wi

ypical).

IC will ente

ecovery pro

will stop sw

5V) and the

egrated to p

D80


timize effic

namically c

wer, the hig

age, as sho

ith a thresh

er into Sho

otection mo

witching. T

en the syst

prevent the

042D


iency. The

controlled

her the

own in

hold of

ort Load

ode.

This will

tem will

e IC from

e

REV：A0_J 2015-12-15

PhysicSOP-7

Symbo

A A1 A2 b c D e

E1 E L θ

cal Dime

ol D

1.27

ensions

DimensionMin

1.350 0.100 1.350 0.330 0.170 4.700

70（BSC）

5.800

0.400 0º

s

ns In Millim

0

005

0.0506

3.800

12

meters Max 1.750 0.250 1.5500.5100.250 5.100 0（BSC）

6.200

1.270 8º

Powe

Dimensio

A A1 A2bc D e

E1 4

L θ

D80


ns In InchM

1.0.1.0.0.4.

1.2705.

.000 0.

042D


hes Min 350 100 350330170 700 （BSC）

800

400 0º

REV：A0_J 2015-12-15

日期

Date

2015-12

期

e

版

Ver

2-15 A0

版本

sion

0_J

说明

Descript

/

13

ion T

排版

Typeseting

Jasper

Powe

g

工程

Engi

/

D80


程师

ineer

/

042D


状态

Status

Active

Documents

D8042D SPEC - Power Mospowermos.com/Uploads/download/IC/D8042D SPEC.pdf · SR CV Mo ycle by the nce voltag is flowing the transf quation fo diode forw inding to 42D nics Limited wermos.com